linux/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
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   1/*
   2 * Broadcom NetXtreme-E RoCE driver.
   3 *
   4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6 *
   7 * This software is available to you under a choice of one of two
   8 * licenses.  You may choose to be licensed under the terms of the GNU
   9 * General Public License (GPL) Version 2, available from the file
  10 * COPYING in the main directory of this source tree, or the
  11 * BSD license below:
  12 *
  13 * Redistribution and use in source and binary forms, with or without
  14 * modification, are permitted provided that the following conditions
  15 * are met:
  16 *
  17 * 1. Redistributions of source code must retain the above copyright
  18 *    notice, this list of conditions and the following disclaimer.
  19 * 2. Redistributions in binary form must reproduce the above copyright
  20 *    notice, this list of conditions and the following disclaimer in
  21 *    the documentation and/or other materials provided with the
  22 *    distribution.
  23 *
  24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 *
  36 * Description: RDMA Controller HW interface (header)
  37 */
  38
  39#ifndef __BNXT_QPLIB_RCFW_H__
  40#define __BNXT_QPLIB_RCFW_H__
  41
  42#define RCFW_CMDQ_TRIG_VAL              1
  43#define RCFW_COMM_PCI_BAR_REGION        0
  44#define RCFW_COMM_CONS_PCI_BAR_REGION   2
  45#define RCFW_COMM_BASE_OFFSET           0x600
  46#define RCFW_PF_COMM_PROD_OFFSET        0xc
  47#define RCFW_VF_COMM_PROD_OFFSET        0xc
  48#define RCFW_COMM_TRIG_OFFSET           0x100
  49#define RCFW_COMM_SIZE                  0x104
  50
  51#define RCFW_DBR_PCI_BAR_REGION         2
  52#define RCFW_DBR_BASE_PAGE_SHIFT        12
  53
  54#define RCFW_CMD_PREP(req, CMD, cmd_flags)                              \
  55        do {                                                            \
  56                memset(&(req), 0, sizeof((req)));                       \
  57                (req).opcode = CMDQ_BASE_OPCODE_##CMD;                  \
  58                (req).cmd_size = (sizeof((req)) +                       \
  59                                BNXT_QPLIB_CMDQE_UNITS - 1) /           \
  60                                BNXT_QPLIB_CMDQE_UNITS;                 \
  61                (req).flags = cpu_to_le16(cmd_flags);                   \
  62        } while (0)
  63
  64#define RCFW_CMD_WAIT_TIME_MS           20000 /* 20 Seconds timeout */
  65
  66/* Cmdq contains a fix number of a 16-Byte slots */
  67struct bnxt_qplib_cmdqe {
  68        u8              data[16];
  69};
  70
  71/* CMDQ elements */
  72#define BNXT_QPLIB_CMDQE_MAX_CNT_256    256
  73#define BNXT_QPLIB_CMDQE_MAX_CNT_8192   8192
  74#define BNXT_QPLIB_CMDQE_UNITS          sizeof(struct bnxt_qplib_cmdqe)
  75#define BNXT_QPLIB_CMDQE_BYTES(depth)   ((depth) * BNXT_QPLIB_CMDQE_UNITS)
  76
  77static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
  78{
  79        u32 npages;
  80
  81        npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
  82        if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
  83                npages++;
  84        return npages;
  85}
  86
  87static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
  88{
  89        return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
  90}
  91
  92static inline u32 bnxt_qplib_cmdqe_cnt_per_pg(u32 depth)
  93{
  94        return (bnxt_qplib_cmdqe_page_size(depth) /
  95                 BNXT_QPLIB_CMDQE_UNITS);
  96}
  97
  98#define MAX_CMDQ_IDX(depth)             ((depth) - 1)
  99
 100static inline u32 bnxt_qplib_max_cmdq_idx_per_pg(u32 depth)
 101{
 102        return (bnxt_qplib_cmdqe_cnt_per_pg(depth) - 1);
 103}
 104
 105#define RCFW_MAX_COOKIE_VALUE           0x7FFF
 106#define RCFW_CMD_IS_BLOCKING            0x8000
 107#define RCFW_BLOCKED_CMD_WAIT_COUNT     0x4E20
 108
 109#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
 110
 111static inline u32 get_cmdq_pg(u32 val, u32 depth)
 112{
 113        return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) /
 114                (bnxt_qplib_cmdqe_cnt_per_pg(depth));
 115}
 116
 117static inline u32 get_cmdq_idx(u32 val, u32 depth)
 118{
 119        return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth));
 120}
 121
 122/* Crsq buf is 1024-Byte */
 123struct bnxt_qplib_crsbe {
 124        u8                      data[1024];
 125};
 126
 127/* CREQ */
 128/* Allocate 1 per QP for async error notification for now */
 129#define BNXT_QPLIB_CREQE_MAX_CNT        (64 * 1024)
 130#define BNXT_QPLIB_CREQE_UNITS          16      /* 16-Bytes per prod unit */
 131#define BNXT_QPLIB_CREQE_CNT_PER_PG     (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
 132
 133#define MAX_CREQ_IDX                    (BNXT_QPLIB_CREQE_MAX_CNT - 1)
 134#define MAX_CREQ_IDX_PER_PG             (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
 135
 136static inline u32 get_creq_pg(u32 val)
 137{
 138        return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
 139}
 140
 141static inline u32 get_creq_idx(u32 val)
 142{
 143        return val & MAX_CREQ_IDX_PER_PG;
 144}
 145
 146#define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
 147
 148#define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)                   \
 149        (!!((hdr)->v & CREQ_BASE_V) ==                          \
 150           !((raw_cons) & (cp_bit)))
 151
 152#define CREQ_DB_KEY_CP                  (0x2 << CMPL_DOORBELL_KEY_SFT)
 153#define CREQ_DB_IDX_VALID               CMPL_DOORBELL_IDX_VALID
 154#define CREQ_DB_IRQ_DIS                 CMPL_DOORBELL_MASK
 155#define CREQ_DB_CP_FLAGS_REARM          (CREQ_DB_KEY_CP |       \
 156                                         CREQ_DB_IDX_VALID)
 157#define CREQ_DB_CP_FLAGS                (CREQ_DB_KEY_CP |       \
 158                                         CREQ_DB_IDX_VALID |    \
 159                                         CREQ_DB_IRQ_DIS)
 160#define CREQ_DB_REARM(db, raw_cons, cp_bit)                     \
 161        writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
 162#define CREQ_DB(db, raw_cons, cp_bit)                           \
 163        writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
 164
 165#define CREQ_ENTRY_POLL_BUDGET          0x100
 166
 167/* HWQ */
 168
 169struct bnxt_qplib_crsq {
 170        struct creq_qp_event    *resp;
 171        u32                     req_size;
 172};
 173
 174struct bnxt_qplib_rcfw_sbuf {
 175        void *sb;
 176        dma_addr_t dma_addr;
 177        u32 size;
 178};
 179
 180struct bnxt_qplib_qp_node {
 181        u32 qp_id;              /* QP id */
 182        void *qp_handle;        /* ptr to qplib_qp */
 183};
 184
 185#define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
 186
 187/* RCFW Communication Channels */
 188struct bnxt_qplib_rcfw {
 189        struct pci_dev          *pdev;
 190        int                     vector;
 191        struct tasklet_struct   worker;
 192        bool                    requested;
 193        unsigned long           *cmdq_bitmap;
 194        u32                     bmap_size;
 195        unsigned long           flags;
 196#define FIRMWARE_INITIALIZED_FLAG       0
 197#define FIRMWARE_FIRST_FLAG             31
 198#define FIRMWARE_TIMED_OUT              3
 199        wait_queue_head_t       waitq;
 200        int                     (*aeq_handler)(struct bnxt_qplib_rcfw *,
 201                                               void *, void *);
 202        u32                     seq_num;
 203
 204        /* Bar region info */
 205        void __iomem            *cmdq_bar_reg_iomem;
 206        u16                     cmdq_bar_reg;
 207        u16                     cmdq_bar_reg_prod_off;
 208        u16                     cmdq_bar_reg_trig_off;
 209        u16                     creq_ring_id;
 210        u16                     creq_bar_reg;
 211        void __iomem            *creq_bar_reg_iomem;
 212
 213        /* Cmd-Resp and Async Event notification queue */
 214        struct bnxt_qplib_hwq   creq;
 215        u64                     creq_qp_event_processed;
 216        u64                     creq_func_event_processed;
 217
 218        /* Actual Cmd and Resp Queues */
 219        struct bnxt_qplib_hwq   cmdq;
 220        struct bnxt_qplib_crsq  *crsqe_tbl;
 221        int qp_tbl_size;
 222        struct bnxt_qplib_qp_node *qp_tbl;
 223        u64 oos_prev;
 224        u32 init_oos_stats;
 225        u32 cmdq_depth;
 226};
 227
 228void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 229int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
 230                                  struct bnxt_qplib_rcfw *rcfw,
 231                                  struct bnxt_qplib_ctx *ctx,
 232                                  int qp_tbl_sz);
 233void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
 234void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 235int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
 236                              bool need_init);
 237int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
 238                                   struct bnxt_qplib_rcfw *rcfw,
 239                                   int msix_vector,
 240                                   int cp_bar_reg_off, int virt_fn,
 241                                   int (*aeq_handler)(struct bnxt_qplib_rcfw *,
 242                                                      void *aeqe, void *obj));
 243
 244struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
 245                                struct bnxt_qplib_rcfw *rcfw,
 246                                u32 size);
 247void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
 248                               struct bnxt_qplib_rcfw_sbuf *sbuf);
 249int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
 250                                 struct cmdq_base *req, struct creq_base *resp,
 251                                 void *sbuf, u8 is_block);
 252
 253int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
 254int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
 255                         struct bnxt_qplib_ctx *ctx, int is_virtfn);
 256void bnxt_qplib_mark_qp_error(void *qp_handle);
 257#endif /* __BNXT_QPLIB_RCFW_H__ */
 258