1#ifndef _HFI1_KERNEL_H
2#define _HFI1_KERNEL_H
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#include <linux/interrupt.h>
51#include <linux/pci.h>
52#include <linux/dma-mapping.h>
53#include <linux/mutex.h>
54#include <linux/list.h>
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/idr.h>
58#include <linux/io.h>
59#include <linux/fs.h>
60#include <linux/completion.h>
61#include <linux/kref.h>
62#include <linux/sched.h>
63#include <linux/cdev.h>
64#include <linux/delay.h>
65#include <linux/kthread.h>
66#include <linux/i2c.h>
67#include <linux/i2c-algo-bit.h>
68#include <rdma/ib_hdrs.h>
69#include <rdma/opa_addr.h>
70#include <linux/rhashtable.h>
71#include <linux/netdevice.h>
72#include <rdma/rdma_vt.h>
73
74#include "chip_registers.h"
75#include "common.h"
76#include "verbs.h"
77#include "pio.h"
78#include "chip.h"
79#include "mad.h"
80#include "qsfp.h"
81#include "platform.h"
82#include "affinity.h"
83#include "msix.h"
84
85
86#define HFI1_CHIP_VERS_MAJ 3U
87
88
89#define HFI1_CHIP_VERS_MIN 0U
90
91
92#define HFI1_OUI 0x001175
93#define HFI1_OUI_LSB 40
94
95#define DROP_PACKET_OFF 0
96#define DROP_PACKET_ON 1
97
98#define NEIGHBOR_TYPE_HFI 0
99#define NEIGHBOR_TYPE_SWITCH 1
100
101extern unsigned long hfi1_cap_mask;
102#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
103#define HFI1_CAP_UGET_MASK(mask, cap) \
104 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
105#define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
106#define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
107#define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
108#define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
109#define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
110 HFI1_CAP_MISC_MASK)
111
112#define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
113
114
115
116
117
118#define HFI1_CTRL_CTXT 0
119
120
121
122
123
124#define NUM_CCE_ERR_STATUS_COUNTERS 41
125#define NUM_RCV_ERR_STATUS_COUNTERS 64
126#define NUM_MISC_ERR_STATUS_COUNTERS 13
127#define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
128#define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
129#define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
130#define NUM_SEND_ERR_STATUS_COUNTERS 3
131#define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
132#define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
133
134
135
136
137
138
139
140
141
142struct hfi1_ib_stats {
143 __u64 sps_ints;
144 __u64 sps_errints;
145 __u64 sps_txerrs;
146 __u64 sps_rcverrs;
147 __u64 sps_hwerrs;
148 __u64 sps_nopiobufs;
149 __u64 sps_ctxts;
150 __u64 sps_lenerrs;
151 __u64 sps_buffull;
152 __u64 sps_hdrfull;
153};
154
155extern struct hfi1_ib_stats hfi1_stats;
156extern const struct pci_error_handlers hfi1_pci_err_handler;
157
158extern int num_driver_cntrs;
159
160
161
162
163
164
165
166#define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
167
168
169
170
171
172struct hfi1_opcode_stats_perctx;
173
174struct ctxt_eager_bufs {
175 struct eager_buffer {
176 void *addr;
177 dma_addr_t dma;
178 ssize_t len;
179 } *buffers;
180 struct {
181 void *addr;
182 dma_addr_t dma;
183 } *rcvtids;
184 u32 size;
185 u32 rcvtid_size;
186 u16 count;
187 u16 numbufs;
188 u16 alloced;
189 u16 threshold;
190};
191
192struct exp_tid_set {
193 struct list_head list;
194 u32 count;
195};
196
197typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
198struct hfi1_ctxtdata {
199
200 void *rcvhdrq;
201
202 volatile __le64 *rcvhdrtail_kvaddr;
203
204 struct hfi1_pportdata *ppd;
205
206 struct hfi1_devdata *dd;
207
208 struct send_context *sc;
209
210 const rhf_rcv_function_ptr *rhf_rcv_function_map;
211
212
213
214
215
216
217
218 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
219
220 struct hfi1_opcode_stats_perctx *opstats;
221
222 u64 imask;
223
224 u32 head;
225
226 u16 rcvhdrq_cnt;
227 u8 ireg;
228
229 u8 seq_cnt;
230
231 u8 rcvhdrqentsize;
232
233 u8 rhf_offset;
234
235 u8 rcvavail_timeout;
236
237 bool is_vnic;
238
239 u8 vnic_q_idx;
240
241 bool aspm_intr_supported;
242
243 bool aspm_enabled;
244
245 bool aspm_intr_enable;
246 struct ctxt_eager_bufs egrbufs;
247
248 struct list_head qp_wait_list;
249
250 struct exp_tid_set tid_group_list;
251 struct exp_tid_set tid_used_list;
252 struct exp_tid_set tid_full_list;
253
254
255 struct timer_list aspm_timer;
256
257 unsigned long flags;
258
259 struct tid_group *groups;
260
261 dma_addr_t rcvhdrq_dma;
262 dma_addr_t rcvhdrqtailaddr_dma;
263
264 ktime_t aspm_ts_last_intr;
265
266 ktime_t aspm_ts_timer_sched;
267
268 spinlock_t aspm_lock;
269
270 struct kref kref;
271
272 int numa_id;
273
274 s16 msix_intr;
275
276 u16 jkey;
277
278 u16 rcv_array_groups;
279
280 u16 eager_base;
281
282 u16 expected_count;
283
284 u16 expected_base;
285
286 u8 ctxt;
287
288
289
290 struct mutex exp_mutex;
291
292 wait_queue_head_t wait;
293
294 u8 uuid[16];
295
296 char comm[TASK_COMM_LEN];
297
298 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
299
300 unsigned long event_flags;
301
302 void *subctxt_uregbase;
303
304 void *subctxt_rcvegrbuf;
305
306 void *subctxt_rcvhdr_base;
307
308 u32 urgent;
309
310 u32 urgent_poll;
311
312 u16 poll_type;
313
314 u16 subctxt_id;
315
316 u32 userversion;
317
318
319
320
321 u8 subctxt_cnt;
322
323};
324
325
326
327
328
329
330
331
332static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
333{
334 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
335 rcd->rcvhdrqentsize * sizeof(u32));
336}
337
338
339
340
341
342
343
344
345struct hfi1_packet {
346 void *ebuf;
347 void *hdr;
348 void *payload;
349 struct hfi1_ctxtdata *rcd;
350 __le32 *rhf_addr;
351 struct rvt_qp *qp;
352 struct ib_other_headers *ohdr;
353 struct ib_grh *grh;
354 struct opa_16b_mgmt *mgmt;
355 u64 rhf;
356 u32 maxcnt;
357 u32 rhqoff;
358 u32 dlid;
359 u32 slid;
360 u16 tlen;
361 s16 etail;
362 u16 pkey;
363 u8 hlen;
364 u8 numpkt;
365 u8 rsize;
366 u8 updegr;
367 u8 etype;
368 u8 extra_byte;
369 u8 pad;
370 u8 sc;
371 u8 sl;
372 u8 opcode;
373 bool migrated;
374};
375
376
377#define HFI1_PKT_TYPE_9B 0
378#define HFI1_PKT_TYPE_16B 1
379
380
381
382
383#define OPA_16B_L4_MASK 0xFFull
384#define OPA_16B_SC_MASK 0x1F00000ull
385#define OPA_16B_SC_SHIFT 20
386#define OPA_16B_LID_MASK 0xFFFFFull
387#define OPA_16B_DLID_MASK 0xF000ull
388#define OPA_16B_DLID_SHIFT 20
389#define OPA_16B_DLID_HIGH_SHIFT 12
390#define OPA_16B_SLID_MASK 0xF00ull
391#define OPA_16B_SLID_SHIFT 20
392#define OPA_16B_SLID_HIGH_SHIFT 8
393#define OPA_16B_BECN_MASK 0x80000000ull
394#define OPA_16B_BECN_SHIFT 31
395#define OPA_16B_FECN_MASK 0x10000000ull
396#define OPA_16B_FECN_SHIFT 28
397#define OPA_16B_L2_MASK 0x60000000ull
398#define OPA_16B_L2_SHIFT 29
399#define OPA_16B_PKEY_MASK 0xFFFF0000ull
400#define OPA_16B_PKEY_SHIFT 16
401#define OPA_16B_LEN_MASK 0x7FF00000ull
402#define OPA_16B_LEN_SHIFT 20
403#define OPA_16B_RC_MASK 0xE000000ull
404#define OPA_16B_RC_SHIFT 25
405#define OPA_16B_AGE_MASK 0xFF0000ull
406#define OPA_16B_AGE_SHIFT 16
407#define OPA_16B_ENTROPY_MASK 0xFFFFull
408
409
410
411
412#define OPA_16B_L4_9B 0x00
413#define OPA_16B_L2_TYPE 0x02
414#define OPA_16B_L4_FM 0x08
415#define OPA_16B_L4_IB_LOCAL 0x09
416#define OPA_16B_L4_IB_GLOBAL 0x0A
417#define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
418
419
420
421
422#define OPA_16B_L4_FM_PAD 3
423#define OPA_16B_L4_FM_HLEN 24
424
425static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
426{
427 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
428}
429
430static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
431{
432 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
433}
434
435static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
436{
437 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
438 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
439 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
440}
441
442static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
443{
444 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
445 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
446 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
447}
448
449static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
450{
451 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
452}
453
454static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
455{
456 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
457}
458
459static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
460{
461 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
462}
463
464static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
465{
466 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
467}
468
469static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
470{
471 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
472}
473
474static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
475{
476 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
477}
478
479static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
480{
481 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
482}
483
484static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
485{
486 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
487}
488
489#define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
490
491
492
493
494#define OPA_16B_BTH_PAD_MASK 7
495static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
496{
497 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
498 OPA_16B_BTH_PAD_MASK);
499}
500
501
502
503
504#define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
505static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
506{
507 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
508}
509
510static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
511{
512 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
513}
514
515static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
516 u32 dest_qp, u32 src_qp)
517{
518 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
519 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
520}
521
522struct rvt_sge_state;
523
524
525
526
527
528
529#define HFI1_IB_CFG_LIDLMC 0
530#define HFI1_IB_CFG_LWID_DG_ENB 1
531#define HFI1_IB_CFG_LWID_ENB 2
532#define HFI1_IB_CFG_LWID 3
533#define HFI1_IB_CFG_SPD_ENB 4
534#define HFI1_IB_CFG_SPD 5
535#define HFI1_IB_CFG_RXPOL_ENB 6
536#define HFI1_IB_CFG_LREV_ENB 7
537#define HFI1_IB_CFG_LINKLATENCY 8
538#define HFI1_IB_CFG_HRTBT 9
539#define HFI1_IB_CFG_OP_VLS 10
540#define HFI1_IB_CFG_VL_HIGH_CAP 11
541#define HFI1_IB_CFG_VL_LOW_CAP 12
542#define HFI1_IB_CFG_OVERRUN_THRESH 13
543#define HFI1_IB_CFG_PHYERR_THRESH 14
544#define HFI1_IB_CFG_LINKDEFAULT 15
545#define HFI1_IB_CFG_PKEYS 16
546#define HFI1_IB_CFG_MTU 17
547#define HFI1_IB_CFG_VL_HIGH_LIMIT 19
548#define HFI1_IB_CFG_PMA_TICKS 20
549#define HFI1_IB_CFG_PORT 21
550
551
552
553
554
555
556
557
558
559#define __HLS_UP_INIT_BP 0
560#define __HLS_UP_ARMED_BP 1
561#define __HLS_UP_ACTIVE_BP 2
562#define __HLS_DN_DOWNDEF_BP 3
563#define __HLS_DN_POLL_BP 4
564#define __HLS_DN_DISABLE_BP 5
565#define __HLS_DN_OFFLINE_BP 6
566#define __HLS_VERIFY_CAP_BP 7
567#define __HLS_GOING_UP_BP 8
568#define __HLS_GOING_OFFLINE_BP 9
569#define __HLS_LINK_COOLDOWN_BP 10
570
571#define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
572#define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
573#define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
574#define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP)
575#define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
576#define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
577#define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
578#define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
579#define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
580#define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
581#define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
582
583#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
584#define HLS_DOWN ~(HLS_UP)
585
586#define HLS_DEFAULT HLS_DN_POLL
587
588
589#define HFI1_DEFAULT_ACTIVE_MTU 10240
590
591#define HFI1_DEFAULT_MAX_MTU 10240
592
593#define DEFAULT_PKEY 0xffff
594
595
596
597
598#define FM_TBL_VL_HIGH_ARB 1
599#define FM_TBL_VL_LOW_ARB 2
600#define FM_TBL_BUFFER_CONTROL 3
601#define FM_TBL_SC2VLNT 4
602#define FM_TBL_VL_PREEMPT_ELEMS 5
603#define FM_TBL_VL_PREEMPT_MATRIX 6
604
605
606
607
608
609
610#define HFI1_RCVCTRL_TAILUPD_ENB 0x01
611#define HFI1_RCVCTRL_TAILUPD_DIS 0x02
612#define HFI1_RCVCTRL_CTXT_ENB 0x04
613#define HFI1_RCVCTRL_CTXT_DIS 0x08
614#define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
615#define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
616#define HFI1_RCVCTRL_PKEY_ENB 0x40
617#define HFI1_RCVCTRL_PKEY_DIS 0x80
618#define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
619#define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
620#define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
621#define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
622#define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
623#define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
624#define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
625#define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
626#define HFI1_RCVCTRL_URGENT_ENB 0x40000
627#define HFI1_RCVCTRL_URGENT_DIS 0x80000
628
629
630#define HFI1_PART_ENFORCE_IN 0x1
631#define HFI1_PART_ENFORCE_OUT 0x2
632
633
634#define SYNTH_CNT_TIME 3
635
636
637#define CNTR_NORMAL 0x0
638#define CNTR_SYNTH 0x1
639#define CNTR_DISABLED 0x2
640#define CNTR_32BIT 0x4
641#define CNTR_VL 0x8
642#define CNTR_SDMA 0x10
643#define CNTR_INVALID_VL -1
644#define CNTR_MODE_W 0x0
645#define CNTR_MODE_R 0x1
646
647
648#define HFI1_MIN_VLS_SUPPORTED 1
649#define HFI1_MAX_VLS_SUPPORTED 8
650
651#define HFI1_GUIDS_PER_PORT 5
652#define HFI1_PORT_GUID_INDEX 0
653
654static inline void incr_cntr64(u64 *cntr)
655{
656 if (*cntr < (u64)-1LL)
657 (*cntr)++;
658}
659
660static inline void incr_cntr32(u32 *cntr)
661{
662 if (*cntr < (u32)-1LL)
663 (*cntr)++;
664}
665
666#define MAX_NAME_SIZE 64
667struct hfi1_msix_entry {
668 enum irq_type type;
669 int irq;
670 void *arg;
671 cpumask_t mask;
672 struct irq_affinity_notify notify;
673};
674
675struct hfi1_msix_info {
676
677 spinlock_t msix_lock;
678 DECLARE_BITMAP(in_use_msix, CCE_NUM_MSIX_VECTORS);
679 struct hfi1_msix_entry *msix_entries;
680 u16 max_requested;
681};
682
683
684struct cca_timer {
685 struct hrtimer hrtimer;
686 struct hfi1_pportdata *ppd;
687 int sl;
688 u16 ccti;
689};
690
691struct link_down_reason {
692
693
694
695
696 u8 sma;
697 u8 latest;
698};
699
700enum {
701 LO_PRIO_TABLE,
702 HI_PRIO_TABLE,
703 MAX_PRIO_TABLE
704};
705
706struct vl_arb_cache {
707
708 spinlock_t lock;
709 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
710};
711
712
713
714
715
716
717
718struct hfi1_pportdata {
719 struct hfi1_ibport ibport_data;
720
721 struct hfi1_devdata *dd;
722 struct kobject pport_cc_kobj;
723 struct kobject sc2vl_kobj;
724 struct kobject sl2sc_kobj;
725 struct kobject vl2mtu_kobj;
726
727
728 struct qsfp_data qsfp_info;
729
730 u32 port_type;
731 u32 tx_preset_eq;
732 u32 tx_preset_noeq;
733 u32 rx_preset;
734 u8 local_atten;
735 u8 remote_atten;
736 u8 default_atten;
737 u8 max_power_class;
738
739
740 bool config_from_scratch;
741
742
743 u64 guids[HFI1_GUIDS_PER_PORT];
744
745
746 u64 neighbor_guid;
747
748
749 u32 linkup;
750
751
752
753
754
755 u64 *statusp;
756
757
758
759 struct workqueue_struct *hfi1_wq;
760 struct workqueue_struct *link_wq;
761
762
763 struct work_struct link_vc_work;
764 struct work_struct link_up_work;
765 struct work_struct link_down_work;
766 struct work_struct sma_message_work;
767 struct work_struct freeze_work;
768 struct work_struct link_downgrade_work;
769 struct work_struct link_bounce_work;
770 struct delayed_work start_link_work;
771
772 struct mutex hls_lock;
773 u32 host_link_state;
774
775
776
777 u32 ibmtu;
778
779
780
781
782 u32 ibmaxlen;
783 u32 current_egress_rate;
784
785 u32 lid;
786
787 u16 pkeys[MAX_PKEY_VALUES];
788 u16 link_width_supported;
789 u16 link_width_downgrade_supported;
790 u16 link_speed_supported;
791 u16 link_width_enabled;
792 u16 link_width_downgrade_enabled;
793 u16 link_speed_enabled;
794 u16 link_width_active;
795 u16 link_width_downgrade_tx_active;
796 u16 link_width_downgrade_rx_active;
797 u16 link_speed_active;
798 u8 vls_supported;
799 u8 vls_operational;
800 u8 actual_vls_operational;
801
802 u8 lmc;
803
804 u8 rx_pol_inv;
805
806 u8 hw_pidx;
807 u8 port;
808
809 u8 neighbor_type;
810 u8 neighbor_normal;
811 u8 neighbor_fm_security;
812 u8 neighbor_port_number;
813 u8 is_sm_config_started;
814 u8 offline_disabled_reason;
815 u8 is_active_optimize_enabled;
816 u8 driver_link_ready;
817 u8 link_enabled;
818 u8 linkinit_reason;
819 u8 local_tx_rate;
820 u8 qsfp_retry_count;
821
822
823 u8 overrun_threshold;
824 u8 phy_error_threshold;
825 unsigned int is_link_down_queued;
826
827
828
829
830
831
832 unsigned long led_override_vals[2];
833 u8 led_override_phase;
834 atomic_t led_override_timer_active;
835
836 struct timer_list led_override_timer;
837
838 u32 sm_trap_qp;
839 u32 sa_qp;
840
841
842
843
844
845 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
846 struct cca_timer cca_timer[OPA_MAX_SLS];
847
848
849 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
850
851
852 struct opa_congestion_setting_entry_shadow
853 congestion_entries[OPA_MAX_SLS];
854
855
856
857
858
859 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
860
861 struct cc_state __rcu *cc_state;
862
863
864 u16 total_cct_entry;
865
866
867 u32 cc_sl_control_map;
868
869
870 u8 cc_max_table_entries;
871
872
873
874
875
876 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
877 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
878 u16 threshold_event_counter;
879 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
880 int cc_log_idx;
881 int cc_mad_idx;
882
883
884 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
885
886
887 u64 *cntrs;
888
889 u64 *scntrs;
890
891 u64 port_xmit_discards;
892 u64 port_xmit_discards_vl[C_VL_COUNT];
893 u64 port_xmit_constraint_errors;
894 u64 port_rcv_constraint_errors;
895
896 u64 link_downed;
897
898 u64 link_up;
899
900 u64 unknown_frame_count;
901
902 u16 port_ltp_crc_mode;
903
904 u8 port_crc_mode_enabled;
905
906 u8 mgmt_allowed;
907 u8 part_enforce;
908 struct link_down_reason local_link_down_reason;
909 struct link_down_reason neigh_link_down_reason;
910
911 u8 remote_link_down_reason;
912
913 u32 port_error_action;
914 struct work_struct linkstate_active_work;
915
916 bool cc_prescan;
917
918
919
920
921 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
922 u16 prev_link_width;
923 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
924};
925
926typedef void (*opcode_handler)(struct hfi1_packet *packet);
927typedef void (*hfi1_make_req)(struct rvt_qp *qp,
928 struct hfi1_pkt_state *ps,
929 struct rvt_swqe *wqe);
930extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
931
932
933
934#define RHF_RCV_CONTINUE 0
935#define RHF_RCV_DONE 1
936#define RHF_RCV_REPROCESS 2
937
938struct rcv_array_data {
939 u16 ngroups;
940 u16 nctxt_extra;
941 u8 group_size;
942};
943
944struct per_vl_data {
945 u16 mtu;
946 struct send_context *sc;
947};
948
949
950#define PER_VL_SEND_CONTEXTS 16
951
952struct err_info_rcvport {
953 u8 status_and_code;
954 u64 packet_flit1;
955 u64 packet_flit2;
956};
957
958struct err_info_constraint {
959 u8 status;
960 u16 pkey;
961 u32 slid;
962};
963
964struct hfi1_temp {
965 unsigned int curr;
966 unsigned int lo_lim;
967 unsigned int hi_lim;
968 unsigned int crit_lim;
969 u8 triggers;
970};
971
972struct hfi1_i2c_bus {
973 struct hfi1_devdata *controlling_dd;
974 struct i2c_adapter adapter;
975 struct i2c_algo_bit_data algo;
976 int num;
977};
978
979
980struct hfi1_asic_data {
981 struct hfi1_devdata *dds[2];
982 struct mutex asic_resource_mutex;
983 struct hfi1_i2c_bus *i2c_bus0;
984 struct hfi1_i2c_bus *i2c_bus1;
985};
986
987
988#define NUM_MAP_ENTRIES 256
989#define NUM_MAP_REGS 32
990
991
992
993
994
995#define HFI1_NUM_VNIC_CTXT 8
996
997
998#define NUM_VNIC_MAP_ENTRIES 8
999
1000
1001struct hfi1_vnic_data {
1002 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
1003 struct kmem_cache *txreq_cache;
1004 u8 num_vports;
1005 struct idr vesw_idr;
1006 u8 rmt_start;
1007 u8 num_ctxt;
1008};
1009
1010struct hfi1_vnic_vport_info;
1011
1012
1013
1014
1015struct sdma_engine;
1016struct sdma_vl_map;
1017
1018#define BOARD_VERS_MAX 96
1019#define SERIAL_MAX 16
1020
1021typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
1022struct hfi1_devdata {
1023 struct hfi1_ibdev verbs_dev;
1024 struct list_head list;
1025
1026
1027 struct pci_dev *pcidev;
1028 struct cdev user_cdev;
1029 struct cdev diag_cdev;
1030 struct cdev ui_cdev;
1031 struct device *user_device;
1032 struct device *diag_device;
1033 struct device *ui_device;
1034
1035
1036 u8 __iomem *kregbase1;
1037 resource_size_t physaddr;
1038
1039
1040 u8 __iomem *kregbase2;
1041
1042 u32 base2_start;
1043
1044
1045 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1046
1047 struct send_context_info *send_contexts;
1048
1049 u8 *hw_to_sw;
1050
1051 spinlock_t sc_lock;
1052
1053 spinlock_t pio_map_lock;
1054
1055 spinlock_t sc_init_lock;
1056
1057 spinlock_t sde_map_lock;
1058
1059 struct send_context **kernel_send_context;
1060
1061 struct pio_vl_map __rcu *pio_map;
1062
1063 u64 default_desc1;
1064
1065
1066
1067 volatile __le64 *sdma_heads_dma;
1068 dma_addr_t sdma_heads_phys;
1069 void *sdma_pad_dma;
1070 dma_addr_t sdma_pad_phys;
1071
1072 size_t sdma_heads_size;
1073
1074 u32 num_sdma;
1075
1076 struct sdma_engine *per_sdma;
1077
1078 struct sdma_vl_map __rcu *sdma_map;
1079
1080 wait_queue_head_t sdma_unfreeze_wq;
1081 atomic_t sdma_unfreeze_count;
1082
1083 u32 lcb_access_count;
1084
1085
1086 struct hfi1_asic_data *asic_data;
1087
1088
1089 void __iomem *piobase;
1090
1091
1092
1093
1094 void __iomem *rcvarray_wc;
1095
1096
1097
1098
1099 struct credit_return_base *cr_base;
1100
1101
1102 struct sc_config_sizes sc_sizes[SC_MAX];
1103
1104 char *boardname;
1105
1106
1107 u64 z_int_counter;
1108 u64 z_rcv_limit;
1109 u64 z_send_schedule;
1110
1111 u64 __percpu *send_schedule;
1112
1113 u16 num_vnic_contexts;
1114
1115 u32 num_rcv_contexts;
1116
1117 u32 num_send_contexts;
1118
1119
1120
1121 u32 freectxts;
1122
1123 u32 num_user_contexts;
1124
1125 u32 rcv_intr_timeout_csr;
1126
1127 spinlock_t sendctrl_lock;
1128 spinlock_t rcvctrl_lock;
1129 spinlock_t uctxt_lock;
1130 struct mutex dc8051_lock;
1131 struct workqueue_struct *update_cntr_wq;
1132 struct work_struct update_cntr_work;
1133
1134 spinlock_t dc8051_memlock;
1135 int dc8051_timed_out;
1136
1137
1138
1139
1140 unsigned long *events;
1141
1142
1143
1144
1145
1146 struct hfi1_status *status;
1147
1148
1149 u64 revision;
1150
1151 u64 base_guid;
1152
1153
1154 u8 link_gen3_capable;
1155 u8 dc_shutdown;
1156
1157 u32 lbus_width;
1158
1159 u32 lbus_speed;
1160 int unit;
1161 int node;
1162
1163
1164 u32 pcibar0;
1165 u32 pcibar1;
1166 u32 pci_rom;
1167 u16 pci_command;
1168 u16 pcie_devctl;
1169 u16 pcie_lnkctl;
1170 u16 pcie_devctl2;
1171 u32 pci_msix0;
1172 u32 pci_tph2;
1173
1174
1175
1176
1177
1178 u8 serial[SERIAL_MAX];
1179
1180 u8 boardversion[BOARD_VERS_MAX];
1181 u8 lbus_info[32];
1182
1183 u8 majrev;
1184
1185 u8 minrev;
1186
1187 u8 hfi1_id;
1188
1189 u8 icode;
1190
1191 u8 vau;
1192
1193 u8 vcu;
1194
1195 u16 link_credits;
1196
1197 u16 vl15_init;
1198
1199
1200
1201
1202
1203
1204
1205 u16 vl15buf_cached;
1206
1207
1208 u8 n_krcv_queues;
1209 u8 qos_shift;
1210
1211 u16 irev;
1212 u32 dc8051_ver;
1213
1214 spinlock_t hfi1_diag_trans_lock;
1215 struct platform_config platform_config;
1216 struct platform_config_cache pcfg_cache;
1217
1218 struct diag_client *diag_client;
1219
1220
1221 u64 gi_mask[CCE_NUM_INT_CSRS];
1222
1223 struct rcv_array_data rcv_entries;
1224
1225
1226 u16 psxmitwait_check_rate;
1227
1228
1229
1230
1231 struct timer_list synth_stats_timer;
1232
1233
1234 struct hfi1_msix_info msix_info;
1235
1236
1237
1238
1239 char *cntrnames;
1240 size_t cntrnameslen;
1241 size_t ndevcntrs;
1242 u64 *cntrs;
1243 u64 *scntrs;
1244
1245
1246
1247
1248 u64 last_tx;
1249 u64 last_rx;
1250
1251
1252
1253
1254 size_t nportcntrs;
1255 char *portcntrnames;
1256 size_t portcntrnameslen;
1257
1258 struct err_info_rcvport err_info_rcvport;
1259 struct err_info_constraint err_info_rcv_constraint;
1260 struct err_info_constraint err_info_xmit_constraint;
1261
1262 atomic_t drop_packet;
1263 u8 do_drop;
1264 u8 err_info_uncorrectable;
1265 u8 err_info_fmconfig;
1266
1267
1268
1269
1270
1271 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1272 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1273 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1274 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1275 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1276 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1277 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1278
1279
1280 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1281
1282 u64 sw_send_dma_eng_err_status_cnt[
1283 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1284
1285 u64 sw_cce_err_status_aggregate;
1286
1287 u64 sw_rcv_bypass_packet_errors;
1288
1289
1290 u64 lcb_err_en;
1291 struct cpu_mask_set *comp_vect;
1292 int *comp_vect_mappings;
1293 u32 comp_vect_possible_cpus;
1294
1295
1296
1297
1298
1299 send_routine process_pio_send ____cacheline_aligned_in_smp;
1300 send_routine process_dma_send;
1301 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1302 u64 pbc, const void *from, size_t count);
1303 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1304 struct hfi1_vnic_vport_info *vinfo,
1305 struct sk_buff *skb, u64 pbc, u8 plen);
1306
1307
1308
1309 struct hfi1_pportdata *pport;
1310
1311 struct hfi1_ctxtdata **rcd;
1312 u64 __percpu *int_counter;
1313
1314 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1315
1316 u16 flags;
1317
1318 u8 num_pports;
1319
1320 u8 first_dyn_alloc_ctxt;
1321
1322
1323
1324 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1325 u64 sc2vl[4];
1326 u64 __percpu *rcv_limit;
1327
1328
1329
1330 u8 oui1;
1331 u8 oui2;
1332 u8 oui3;
1333
1334
1335 struct timer_list rcverr_timer;
1336
1337 wait_queue_head_t event_queue;
1338
1339
1340 __le64 *rcvhdrtail_dummy_kvaddr;
1341 dma_addr_t rcvhdrtail_dummy_dma;
1342
1343 u32 rcv_ovfl_cnt;
1344
1345 spinlock_t aspm_lock;
1346
1347 atomic_t aspm_disabled_cnt;
1348
1349 atomic_t user_refcount;
1350
1351 struct completion user_comp;
1352
1353 bool eprom_available;
1354 bool aspm_supported;
1355 bool aspm_enabled;
1356 struct rhashtable *sdma_rht;
1357
1358 struct kobject kobj;
1359
1360
1361 struct hfi1_vnic_data vnic;
1362
1363 spinlock_t irq_src_lock;
1364};
1365
1366static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1367{
1368 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1369}
1370
1371
1372#define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1373#define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1374#define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1375#define dc8051_ver_patch(a) ((a) & 0x0000ff)
1376
1377
1378#define PT_EXPECTED 0
1379#define PT_EAGER 1
1380#define PT_INVALID_FLUSH 2
1381#define PT_INVALID 3
1382
1383struct tid_rb_node;
1384struct mmu_rb_node;
1385struct mmu_rb_handler;
1386
1387
1388struct hfi1_filedata {
1389 struct hfi1_devdata *dd;
1390 struct hfi1_ctxtdata *uctxt;
1391 struct hfi1_user_sdma_comp_q *cq;
1392 struct hfi1_user_sdma_pkt_q *pq;
1393 u16 subctxt;
1394
1395 int rec_cpu_num;
1396 u32 tid_n_pinned;
1397 struct mmu_rb_handler *handler;
1398 struct tid_rb_node **entry_to_rb;
1399 spinlock_t tid_lock;
1400 u32 tid_limit;
1401 u32 tid_used;
1402 u32 *invalid_tids;
1403 u32 invalid_tid_idx;
1404
1405 spinlock_t invalid_lock;
1406 struct mm_struct *mm;
1407};
1408
1409extern struct list_head hfi1_dev_list;
1410extern spinlock_t hfi1_devs_lock;
1411struct hfi1_devdata *hfi1_lookup(int unit);
1412
1413static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1414{
1415 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1416 HFI1_MAX_SHARED_CTXTS;
1417}
1418
1419int hfi1_init(struct hfi1_devdata *dd, int reinit);
1420int hfi1_count_active_units(void);
1421
1422int hfi1_diag_add(struct hfi1_devdata *dd);
1423void hfi1_diag_remove(struct hfi1_devdata *dd);
1424void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1425
1426void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1427
1428int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1429int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1430int hfi1_create_kctxts(struct hfi1_devdata *dd);
1431int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1432 struct hfi1_ctxtdata **rcd);
1433void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1434void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1435 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1436void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1437int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1438void hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1439struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1440 u16 ctxt);
1441struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1442int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1443int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1444int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1445void set_all_slowpath(struct hfi1_devdata *dd);
1446
1447extern const struct pci_device_id hfi1_pci_tbl[];
1448void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1449 struct hfi1_pkt_state *ps,
1450 struct rvt_swqe *wqe);
1451
1452void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1453 struct hfi1_pkt_state *ps,
1454 struct rvt_swqe *wqe);
1455
1456
1457#define RCV_PKT_OK 0x0
1458#define RCV_PKT_LIMIT 0x1
1459#define RCV_PKT_DONE 0x2
1460
1461
1462static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1463{
1464 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
1465}
1466
1467int hfi1_reset_device(int);
1468
1469void receive_interrupt_work(struct work_struct *work);
1470
1471
1472static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1473{
1474 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1475}
1476
1477#define HFI1_JKEY_WIDTH 16
1478#define HFI1_JKEY_MASK (BIT(16) - 1)
1479#define HFI1_ADMIN_JKEY_RANGE 32
1480
1481
1482
1483
1484
1485
1486
1487static inline u16 generate_jkey(kuid_t uid)
1488{
1489 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1490
1491 if (capable(CAP_SYS_ADMIN))
1492 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1493 else if (jkey < 64)
1494 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1495
1496 return jkey;
1497}
1498
1499
1500
1501
1502
1503
1504static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1505{
1506 u16 link_speed = ppd->link_speed_active;
1507 u16 link_width = ppd->link_width_active;
1508 u32 egress_rate;
1509
1510 if (link_speed == OPA_LINK_SPEED_25G)
1511 egress_rate = 25000;
1512 else
1513 egress_rate = 12500;
1514
1515 switch (link_width) {
1516 case OPA_LINK_WIDTH_4X:
1517 egress_rate *= 4;
1518 break;
1519 case OPA_LINK_WIDTH_3X:
1520 egress_rate *= 3;
1521 break;
1522 case OPA_LINK_WIDTH_2X:
1523 egress_rate *= 2;
1524 break;
1525 default:
1526
1527 break;
1528 }
1529
1530 return egress_rate;
1531}
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541static inline u32 egress_cycles(u32 len, u32 rate)
1542{
1543 u32 cycles;
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553 cycles = len * 8;
1554 cycles *= 805;
1555 cycles /= rate;
1556
1557 return cycles;
1558}
1559
1560void set_link_ipg(struct hfi1_pportdata *ppd);
1561void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1562 u32 rqpn, u8 svc_type);
1563void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1564 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1565 const struct ib_grh *old_grh);
1566void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1567 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1568 u8 sc5, const struct ib_grh *old_grh);
1569typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1570 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1571 u8 sc5, const struct ib_grh *old_grh);
1572
1573#define PKEY_CHECK_INVALID -1
1574int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1575 u8 sc5, int8_t s_pkey_index);
1576
1577#define PACKET_EGRESS_TIMEOUT 350
1578static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1579{
1580
1581 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1582
1583 udelay(usec ? usec : 1);
1584}
1585
1586
1587
1588
1589
1590
1591static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1592{
1593 unsigned seq;
1594 u8 rval;
1595
1596 if (sc5 >= OPA_MAX_SCS)
1597 return (u8)(0xff);
1598
1599 do {
1600 seq = read_seqbegin(&dd->sc2vl_lock);
1601 rval = *(((u8 *)dd->sc2vl) + sc5);
1602 } while (read_seqretry(&dd->sc2vl_lock, seq));
1603
1604 return rval;
1605}
1606
1607#define PKEY_MEMBER_MASK 0x8000
1608#define PKEY_LOW_15_MASK 0x7fff
1609
1610
1611
1612
1613
1614
1615
1616static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1617{
1618 u16 mkey = pkey & PKEY_LOW_15_MASK;
1619 u16 ment = ent & PKEY_LOW_15_MASK;
1620
1621 if (mkey == ment) {
1622
1623
1624
1625
1626
1627 if (!(pkey & PKEY_MEMBER_MASK))
1628 return !!(ent & PKEY_MEMBER_MASK);
1629 return 1;
1630 }
1631 return 0;
1632}
1633
1634
1635
1636
1637
1638
1639static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1640{
1641 int i;
1642
1643 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1644 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1645 return 0;
1646 }
1647 return 1;
1648}
1649
1650
1651
1652
1653
1654
1655static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1656 u32 slid)
1657{
1658 struct hfi1_devdata *dd = ppd->dd;
1659
1660 incr_cntr64(&ppd->port_rcv_constraint_errors);
1661 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1662 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1663 dd->err_info_rcv_constraint.slid = slid;
1664 dd->err_info_rcv_constraint.pkey = pkey;
1665 }
1666}
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1677 u8 sc5, u8 idx, u32 slid, bool force)
1678{
1679 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1680 return 0;
1681
1682
1683 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1684 goto bad;
1685
1686
1687 if ((pkey & PKEY_LOW_15_MASK) == 0)
1688 goto bad;
1689
1690
1691 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1692 return 0;
1693
1694
1695 if (!ingress_pkey_table_search(ppd, pkey))
1696 return 0;
1697
1698bad:
1699 ingress_pkey_table_fail(ppd, pkey, slid);
1700 return 1;
1701}
1702
1703
1704
1705
1706
1707
1708
1709static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1710 u8 sc5, u16 slid)
1711{
1712 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1713 return 0;
1714
1715
1716 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1717 goto bad;
1718
1719 return 0;
1720bad:
1721 ingress_pkey_table_fail(ppd, pkey, slid);
1722 return 1;
1723}
1724
1725
1726
1727
1728#define OPA_MTU_0 0
1729#define OPA_MTU_256 1
1730#define OPA_MTU_512 2
1731#define OPA_MTU_1024 3
1732#define OPA_MTU_2048 4
1733#define OPA_MTU_4096 5
1734
1735u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1736int mtu_to_enum(u32 mtu, int default_if_bad);
1737u16 enum_to_mtu(int mtu);
1738static inline int valid_ib_mtu(unsigned int mtu)
1739{
1740 return mtu == 256 || mtu == 512 ||
1741 mtu == 1024 || mtu == 2048 ||
1742 mtu == 4096;
1743}
1744
1745static inline int valid_opa_max_mtu(unsigned int mtu)
1746{
1747 return mtu >= 2048 &&
1748 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1749}
1750
1751int set_mtu(struct hfi1_pportdata *ppd);
1752
1753int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1754void hfi1_disable_after_error(struct hfi1_devdata *dd);
1755int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1756int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1757
1758int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1759int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1760
1761void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1762void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1763void reset_link_credits(struct hfi1_devdata *dd);
1764void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1765
1766int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1767
1768static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1769{
1770 return ppd->dd;
1771}
1772
1773static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1774{
1775 return container_of(dev, struct hfi1_devdata, verbs_dev);
1776}
1777
1778static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1779{
1780 return dd_from_dev(to_idev(ibdev));
1781}
1782
1783static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1784{
1785 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1786}
1787
1788static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1789{
1790 return container_of(rdi, struct hfi1_ibdev, rdi);
1791}
1792
1793static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1794{
1795 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1796 unsigned pidx = port - 1;
1797
1798 WARN_ON(pidx >= dd->num_pports);
1799 return &dd->pport[pidx].ibport_data;
1800}
1801
1802static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1803{
1804 return &rcd->ppd->ibport_data;
1805}
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818static inline bool hfi1_may_ecn(struct hfi1_packet *pkt)
1819{
1820 bool fecn, becn;
1821
1822 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1823 fecn = hfi1_16B_get_fecn(pkt->hdr);
1824 becn = hfi1_16B_get_becn(pkt->hdr);
1825 } else {
1826 fecn = ib_bth_get_fecn(pkt->ohdr);
1827 becn = ib_bth_get_becn(pkt->ohdr);
1828 }
1829 return fecn || becn;
1830}
1831
1832bool hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1833 bool prescan);
1834static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt)
1835{
1836 bool do_work;
1837
1838 do_work = hfi1_may_ecn(pkt);
1839 if (unlikely(do_work))
1840 return hfi1_process_ecn_slowpath(qp, pkt, false);
1841 return false;
1842}
1843
1844
1845
1846
1847static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1848{
1849 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1850 u16 ret;
1851
1852 if (index >= ARRAY_SIZE(ppd->pkeys))
1853 ret = 0;
1854 else
1855 ret = ppd->pkeys[index];
1856
1857 return ret;
1858}
1859
1860
1861
1862
1863static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1864{
1865 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1866
1867 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1868 return cpu_to_be64(ppd->guids[index]);
1869}
1870
1871
1872
1873
1874static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1875{
1876 return rcu_dereference(ppd->cc_state);
1877}
1878
1879
1880
1881
1882static inline
1883struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1884{
1885 return rcu_dereference_protected(ppd->cc_state,
1886 lockdep_is_held(&ppd->cc_state_lock));
1887}
1888
1889
1890
1891
1892#define HFI1_INITTED 0x1
1893#define HFI1_PRESENT 0x2
1894#define HFI1_FROZEN 0x4
1895#define HFI1_HAS_SDMA_TIMEOUT 0x8
1896#define HFI1_HAS_SEND_DMA 0x10
1897#define HFI1_FORCED_FREEZE 0x80
1898#define HFI1_SHUTDOWN 0x100
1899
1900
1901#define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1902
1903
1904
1905#define HFI1_CTXT_BASE_UNINIT 1
1906
1907#define HFI1_CTXT_BASE_FAILED 2
1908
1909#define HFI1_CTXT_WAITING_RCV 3
1910
1911#define HFI1_CTXT_WAITING_URG 4
1912
1913
1914int hfi1_init_dd(struct hfi1_devdata *dd);
1915void hfi1_free_devdata(struct hfi1_devdata *dd);
1916
1917
1918void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1919 unsigned int timeoff);
1920void shutdown_led_override(struct hfi1_pportdata *ppd);
1921
1922#define HFI1_CREDIT_RETURN_RATE (100)
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943#define DEFAULT_RCVHDRSIZE 9
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960#define DEFAULT_RCVHDR_ENTSIZE 32
1961
1962bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1963 u32 nlocked, u32 npages);
1964int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1965 size_t npages, bool writable, struct page **pages);
1966void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1967 size_t npages, bool dirty);
1968
1969static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1970{
1971 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1972}
1973
1974static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1975{
1976
1977
1978
1979
1980 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1981}
1982
1983
1984
1985
1986
1987extern const char ib_hfi1_version[];
1988extern const struct attribute_group ib_hfi1_attr_group;
1989
1990int hfi1_device_create(struct hfi1_devdata *dd);
1991void hfi1_device_remove(struct hfi1_devdata *dd);
1992
1993int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1994 struct kobject *kobj);
1995int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1996void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1997
1998int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1999
2000int hfi1_pcie_init(struct hfi1_devdata *dd);
2001void hfi1_pcie_cleanup(struct pci_dev *pdev);
2002int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
2003void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
2004int pcie_speeds(struct hfi1_devdata *dd);
2005int restore_pci_variables(struct hfi1_devdata *dd);
2006int save_pci_variables(struct hfi1_devdata *dd);
2007int do_pcie_gen3_transition(struct hfi1_devdata *dd);
2008void tune_pcie_caps(struct hfi1_devdata *dd);
2009int parse_platform_config(struct hfi1_devdata *dd);
2010int get_platform_config_field(struct hfi1_devdata *dd,
2011 enum platform_config_table_type_encoding
2012 table_type, int table_index, int field_index,
2013 u32 *data, u32 len);
2014
2015struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
2016
2017
2018
2019
2020
2021static inline void flush_wc(void)
2022{
2023 asm volatile("sfence" : : : "memory");
2024}
2025
2026void handle_eflags(struct hfi1_packet *packet);
2027void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2028
2029
2030extern unsigned int hfi1_max_mtu;
2031extern unsigned int hfi1_cu;
2032extern unsigned int user_credit_return_threshold;
2033extern int num_user_contexts;
2034extern unsigned long n_krcvqs;
2035extern uint krcvqs[];
2036extern int krcvqsset;
2037extern uint kdeth_qp;
2038extern uint loopback;
2039extern uint quick_linkup;
2040extern uint rcv_intr_timeout;
2041extern uint rcv_intr_count;
2042extern uint rcv_intr_dynamic;
2043extern ushort link_crc_mask;
2044
2045extern struct mutex hfi1_mutex;
2046
2047
2048#define STATUS_TIMEOUT 60
2049
2050#define DRIVER_NAME "hfi1"
2051#define HFI1_USER_MINOR_BASE 0
2052#define HFI1_TRACE_MINOR 127
2053#define HFI1_NMINORS 255
2054
2055#define PCI_VENDOR_ID_INTEL 0x8086
2056#define PCI_DEVICE_ID_INTEL0 0x24f0
2057#define PCI_DEVICE_ID_INTEL1 0x24f1
2058
2059#define HFI1_PKT_USER_SC_INTEGRITY \
2060 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2061 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2062 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2063 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2064
2065#define HFI1_PKT_KERNEL_SC_INTEGRITY \
2066 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2067
2068static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2069 u16 ctxt_type)
2070{
2071 u64 base_sc_integrity;
2072
2073
2074 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2075 return 0;
2076
2077 base_sc_integrity =
2078 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2079 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2080 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2081 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2082 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2083#ifndef CONFIG_FAULT_INJECTION
2084 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2085#endif
2086 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2087 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2088 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2089 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2090 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2091 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2092 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2093 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2094 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2095 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2096
2097 if (ctxt_type == SC_USER)
2098 base_sc_integrity |=
2099#ifndef CONFIG_FAULT_INJECTION
2100 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2101#endif
2102 HFI1_PKT_USER_SC_INTEGRITY;
2103 else
2104 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2105
2106
2107 if (!is_ax(dd))
2108 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2109
2110 return base_sc_integrity;
2111}
2112
2113static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2114{
2115 u64 base_sdma_integrity;
2116
2117
2118 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2119 return 0;
2120
2121 base_sdma_integrity =
2122 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2123 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2124 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2125 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2126 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2127 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2128 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2129 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2130 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2131 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2132 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2133 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2134 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2135 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2136
2137 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2138 base_sdma_integrity |=
2139 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2140
2141
2142 if (!is_ax(dd))
2143 base_sdma_integrity |=
2144 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2145
2146 return base_sdma_integrity;
2147}
2148
2149#define dd_dev_emerg(dd, fmt, ...) \
2150 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2151 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2152
2153#define dd_dev_err(dd, fmt, ...) \
2154 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2155 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2156
2157#define dd_dev_err_ratelimited(dd, fmt, ...) \
2158 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2159 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2160 ##__VA_ARGS__)
2161
2162#define dd_dev_warn(dd, fmt, ...) \
2163 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2164 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2165
2166#define dd_dev_warn_ratelimited(dd, fmt, ...) \
2167 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2168 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2169 ##__VA_ARGS__)
2170
2171#define dd_dev_info(dd, fmt, ...) \
2172 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2173 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2174
2175#define dd_dev_info_ratelimited(dd, fmt, ...) \
2176 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2177 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2178 ##__VA_ARGS__)
2179
2180#define dd_dev_dbg(dd, fmt, ...) \
2181 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2182 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2183
2184#define hfi1_dev_porterr(dd, port, fmt, ...) \
2185 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2186 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2187
2188
2189
2190
2191struct hfi1_hwerror_msgs {
2192 u64 mask;
2193 const char *msg;
2194 size_t sz;
2195};
2196
2197
2198void hfi1_format_hwerrors(u64 hwerrs,
2199 const struct hfi1_hwerror_msgs *hwerrmsgs,
2200 size_t nhwerrmsgs, char *msg, size_t lmsg);
2201
2202#define USER_OPCODE_CHECK_VAL 0xC0
2203#define USER_OPCODE_CHECK_MASK 0xC0
2204#define OPCODE_CHECK_VAL_DISABLED 0x0
2205#define OPCODE_CHECK_MASK_DISABLED 0x0
2206
2207static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2208{
2209 struct hfi1_pportdata *ppd;
2210 int i;
2211
2212 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2213 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2214 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2215
2216 ppd = (struct hfi1_pportdata *)(dd + 1);
2217 for (i = 0; i < dd->num_pports; i++, ppd++) {
2218 ppd->ibport_data.rvp.z_rc_acks =
2219 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2220 ppd->ibport_data.rvp.z_rc_qacks =
2221 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2222 }
2223}
2224
2225
2226static inline void setextled(struct hfi1_devdata *dd, u32 on)
2227{
2228 if (on)
2229 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2230 else
2231 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2232}
2233
2234
2235static inline u32 i2c_target(u32 target)
2236{
2237 return target ? CR_I2C2 : CR_I2C1;
2238}
2239
2240
2241static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2242{
2243 return i2c_target(dd->hfi1_id);
2244}
2245
2246
2247static inline bool is_integrated(struct hfi1_devdata *dd)
2248{
2249 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2250}
2251
2252int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2253
2254#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2255#define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2256
2257static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2258 struct rdma_ah_attr *attr)
2259{
2260 struct hfi1_pportdata *ppd;
2261 struct hfi1_ibport *ibp;
2262 u32 dlid = rdma_ah_get_dlid(attr);
2263
2264
2265
2266
2267
2268 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2269 ppd = ppd_from_ibp(ibp);
2270 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2271 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2272 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2273 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2274 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2275 (rdma_ah_get_make_grd(attr))) {
2276 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2277 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2278 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2279 }
2280}
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290static inline bool hfi1_check_mcast(u32 lid)
2291{
2292 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2293 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2294}
2295
2296#define opa_get_lid(lid, format) \
2297 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2298
2299
2300static inline u32 __opa_get_lid(u32 lid, u8 format)
2301{
2302 bool is_mcast = hfi1_check_mcast(lid);
2303
2304 switch (format) {
2305 case OPA_PORT_PACKET_FORMAT_8B:
2306 case OPA_PORT_PACKET_FORMAT_10B:
2307 if (is_mcast)
2308 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2309 0xF0000);
2310 return lid & 0xFFFFF;
2311 case OPA_PORT_PACKET_FORMAT_16B:
2312 if (is_mcast)
2313 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2314 0xF00000);
2315 return lid & 0xFFFFFF;
2316 case OPA_PORT_PACKET_FORMAT_9B:
2317 if (is_mcast)
2318 return (lid -
2319 opa_get_mcast_base(OPA_MCAST_NR) +
2320 be16_to_cpu(IB_MULTICAST_LID_BASE));
2321 else
2322 return lid & 0xFFFF;
2323 default:
2324 return lid;
2325 }
2326}
2327
2328
2329static inline bool hfi1_is_16B_mcast(u32 lid)
2330{
2331 return ((lid >=
2332 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2333 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2334}
2335
2336static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2337{
2338 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2339 u32 dlid = rdma_ah_get_dlid(attr);
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349 if (ib_is_opa_gid(&grh->dgid))
2350 dlid = opa_get_lid_from_gid(&grh->dgid);
2351 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2352 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2353 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2354 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2355 opa_get_mcast_base(OPA_MCAST_NR);
2356 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2357 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2358
2359 rdma_ah_set_dlid(attr, dlid);
2360}
2361
2362static inline u8 hfi1_get_packet_type(u32 lid)
2363{
2364
2365 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2366 return HFI1_PKT_TYPE_9B;
2367
2368
2369 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2370 return HFI1_PKT_TYPE_16B;
2371
2372 return HFI1_PKT_TYPE_9B;
2373}
2374
2375static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2376{
2377
2378
2379
2380
2381
2382
2383
2384 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2385 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2386 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2387
2388
2389
2390
2391
2392 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2393 return HFI1_PKT_TYPE_16B;
2394
2395 return hfi1_get_packet_type(lid);
2396}
2397
2398static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2399 struct ib_grh *grh, u32 slid,
2400 u32 dlid)
2401{
2402 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2403 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2404
2405 if (!ibp)
2406 return;
2407
2408 grh->hop_limit = 1;
2409 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2410 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2411 grh->sgid.global.interface_id =
2412 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2413 else
2414 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2415
2416
2417
2418
2419
2420
2421
2422
2423 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2424 grh->dgid.global.interface_id =
2425 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2426}
2427
2428static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2429{
2430 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2431 SIZE_OF_LT) & 0x7;
2432}
2433
2434static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2435 u16 lrh0, u16 len,
2436 u16 dlid, u16 slid)
2437{
2438 hdr->lrh[0] = cpu_to_be16(lrh0);
2439 hdr->lrh[1] = cpu_to_be16(dlid);
2440 hdr->lrh[2] = cpu_to_be16(len);
2441 hdr->lrh[3] = cpu_to_be16(slid);
2442}
2443
2444static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2445 u32 slid, u32 dlid,
2446 u16 len, u16 pkey,
2447 bool becn, bool fecn, u8 l4,
2448 u8 sc)
2449{
2450 u32 lrh0 = 0;
2451 u32 lrh1 = 0x40000000;
2452 u32 lrh2 = 0;
2453 u32 lrh3 = 0;
2454
2455 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2456 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2457 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2458 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2459 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2460 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2461 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2462 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2463 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2464 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2465 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2466 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2467
2468 hdr->lrh[0] = lrh0;
2469 hdr->lrh[1] = lrh1;
2470 hdr->lrh[2] = lrh2;
2471 hdr->lrh[3] = lrh3;
2472}
2473#endif
2474