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46#ifndef __PVRDMA_DEV_API_H__
47#define __PVRDMA_DEV_API_H__
48
49#include <linux/types.h>
50
51#include "pvrdma_verbs.h"
52
53
54
55
56
57
58#define PVRDMA_ROCEV1_VERSION 17
59#define PVRDMA_ROCEV2_VERSION 18
60#define PVRDMA_VERSION PVRDMA_ROCEV2_VERSION
61
62#define PVRDMA_BOARD_ID 1
63#define PVRDMA_REV_ID 1
64
65
66
67
68
69
70
71
72#define PVRDMA_PDIR_SHIFT 18
73#define PVRDMA_PTABLE_SHIFT 9
74#define PVRDMA_PAGE_DIR_DIR(x) (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
75#define PVRDMA_PAGE_DIR_TABLE(x) (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
76#define PVRDMA_PAGE_DIR_PAGE(x) ((x) & 0x1ff)
77#define PVRDMA_PAGE_DIR_MAX_PAGES (1 * 512 * 512)
78#define PVRDMA_MAX_FAST_REG_PAGES 128
79
80
81
82
83
84#define PVRDMA_MAX_INTERRUPTS 3
85
86
87#define PVRDMA_REG_VERSION 0x00
88#define PVRDMA_REG_DSRLOW 0x04
89#define PVRDMA_REG_DSRHIGH 0x08
90#define PVRDMA_REG_CTL 0x0c
91#define PVRDMA_REG_REQUEST 0x10
92#define PVRDMA_REG_ERR 0x14
93#define PVRDMA_REG_ICR 0x18
94#define PVRDMA_REG_IMR 0x1c
95#define PVRDMA_REG_MACL 0x20
96#define PVRDMA_REG_MACH 0x24
97
98
99#define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0)
100#define PVRDMA_CQ_FLAG_ARMED BIT(1)
101#define PVRDMA_MR_FLAG_DMA BIT(0)
102#define PVRDMA_MR_FLAG_FRMR BIT(1)
103
104
105
106
107
108
109#define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0)
110#define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1)
111#define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2)
112#define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3)
113
114
115
116
117
118
119
120#define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0)
121#define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1)
122#define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2)
123
124
125
126
127
128
129
130
131#define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0)
132#define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1)
133
134
135
136
137
138
139#define PVRDMA_IS_VERSION17(_dev) \
140 (_dev->dsr_version == PVRDMA_ROCEV1_VERSION && \
141 _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
142
143#define PVRDMA_IS_VERSION18(_dev) \
144 (_dev->dsr_version >= PVRDMA_ROCEV2_VERSION && \
145 (_dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1 || \
146 _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)) \
147
148#define PVRDMA_SUPPORTED(_dev) \
149 ((_dev->dsr->caps.mode == PVRDMA_DEVICE_MODE_ROCE) && \
150 (PVRDMA_IS_VERSION17(_dev) || PVRDMA_IS_VERSION18(_dev)))
151
152
153
154
155
156#define PVRDMA_GET_CAP(_dev, _old_val, _val) \
157 ((PVRDMA_IS_VERSION18(_dev)) ? _val : _old_val)
158
159enum pvrdma_pci_resource {
160 PVRDMA_PCI_RESOURCE_MSIX,
161 PVRDMA_PCI_RESOURCE_REG,
162 PVRDMA_PCI_RESOURCE_UAR,
163 PVRDMA_PCI_RESOURCE_LAST,
164};
165
166enum pvrdma_device_ctl {
167 PVRDMA_DEVICE_CTL_ACTIVATE,
168 PVRDMA_DEVICE_CTL_UNQUIESCE,
169 PVRDMA_DEVICE_CTL_RESET,
170};
171
172enum pvrdma_intr_vector {
173 PVRDMA_INTR_VECTOR_RESPONSE,
174 PVRDMA_INTR_VECTOR_ASYNC,
175 PVRDMA_INTR_VECTOR_CQ,
176
177};
178
179enum pvrdma_intr_cause {
180 PVRDMA_INTR_CAUSE_RESPONSE = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
181 PVRDMA_INTR_CAUSE_ASYNC = (1 << PVRDMA_INTR_VECTOR_ASYNC),
182 PVRDMA_INTR_CAUSE_CQ = (1 << PVRDMA_INTR_VECTOR_CQ),
183};
184
185enum pvrdma_gos_bits {
186 PVRDMA_GOS_BITS_UNK,
187 PVRDMA_GOS_BITS_32,
188 PVRDMA_GOS_BITS_64,
189};
190
191enum pvrdma_gos_type {
192 PVRDMA_GOS_TYPE_UNK,
193 PVRDMA_GOS_TYPE_LINUX,
194};
195
196enum pvrdma_device_mode {
197 PVRDMA_DEVICE_MODE_ROCE,
198 PVRDMA_DEVICE_MODE_IWARP,
199 PVRDMA_DEVICE_MODE_IB,
200};
201
202struct pvrdma_gos_info {
203 u32 gos_bits:2;
204 u32 gos_type:4;
205 u32 gos_ver:16;
206 u32 gos_misc:10;
207 u32 pad;
208};
209
210struct pvrdma_device_caps {
211 u64 fw_ver;
212 __be64 node_guid;
213 __be64 sys_image_guid;
214 u64 max_mr_size;
215 u64 page_size_cap;
216 u64 atomic_arg_sizes;
217 u32 ex_comp_mask;
218 u32 device_cap_flags2;
219 u32 max_fa_bit_boundary;
220 u32 log_max_atomic_inline_arg;
221 u32 vendor_id;
222 u32 vendor_part_id;
223 u32 hw_ver;
224 u32 max_qp;
225 u32 max_qp_wr;
226 u32 device_cap_flags;
227 u32 max_sge;
228 u32 max_sge_rd;
229 u32 max_cq;
230 u32 max_cqe;
231 u32 max_mr;
232 u32 max_pd;
233 u32 max_qp_rd_atom;
234 u32 max_ee_rd_atom;
235 u32 max_res_rd_atom;
236 u32 max_qp_init_rd_atom;
237 u32 max_ee_init_rd_atom;
238 u32 max_ee;
239 u32 max_rdd;
240 u32 max_mw;
241 u32 max_raw_ipv6_qp;
242 u32 max_raw_ethy_qp;
243 u32 max_mcast_grp;
244 u32 max_mcast_qp_attach;
245 u32 max_total_mcast_qp_attach;
246 u32 max_ah;
247 u32 max_fmr;
248 u32 max_map_per_fmr;
249 u32 max_srq;
250 u32 max_srq_wr;
251 u32 max_srq_sge;
252 u32 max_uar;
253 u32 gid_tbl_len;
254 u16 max_pkeys;
255 u8 local_ca_ack_delay;
256 u8 phys_port_cnt;
257 u8 mode;
258 u8 atomic_ops;
259 u8 bmme_flags;
260 u8 gid_types;
261 u32 max_fast_reg_page_list_len;
262};
263
264struct pvrdma_ring_page_info {
265 u32 num_pages;
266 u32 reserved;
267 u64 pdir_dma;
268};
269
270#pragma pack(push, 1)
271
272struct pvrdma_device_shared_region {
273 u32 driver_version;
274 u32 pad;
275 struct pvrdma_gos_info gos_info;
276 u64 cmd_slot_dma;
277 u64 resp_slot_dma;
278 struct pvrdma_ring_page_info async_ring_pages;
279
280 struct pvrdma_ring_page_info cq_ring_pages;
281
282 u32 uar_pfn;
283 u32 pad2;
284 struct pvrdma_device_caps caps;
285};
286
287#pragma pack(pop)
288
289
290enum pvrdma_eqe_type {
291 PVRDMA_EVENT_CQ_ERR,
292 PVRDMA_EVENT_QP_FATAL,
293 PVRDMA_EVENT_QP_REQ_ERR,
294 PVRDMA_EVENT_QP_ACCESS_ERR,
295 PVRDMA_EVENT_COMM_EST,
296 PVRDMA_EVENT_SQ_DRAINED,
297 PVRDMA_EVENT_PATH_MIG,
298 PVRDMA_EVENT_PATH_MIG_ERR,
299 PVRDMA_EVENT_DEVICE_FATAL,
300 PVRDMA_EVENT_PORT_ACTIVE,
301 PVRDMA_EVENT_PORT_ERR,
302 PVRDMA_EVENT_LID_CHANGE,
303 PVRDMA_EVENT_PKEY_CHANGE,
304 PVRDMA_EVENT_SM_CHANGE,
305 PVRDMA_EVENT_SRQ_ERR,
306 PVRDMA_EVENT_SRQ_LIMIT_REACHED,
307 PVRDMA_EVENT_QP_LAST_WQE_REACHED,
308 PVRDMA_EVENT_CLIENT_REREGISTER,
309 PVRDMA_EVENT_GID_CHANGE,
310};
311
312
313struct pvrdma_eqe {
314 u32 type;
315 u32 info;
316};
317
318
319struct pvrdma_cqne {
320 u32 info;
321};
322
323enum {
324 PVRDMA_CMD_FIRST,
325 PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
326 PVRDMA_CMD_QUERY_PKEY,
327 PVRDMA_CMD_CREATE_PD,
328 PVRDMA_CMD_DESTROY_PD,
329 PVRDMA_CMD_CREATE_MR,
330 PVRDMA_CMD_DESTROY_MR,
331 PVRDMA_CMD_CREATE_CQ,
332 PVRDMA_CMD_RESIZE_CQ,
333 PVRDMA_CMD_DESTROY_CQ,
334 PVRDMA_CMD_CREATE_QP,
335 PVRDMA_CMD_MODIFY_QP,
336 PVRDMA_CMD_QUERY_QP,
337 PVRDMA_CMD_DESTROY_QP,
338 PVRDMA_CMD_CREATE_UC,
339 PVRDMA_CMD_DESTROY_UC,
340 PVRDMA_CMD_CREATE_BIND,
341 PVRDMA_CMD_DESTROY_BIND,
342 PVRDMA_CMD_CREATE_SRQ,
343 PVRDMA_CMD_MODIFY_SRQ,
344 PVRDMA_CMD_QUERY_SRQ,
345 PVRDMA_CMD_DESTROY_SRQ,
346 PVRDMA_CMD_MAX,
347};
348
349enum {
350 PVRDMA_CMD_FIRST_RESP = (1 << 31),
351 PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
352 PVRDMA_CMD_QUERY_PKEY_RESP,
353 PVRDMA_CMD_CREATE_PD_RESP,
354 PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
355 PVRDMA_CMD_CREATE_MR_RESP,
356 PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
357 PVRDMA_CMD_CREATE_CQ_RESP,
358 PVRDMA_CMD_RESIZE_CQ_RESP,
359 PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
360 PVRDMA_CMD_CREATE_QP_RESP,
361 PVRDMA_CMD_MODIFY_QP_RESP,
362 PVRDMA_CMD_QUERY_QP_RESP,
363 PVRDMA_CMD_DESTROY_QP_RESP,
364 PVRDMA_CMD_CREATE_UC_RESP,
365 PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
366 PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
367 PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
368 PVRDMA_CMD_CREATE_SRQ_RESP,
369 PVRDMA_CMD_MODIFY_SRQ_RESP,
370 PVRDMA_CMD_QUERY_SRQ_RESP,
371 PVRDMA_CMD_DESTROY_SRQ_RESP,
372 PVRDMA_CMD_MAX_RESP,
373};
374
375struct pvrdma_cmd_hdr {
376 u64 response;
377 u32 cmd;
378 u32 reserved;
379};
380
381struct pvrdma_cmd_resp_hdr {
382 u64 response;
383 u32 ack;
384 u8 err;
385 u8 reserved[3];
386};
387
388struct pvrdma_cmd_query_port {
389 struct pvrdma_cmd_hdr hdr;
390 u8 port_num;
391 u8 reserved[7];
392};
393
394struct pvrdma_cmd_query_port_resp {
395 struct pvrdma_cmd_resp_hdr hdr;
396 struct pvrdma_port_attr attrs;
397};
398
399struct pvrdma_cmd_query_pkey {
400 struct pvrdma_cmd_hdr hdr;
401 u8 port_num;
402 u8 index;
403 u8 reserved[6];
404};
405
406struct pvrdma_cmd_query_pkey_resp {
407 struct pvrdma_cmd_resp_hdr hdr;
408 u16 pkey;
409 u8 reserved[6];
410};
411
412struct pvrdma_cmd_create_uc {
413 struct pvrdma_cmd_hdr hdr;
414 u32 pfn;
415 u8 reserved[4];
416};
417
418struct pvrdma_cmd_create_uc_resp {
419 struct pvrdma_cmd_resp_hdr hdr;
420 u32 ctx_handle;
421 u8 reserved[4];
422};
423
424struct pvrdma_cmd_destroy_uc {
425 struct pvrdma_cmd_hdr hdr;
426 u32 ctx_handle;
427 u8 reserved[4];
428};
429
430struct pvrdma_cmd_create_pd {
431 struct pvrdma_cmd_hdr hdr;
432 u32 ctx_handle;
433 u8 reserved[4];
434};
435
436struct pvrdma_cmd_create_pd_resp {
437 struct pvrdma_cmd_resp_hdr hdr;
438 u32 pd_handle;
439 u8 reserved[4];
440};
441
442struct pvrdma_cmd_destroy_pd {
443 struct pvrdma_cmd_hdr hdr;
444 u32 pd_handle;
445 u8 reserved[4];
446};
447
448struct pvrdma_cmd_create_mr {
449 struct pvrdma_cmd_hdr hdr;
450 u64 start;
451 u64 length;
452 u64 pdir_dma;
453 u32 pd_handle;
454 u32 access_flags;
455 u32 flags;
456 u32 nchunks;
457};
458
459struct pvrdma_cmd_create_mr_resp {
460 struct pvrdma_cmd_resp_hdr hdr;
461 u32 mr_handle;
462 u32 lkey;
463 u32 rkey;
464 u8 reserved[4];
465};
466
467struct pvrdma_cmd_destroy_mr {
468 struct pvrdma_cmd_hdr hdr;
469 u32 mr_handle;
470 u8 reserved[4];
471};
472
473struct pvrdma_cmd_create_cq {
474 struct pvrdma_cmd_hdr hdr;
475 u64 pdir_dma;
476 u32 ctx_handle;
477 u32 cqe;
478 u32 nchunks;
479 u8 reserved[4];
480};
481
482struct pvrdma_cmd_create_cq_resp {
483 struct pvrdma_cmd_resp_hdr hdr;
484 u32 cq_handle;
485 u32 cqe;
486};
487
488struct pvrdma_cmd_resize_cq {
489 struct pvrdma_cmd_hdr hdr;
490 u32 cq_handle;
491 u32 cqe;
492};
493
494struct pvrdma_cmd_resize_cq_resp {
495 struct pvrdma_cmd_resp_hdr hdr;
496 u32 cqe;
497 u8 reserved[4];
498};
499
500struct pvrdma_cmd_destroy_cq {
501 struct pvrdma_cmd_hdr hdr;
502 u32 cq_handle;
503 u8 reserved[4];
504};
505
506struct pvrdma_cmd_create_srq {
507 struct pvrdma_cmd_hdr hdr;
508 u64 pdir_dma;
509 u32 pd_handle;
510 u32 nchunks;
511 struct pvrdma_srq_attr attrs;
512 u8 srq_type;
513 u8 reserved[7];
514};
515
516struct pvrdma_cmd_create_srq_resp {
517 struct pvrdma_cmd_resp_hdr hdr;
518 u32 srqn;
519 u8 reserved[4];
520};
521
522struct pvrdma_cmd_modify_srq {
523 struct pvrdma_cmd_hdr hdr;
524 u32 srq_handle;
525 u32 attr_mask;
526 struct pvrdma_srq_attr attrs;
527};
528
529struct pvrdma_cmd_query_srq {
530 struct pvrdma_cmd_hdr hdr;
531 u32 srq_handle;
532 u8 reserved[4];
533};
534
535struct pvrdma_cmd_query_srq_resp {
536 struct pvrdma_cmd_resp_hdr hdr;
537 struct pvrdma_srq_attr attrs;
538};
539
540struct pvrdma_cmd_destroy_srq {
541 struct pvrdma_cmd_hdr hdr;
542 u32 srq_handle;
543 u8 reserved[4];
544};
545
546struct pvrdma_cmd_create_qp {
547 struct pvrdma_cmd_hdr hdr;
548 u64 pdir_dma;
549 u32 pd_handle;
550 u32 send_cq_handle;
551 u32 recv_cq_handle;
552 u32 srq_handle;
553 u32 max_send_wr;
554 u32 max_recv_wr;
555 u32 max_send_sge;
556 u32 max_recv_sge;
557 u32 max_inline_data;
558 u32 lkey;
559 u32 access_flags;
560 u16 total_chunks;
561 u16 send_chunks;
562 u16 max_atomic_arg;
563 u8 sq_sig_all;
564 u8 qp_type;
565 u8 is_srq;
566 u8 reserved[3];
567};
568
569struct pvrdma_cmd_create_qp_resp {
570 struct pvrdma_cmd_resp_hdr hdr;
571 u32 qpn;
572 u32 max_send_wr;
573 u32 max_recv_wr;
574 u32 max_send_sge;
575 u32 max_recv_sge;
576 u32 max_inline_data;
577};
578
579struct pvrdma_cmd_modify_qp {
580 struct pvrdma_cmd_hdr hdr;
581 u32 qp_handle;
582 u32 attr_mask;
583 struct pvrdma_qp_attr attrs;
584};
585
586struct pvrdma_cmd_query_qp {
587 struct pvrdma_cmd_hdr hdr;
588 u32 qp_handle;
589 u32 attr_mask;
590};
591
592struct pvrdma_cmd_query_qp_resp {
593 struct pvrdma_cmd_resp_hdr hdr;
594 struct pvrdma_qp_attr attrs;
595};
596
597struct pvrdma_cmd_destroy_qp {
598 struct pvrdma_cmd_hdr hdr;
599 u32 qp_handle;
600 u8 reserved[4];
601};
602
603struct pvrdma_cmd_destroy_qp_resp {
604 struct pvrdma_cmd_resp_hdr hdr;
605 u32 events_reported;
606 u8 reserved[4];
607};
608
609struct pvrdma_cmd_create_bind {
610 struct pvrdma_cmd_hdr hdr;
611 u32 mtu;
612 u32 vlan;
613 u32 index;
614 u8 new_gid[16];
615 u8 gid_type;
616 u8 reserved[3];
617};
618
619struct pvrdma_cmd_destroy_bind {
620 struct pvrdma_cmd_hdr hdr;
621 u32 index;
622 u8 dest_gid[16];
623 u8 reserved[4];
624};
625
626union pvrdma_cmd_req {
627 struct pvrdma_cmd_hdr hdr;
628 struct pvrdma_cmd_query_port query_port;
629 struct pvrdma_cmd_query_pkey query_pkey;
630 struct pvrdma_cmd_create_uc create_uc;
631 struct pvrdma_cmd_destroy_uc destroy_uc;
632 struct pvrdma_cmd_create_pd create_pd;
633 struct pvrdma_cmd_destroy_pd destroy_pd;
634 struct pvrdma_cmd_create_mr create_mr;
635 struct pvrdma_cmd_destroy_mr destroy_mr;
636 struct pvrdma_cmd_create_cq create_cq;
637 struct pvrdma_cmd_resize_cq resize_cq;
638 struct pvrdma_cmd_destroy_cq destroy_cq;
639 struct pvrdma_cmd_create_qp create_qp;
640 struct pvrdma_cmd_modify_qp modify_qp;
641 struct pvrdma_cmd_query_qp query_qp;
642 struct pvrdma_cmd_destroy_qp destroy_qp;
643 struct pvrdma_cmd_create_bind create_bind;
644 struct pvrdma_cmd_destroy_bind destroy_bind;
645 struct pvrdma_cmd_create_srq create_srq;
646 struct pvrdma_cmd_modify_srq modify_srq;
647 struct pvrdma_cmd_query_srq query_srq;
648 struct pvrdma_cmd_destroy_srq destroy_srq;
649};
650
651union pvrdma_cmd_resp {
652 struct pvrdma_cmd_resp_hdr hdr;
653 struct pvrdma_cmd_query_port_resp query_port_resp;
654 struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
655 struct pvrdma_cmd_create_uc_resp create_uc_resp;
656 struct pvrdma_cmd_create_pd_resp create_pd_resp;
657 struct pvrdma_cmd_create_mr_resp create_mr_resp;
658 struct pvrdma_cmd_create_cq_resp create_cq_resp;
659 struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
660 struct pvrdma_cmd_create_qp_resp create_qp_resp;
661 struct pvrdma_cmd_query_qp_resp query_qp_resp;
662 struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
663 struct pvrdma_cmd_create_srq_resp create_srq_resp;
664 struct pvrdma_cmd_query_srq_resp query_srq_resp;
665};
666
667#endif
668