linux/drivers/irqchip/irq-bcm6345-l1.c
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   1/*
   2 * Broadcom BCM6345 style Level 1 interrupt controller driver
   3 *
   4 * Copyright (C) 2014 Broadcom Corporation
   5 * Copyright 2015 Simon Arlott
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * This is based on the BCM7038 (which supports SMP) but with a single
  12 * enable register instead of separate mask/set/clear registers.
  13 *
  14 * The BCM3380 has a similar mask/status register layout, but each pair
  15 * of words is at separate locations (and SMP is not supported).
  16 *
  17 * ENABLE/STATUS words are packed next to each other for each CPU:
  18 *
  19 * BCM6368:
  20 *   0x1000_0020: CPU0_W0_ENABLE
  21 *   0x1000_0024: CPU0_W1_ENABLE
  22 *   0x1000_0028: CPU0_W0_STATUS                IRQs 31-63
  23 *   0x1000_002c: CPU0_W1_STATUS                IRQs 0-31
  24 *   0x1000_0030: CPU1_W0_ENABLE
  25 *   0x1000_0034: CPU1_W1_ENABLE
  26 *   0x1000_0038: CPU1_W0_STATUS                IRQs 31-63
  27 *   0x1000_003c: CPU1_W1_STATUS                IRQs 0-31
  28 *
  29 * BCM63168:
  30 *   0x1000_0020: CPU0_W0_ENABLE
  31 *   0x1000_0024: CPU0_W1_ENABLE
  32 *   0x1000_0028: CPU0_W2_ENABLE
  33 *   0x1000_002c: CPU0_W3_ENABLE
  34 *   0x1000_0030: CPU0_W0_STATUS        IRQs 96-127
  35 *   0x1000_0034: CPU0_W1_STATUS        IRQs 64-95
  36 *   0x1000_0038: CPU0_W2_STATUS        IRQs 32-63
  37 *   0x1000_003c: CPU0_W3_STATUS        IRQs 0-31
  38 *   0x1000_0040: CPU1_W0_ENABLE
  39 *   0x1000_0044: CPU1_W1_ENABLE
  40 *   0x1000_0048: CPU1_W2_ENABLE
  41 *   0x1000_004c: CPU1_W3_ENABLE
  42 *   0x1000_0050: CPU1_W0_STATUS        IRQs 96-127
  43 *   0x1000_0054: CPU1_W1_STATUS        IRQs 64-95
  44 *   0x1000_0058: CPU1_W2_STATUS        IRQs 32-63
  45 *   0x1000_005c: CPU1_W3_STATUS        IRQs 0-31
  46 *
  47 * IRQs are numbered in CPU native endian order
  48 * (which is big-endian in these examples)
  49 */
  50
  51#define pr_fmt(fmt)     KBUILD_MODNAME  ": " fmt
  52
  53#include <linux/bitops.h>
  54#include <linux/cpumask.h>
  55#include <linux/kernel.h>
  56#include <linux/init.h>
  57#include <linux/interrupt.h>
  58#include <linux/io.h>
  59#include <linux/ioport.h>
  60#include <linux/irq.h>
  61#include <linux/irqdomain.h>
  62#include <linux/module.h>
  63#include <linux/of.h>
  64#include <linux/of_irq.h>
  65#include <linux/of_address.h>
  66#include <linux/of_platform.h>
  67#include <linux/platform_device.h>
  68#include <linux/slab.h>
  69#include <linux/smp.h>
  70#include <linux/types.h>
  71#include <linux/irqchip.h>
  72#include <linux/irqchip/chained_irq.h>
  73
  74#define IRQS_PER_WORD           32
  75#define REG_BYTES_PER_IRQ_WORD  (sizeof(u32) * 2)
  76
  77struct bcm6345_l1_cpu;
  78
  79struct bcm6345_l1_chip {
  80        raw_spinlock_t          lock;
  81        unsigned int            n_words;
  82        struct irq_domain       *domain;
  83        struct cpumask          cpumask;
  84        struct bcm6345_l1_cpu   *cpus[NR_CPUS];
  85};
  86
  87struct bcm6345_l1_cpu {
  88        void __iomem            *map_base;
  89        unsigned int            parent_irq;
  90        u32                     enable_cache[];
  91};
  92
  93static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
  94                                           unsigned int word)
  95{
  96#ifdef __BIG_ENDIAN
  97        return (1 * intc->n_words - word - 1) * sizeof(u32);
  98#else
  99        return (0 * intc->n_words + word) * sizeof(u32);
 100#endif
 101}
 102
 103static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
 104                                      unsigned int word)
 105{
 106#ifdef __BIG_ENDIAN
 107        return (2 * intc->n_words - word - 1) * sizeof(u32);
 108#else
 109        return (1 * intc->n_words + word) * sizeof(u32);
 110#endif
 111}
 112
 113static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
 114                                        struct irq_data *d)
 115{
 116        return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
 117}
 118
 119static void bcm6345_l1_irq_handle(struct irq_desc *desc)
 120{
 121        struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
 122        struct bcm6345_l1_cpu *cpu;
 123        struct irq_chip *chip = irq_desc_get_chip(desc);
 124        unsigned int idx;
 125
 126#ifdef CONFIG_SMP
 127        cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
 128#else
 129        cpu = intc->cpus[0];
 130#endif
 131
 132        chained_irq_enter(chip, desc);
 133
 134        for (idx = 0; idx < intc->n_words; idx++) {
 135                int base = idx * IRQS_PER_WORD;
 136                unsigned long pending;
 137                irq_hw_number_t hwirq;
 138                unsigned int irq;
 139
 140                pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
 141                pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
 142
 143                for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
 144                        irq = irq_linear_revmap(intc->domain, base + hwirq);
 145                        if (irq)
 146                                do_IRQ(irq);
 147                        else
 148                                spurious_interrupt();
 149                }
 150        }
 151
 152        chained_irq_exit(chip, desc);
 153}
 154
 155static inline void __bcm6345_l1_unmask(struct irq_data *d)
 156{
 157        struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 158        u32 word = d->hwirq / IRQS_PER_WORD;
 159        u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 160        unsigned int cpu_idx = cpu_for_irq(intc, d);
 161
 162        intc->cpus[cpu_idx]->enable_cache[word] |= mask;
 163        __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
 164                intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
 165}
 166
 167static inline void __bcm6345_l1_mask(struct irq_data *d)
 168{
 169        struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 170        u32 word = d->hwirq / IRQS_PER_WORD;
 171        u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 172        unsigned int cpu_idx = cpu_for_irq(intc, d);
 173
 174        intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
 175        __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
 176                intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
 177}
 178
 179static void bcm6345_l1_unmask(struct irq_data *d)
 180{
 181        struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 182        unsigned long flags;
 183
 184        raw_spin_lock_irqsave(&intc->lock, flags);
 185        __bcm6345_l1_unmask(d);
 186        raw_spin_unlock_irqrestore(&intc->lock, flags);
 187}
 188
 189static void bcm6345_l1_mask(struct irq_data *d)
 190{
 191        struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 192        unsigned long flags;
 193
 194        raw_spin_lock_irqsave(&intc->lock, flags);
 195        __bcm6345_l1_mask(d);
 196        raw_spin_unlock_irqrestore(&intc->lock, flags);
 197}
 198
 199static int bcm6345_l1_set_affinity(struct irq_data *d,
 200                                   const struct cpumask *dest,
 201                                   bool force)
 202{
 203        struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
 204        u32 word = d->hwirq / IRQS_PER_WORD;
 205        u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
 206        unsigned int old_cpu = cpu_for_irq(intc, d);
 207        unsigned int new_cpu;
 208        struct cpumask valid;
 209        unsigned long flags;
 210        bool enabled;
 211
 212        if (!cpumask_and(&valid, &intc->cpumask, dest))
 213                return -EINVAL;
 214
 215        new_cpu = cpumask_any_and(&valid, cpu_online_mask);
 216        if (new_cpu >= nr_cpu_ids)
 217                return -EINVAL;
 218
 219        dest = cpumask_of(new_cpu);
 220
 221        raw_spin_lock_irqsave(&intc->lock, flags);
 222        if (old_cpu != new_cpu) {
 223                enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
 224                if (enabled)
 225                        __bcm6345_l1_mask(d);
 226                cpumask_copy(irq_data_get_affinity_mask(d), dest);
 227                if (enabled)
 228                        __bcm6345_l1_unmask(d);
 229        } else {
 230                cpumask_copy(irq_data_get_affinity_mask(d), dest);
 231        }
 232        raw_spin_unlock_irqrestore(&intc->lock, flags);
 233
 234        irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
 235
 236        return IRQ_SET_MASK_OK_NOCOPY;
 237}
 238
 239static int __init bcm6345_l1_init_one(struct device_node *dn,
 240                                      unsigned int idx,
 241                                      struct bcm6345_l1_chip *intc)
 242{
 243        struct resource res;
 244        resource_size_t sz;
 245        struct bcm6345_l1_cpu *cpu;
 246        unsigned int i, n_words;
 247
 248        if (of_address_to_resource(dn, idx, &res))
 249                return -EINVAL;
 250        sz = resource_size(&res);
 251        n_words = sz / REG_BYTES_PER_IRQ_WORD;
 252
 253        if (!intc->n_words)
 254                intc->n_words = n_words;
 255        else if (intc->n_words != n_words)
 256                return -EINVAL;
 257
 258        cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
 259                                        GFP_KERNEL);
 260        if (!cpu)
 261                return -ENOMEM;
 262
 263        cpu->map_base = ioremap(res.start, sz);
 264        if (!cpu->map_base)
 265                return -ENOMEM;
 266
 267        for (i = 0; i < n_words; i++) {
 268                cpu->enable_cache[i] = 0;
 269                __raw_writel(0, cpu->map_base + reg_enable(intc, i));
 270        }
 271
 272        cpu->parent_irq = irq_of_parse_and_map(dn, idx);
 273        if (!cpu->parent_irq) {
 274                pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
 275                return -EINVAL;
 276        }
 277        irq_set_chained_handler_and_data(cpu->parent_irq,
 278                                                bcm6345_l1_irq_handle, intc);
 279
 280        return 0;
 281}
 282
 283static struct irq_chip bcm6345_l1_irq_chip = {
 284        .name                   = "bcm6345-l1",
 285        .irq_mask               = bcm6345_l1_mask,
 286        .irq_unmask             = bcm6345_l1_unmask,
 287        .irq_set_affinity       = bcm6345_l1_set_affinity,
 288};
 289
 290static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
 291                          irq_hw_number_t hw_irq)
 292{
 293        irq_set_chip_and_handler(virq,
 294                &bcm6345_l1_irq_chip, handle_percpu_irq);
 295        irq_set_chip_data(virq, d->host_data);
 296        irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 297        return 0;
 298}
 299
 300static const struct irq_domain_ops bcm6345_l1_domain_ops = {
 301        .xlate                  = irq_domain_xlate_onecell,
 302        .map                    = bcm6345_l1_map,
 303};
 304
 305static int __init bcm6345_l1_of_init(struct device_node *dn,
 306                              struct device_node *parent)
 307{
 308        struct bcm6345_l1_chip *intc;
 309        unsigned int idx;
 310        int ret;
 311
 312        intc = kzalloc(sizeof(*intc), GFP_KERNEL);
 313        if (!intc)
 314                return -ENOMEM;
 315
 316        for_each_possible_cpu(idx) {
 317                ret = bcm6345_l1_init_one(dn, idx, intc);
 318                if (ret)
 319                        pr_err("failed to init intc L1 for cpu %d: %d\n",
 320                                idx, ret);
 321                else
 322                        cpumask_set_cpu(idx, &intc->cpumask);
 323        }
 324
 325        if (!cpumask_weight(&intc->cpumask)) {
 326                ret = -ENODEV;
 327                goto out_free;
 328        }
 329
 330        raw_spin_lock_init(&intc->lock);
 331
 332        intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
 333                                             &bcm6345_l1_domain_ops,
 334                                             intc);
 335        if (!intc->domain) {
 336                ret = -ENOMEM;
 337                goto out_unmap;
 338        }
 339
 340        pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
 341                        IRQS_PER_WORD * intc->n_words);
 342        for_each_cpu(idx, &intc->cpumask) {
 343                struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
 344
 345                pr_info("  CPU%u at MMIO 0x%p (irq = %d)\n", idx,
 346                                cpu->map_base, cpu->parent_irq);
 347        }
 348
 349        return 0;
 350
 351out_unmap:
 352        for_each_possible_cpu(idx) {
 353                struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
 354
 355                if (cpu) {
 356                        if (cpu->map_base)
 357                                iounmap(cpu->map_base);
 358                        kfree(cpu);
 359                }
 360        }
 361out_free:
 362        kfree(intc);
 363        return ret;
 364}
 365
 366IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);
 367