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6#include <linux/err.h>
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/irqchip.h>
10#include <linux/irqdomain.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_device.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/types.h>
20
21#define PDC_MAX_IRQS 126
22
23#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
24#define ENABLE_INTR(reg, intr) (reg | (1 << intr))
25
26#define IRQ_ENABLE_BANK 0x10
27#define IRQ_i_CFG 0x110
28
29struct pdc_pin_region {
30 u32 pin_base;
31 u32 parent_base;
32 u32 cnt;
33};
34
35static DEFINE_RAW_SPINLOCK(pdc_lock);
36static void __iomem *pdc_base;
37static struct pdc_pin_region *pdc_region;
38static int pdc_region_cnt;
39
40static void pdc_reg_write(int reg, u32 i, u32 val)
41{
42 writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
43}
44
45static u32 pdc_reg_read(int reg, u32 i)
46{
47 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
48}
49
50static void pdc_enable_intr(struct irq_data *d, bool on)
51{
52 int pin_out = d->hwirq;
53 u32 index, mask;
54 u32 enable;
55
56 index = pin_out / 32;
57 mask = pin_out % 32;
58
59 raw_spin_lock(&pdc_lock);
60 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
61 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
62 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
63 raw_spin_unlock(&pdc_lock);
64}
65
66static void qcom_pdc_gic_mask(struct irq_data *d)
67{
68 pdc_enable_intr(d, false);
69 irq_chip_mask_parent(d);
70}
71
72static void qcom_pdc_gic_unmask(struct irq_data *d)
73{
74 pdc_enable_intr(d, true);
75 irq_chip_unmask_parent(d);
76}
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92
93enum pdc_irq_config_bits {
94 PDC_LEVEL_LOW = 0b000,
95 PDC_EDGE_FALLING = 0b010,
96 PDC_LEVEL_HIGH = 0b100,
97 PDC_EDGE_RISING = 0b110,
98 PDC_EDGE_DUAL = 0b111,
99};
100
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111
112static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
113{
114 int pin_out = d->hwirq;
115 enum pdc_irq_config_bits pdc_type;
116
117 switch (type) {
118 case IRQ_TYPE_EDGE_RISING:
119 pdc_type = PDC_EDGE_RISING;
120 break;
121 case IRQ_TYPE_EDGE_FALLING:
122 pdc_type = PDC_EDGE_FALLING;
123 type = IRQ_TYPE_EDGE_RISING;
124 break;
125 case IRQ_TYPE_EDGE_BOTH:
126 pdc_type = PDC_EDGE_DUAL;
127 type = IRQ_TYPE_EDGE_RISING;
128 break;
129 case IRQ_TYPE_LEVEL_HIGH:
130 pdc_type = PDC_LEVEL_HIGH;
131 break;
132 case IRQ_TYPE_LEVEL_LOW:
133 pdc_type = PDC_LEVEL_LOW;
134 type = IRQ_TYPE_LEVEL_HIGH;
135 break;
136 default:
137 WARN_ON(1);
138 return -EINVAL;
139 }
140
141 pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
142
143 return irq_chip_set_type_parent(d, type);
144}
145
146static struct irq_chip qcom_pdc_gic_chip = {
147 .name = "PDC",
148 .irq_eoi = irq_chip_eoi_parent,
149 .irq_mask = qcom_pdc_gic_mask,
150 .irq_unmask = qcom_pdc_gic_unmask,
151 .irq_retrigger = irq_chip_retrigger_hierarchy,
152 .irq_set_type = qcom_pdc_gic_set_type,
153 .flags = IRQCHIP_MASK_ON_SUSPEND |
154 IRQCHIP_SET_TYPE_MASKED |
155 IRQCHIP_SKIP_SET_WAKE,
156 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
157 .irq_set_affinity = irq_chip_set_affinity_parent,
158};
159
160static irq_hw_number_t get_parent_hwirq(int pin)
161{
162 int i;
163 struct pdc_pin_region *region;
164
165 for (i = 0; i < pdc_region_cnt; i++) {
166 region = &pdc_region[i];
167 if (pin >= region->pin_base &&
168 pin < region->pin_base + region->cnt)
169 return (region->parent_base + pin - region->pin_base);
170 }
171
172 WARN_ON(1);
173 return ~0UL;
174}
175
176static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
177 unsigned long *hwirq, unsigned int *type)
178{
179 if (is_of_node(fwspec->fwnode)) {
180 if (fwspec->param_count != 2)
181 return -EINVAL;
182
183 *hwirq = fwspec->param[0];
184 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
185 return 0;
186 }
187
188 return -EINVAL;
189}
190
191static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
192 unsigned int nr_irqs, void *data)
193{
194 struct irq_fwspec *fwspec = data;
195 struct irq_fwspec parent_fwspec;
196 irq_hw_number_t hwirq, parent_hwirq;
197 unsigned int type;
198 int ret;
199
200 ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
201 if (ret)
202 return -EINVAL;
203
204 parent_hwirq = get_parent_hwirq(hwirq);
205 if (parent_hwirq == ~0UL)
206 return -EINVAL;
207
208 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
209 &qcom_pdc_gic_chip, NULL);
210 if (ret)
211 return ret;
212
213 if (type & IRQ_TYPE_EDGE_BOTH)
214 type = IRQ_TYPE_EDGE_RISING;
215
216 if (type & IRQ_TYPE_LEVEL_MASK)
217 type = IRQ_TYPE_LEVEL_HIGH;
218
219 parent_fwspec.fwnode = domain->parent->fwnode;
220 parent_fwspec.param_count = 3;
221 parent_fwspec.param[0] = 0;
222 parent_fwspec.param[1] = parent_hwirq;
223 parent_fwspec.param[2] = type;
224
225 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
226 &parent_fwspec);
227}
228
229static const struct irq_domain_ops qcom_pdc_ops = {
230 .translate = qcom_pdc_translate,
231 .alloc = qcom_pdc_alloc,
232 .free = irq_domain_free_irqs_common,
233};
234
235static int pdc_setup_pin_mapping(struct device_node *np)
236{
237 int ret, n;
238
239 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
240 if (n <= 0 || n % 3)
241 return -EINVAL;
242
243 pdc_region_cnt = n / 3;
244 pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
245 if (!pdc_region) {
246 pdc_region_cnt = 0;
247 return -ENOMEM;
248 }
249
250 for (n = 0; n < pdc_region_cnt; n++) {
251 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
252 n * 3 + 0,
253 &pdc_region[n].pin_base);
254 if (ret)
255 return ret;
256 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
257 n * 3 + 1,
258 &pdc_region[n].parent_base);
259 if (ret)
260 return ret;
261 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
262 n * 3 + 2,
263 &pdc_region[n].cnt);
264 if (ret)
265 return ret;
266 }
267
268 return 0;
269}
270
271static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
272{
273 struct irq_domain *parent_domain, *pdc_domain;
274 int ret;
275
276 pdc_base = of_iomap(node, 0);
277 if (!pdc_base) {
278 pr_err("%pOF: unable to map PDC registers\n", node);
279 return -ENXIO;
280 }
281
282 parent_domain = irq_find_host(parent);
283 if (!parent_domain) {
284 pr_err("%pOF: unable to find PDC's parent domain\n", node);
285 ret = -ENXIO;
286 goto fail;
287 }
288
289 ret = pdc_setup_pin_mapping(node);
290 if (ret) {
291 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
292 goto fail;
293 }
294
295 pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
296 of_fwnode_handle(node),
297 &qcom_pdc_ops, NULL);
298 if (!pdc_domain) {
299 pr_err("%pOF: GIC domain add failed\n", node);
300 ret = -ENOMEM;
301 goto fail;
302 }
303
304 return 0;
305
306fail:
307 kfree(pdc_region);
308 iounmap(pdc_base);
309 return ret;
310}
311
312IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
313
