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117#ifndef __XGBE_COMMON_H__
118#define __XGBE_COMMON_H__
119
120
121#define DMA_MR 0x3000
122#define DMA_SBMR 0x3004
123#define DMA_ISR 0x3008
124#define DMA_AXIARCR 0x3010
125#define DMA_AXIAWCR 0x3018
126#define DMA_AXIAWARCR 0x301c
127#define DMA_DSR0 0x3020
128#define DMA_DSR1 0x3024
129#define DMA_TXEDMACR 0x3040
130#define DMA_RXEDMACR 0x3044
131
132
133#define DMA_ISR_MACIS_INDEX 17
134#define DMA_ISR_MACIS_WIDTH 1
135#define DMA_ISR_MTLIS_INDEX 16
136#define DMA_ISR_MTLIS_WIDTH 1
137#define DMA_MR_INTM_INDEX 12
138#define DMA_MR_INTM_WIDTH 2
139#define DMA_MR_SWR_INDEX 0
140#define DMA_MR_SWR_WIDTH 1
141#define DMA_RXEDMACR_RDPS_INDEX 0
142#define DMA_RXEDMACR_RDPS_WIDTH 3
143#define DMA_SBMR_AAL_INDEX 12
144#define DMA_SBMR_AAL_WIDTH 1
145#define DMA_SBMR_EAME_INDEX 11
146#define DMA_SBMR_EAME_WIDTH 1
147#define DMA_SBMR_BLEN_INDEX 1
148#define DMA_SBMR_BLEN_WIDTH 7
149#define DMA_SBMR_RD_OSR_LMT_INDEX 16
150#define DMA_SBMR_RD_OSR_LMT_WIDTH 6
151#define DMA_SBMR_UNDEF_INDEX 0
152#define DMA_SBMR_UNDEF_WIDTH 1
153#define DMA_SBMR_WR_OSR_LMT_INDEX 24
154#define DMA_SBMR_WR_OSR_LMT_WIDTH 6
155#define DMA_TXEDMACR_TDPS_INDEX 0
156#define DMA_TXEDMACR_TDPS_WIDTH 3
157
158
159#define DMA_SBMR_BLEN_256 256
160#define DMA_SBMR_BLEN_128 128
161#define DMA_SBMR_BLEN_64 64
162#define DMA_SBMR_BLEN_32 32
163#define DMA_SBMR_BLEN_16 16
164#define DMA_SBMR_BLEN_8 8
165#define DMA_SBMR_BLEN_4 4
166#define DMA_DSR_RPS_WIDTH 4
167#define DMA_DSR_TPS_WIDTH 4
168#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
169#define DMA_DSR0_RPS_START 8
170#define DMA_DSR0_TPS_START 12
171#define DMA_DSRX_FIRST_QUEUE 3
172#define DMA_DSRX_INC 4
173#define DMA_DSRX_QPR 4
174#define DMA_DSRX_RPS_START 0
175#define DMA_DSRX_TPS_START 4
176#define DMA_TPS_STOPPED 0x00
177#define DMA_TPS_SUSPENDED 0x06
178
179
180
181
182
183
184#define DMA_CH_BASE 0x3100
185#define DMA_CH_INC 0x80
186
187#define DMA_CH_CR 0x00
188#define DMA_CH_TCR 0x04
189#define DMA_CH_RCR 0x08
190#define DMA_CH_TDLR_HI 0x10
191#define DMA_CH_TDLR_LO 0x14
192#define DMA_CH_RDLR_HI 0x18
193#define DMA_CH_RDLR_LO 0x1c
194#define DMA_CH_TDTR_LO 0x24
195#define DMA_CH_RDTR_LO 0x2c
196#define DMA_CH_TDRLR 0x30
197#define DMA_CH_RDRLR 0x34
198#define DMA_CH_IER 0x38
199#define DMA_CH_RIWT 0x3c
200#define DMA_CH_CATDR_LO 0x44
201#define DMA_CH_CARDR_LO 0x4c
202#define DMA_CH_CATBR_HI 0x50
203#define DMA_CH_CATBR_LO 0x54
204#define DMA_CH_CARBR_HI 0x58
205#define DMA_CH_CARBR_LO 0x5c
206#define DMA_CH_SR 0x60
207
208
209#define DMA_CH_CR_PBLX8_INDEX 16
210#define DMA_CH_CR_PBLX8_WIDTH 1
211#define DMA_CH_CR_SPH_INDEX 24
212#define DMA_CH_CR_SPH_WIDTH 1
213#define DMA_CH_IER_AIE20_INDEX 15
214#define DMA_CH_IER_AIE20_WIDTH 1
215#define DMA_CH_IER_AIE_INDEX 14
216#define DMA_CH_IER_AIE_WIDTH 1
217#define DMA_CH_IER_FBEE_INDEX 12
218#define DMA_CH_IER_FBEE_WIDTH 1
219#define DMA_CH_IER_NIE20_INDEX 16
220#define DMA_CH_IER_NIE20_WIDTH 1
221#define DMA_CH_IER_NIE_INDEX 15
222#define DMA_CH_IER_NIE_WIDTH 1
223#define DMA_CH_IER_RBUE_INDEX 7
224#define DMA_CH_IER_RBUE_WIDTH 1
225#define DMA_CH_IER_RIE_INDEX 6
226#define DMA_CH_IER_RIE_WIDTH 1
227#define DMA_CH_IER_RSE_INDEX 8
228#define DMA_CH_IER_RSE_WIDTH 1
229#define DMA_CH_IER_TBUE_INDEX 2
230#define DMA_CH_IER_TBUE_WIDTH 1
231#define DMA_CH_IER_TIE_INDEX 0
232#define DMA_CH_IER_TIE_WIDTH 1
233#define DMA_CH_IER_TXSE_INDEX 1
234#define DMA_CH_IER_TXSE_WIDTH 1
235#define DMA_CH_RCR_PBL_INDEX 16
236#define DMA_CH_RCR_PBL_WIDTH 6
237#define DMA_CH_RCR_RBSZ_INDEX 1
238#define DMA_CH_RCR_RBSZ_WIDTH 14
239#define DMA_CH_RCR_SR_INDEX 0
240#define DMA_CH_RCR_SR_WIDTH 1
241#define DMA_CH_RIWT_RWT_INDEX 0
242#define DMA_CH_RIWT_RWT_WIDTH 8
243#define DMA_CH_SR_FBE_INDEX 12
244#define DMA_CH_SR_FBE_WIDTH 1
245#define DMA_CH_SR_RBU_INDEX 7
246#define DMA_CH_SR_RBU_WIDTH 1
247#define DMA_CH_SR_RI_INDEX 6
248#define DMA_CH_SR_RI_WIDTH 1
249#define DMA_CH_SR_RPS_INDEX 8
250#define DMA_CH_SR_RPS_WIDTH 1
251#define DMA_CH_SR_TBU_INDEX 2
252#define DMA_CH_SR_TBU_WIDTH 1
253#define DMA_CH_SR_TI_INDEX 0
254#define DMA_CH_SR_TI_WIDTH 1
255#define DMA_CH_SR_TPS_INDEX 1
256#define DMA_CH_SR_TPS_WIDTH 1
257#define DMA_CH_TCR_OSP_INDEX 4
258#define DMA_CH_TCR_OSP_WIDTH 1
259#define DMA_CH_TCR_PBL_INDEX 16
260#define DMA_CH_TCR_PBL_WIDTH 6
261#define DMA_CH_TCR_ST_INDEX 0
262#define DMA_CH_TCR_ST_WIDTH 1
263#define DMA_CH_TCR_TSE_INDEX 12
264#define DMA_CH_TCR_TSE_WIDTH 1
265
266
267#define DMA_OSP_DISABLE 0x00
268#define DMA_OSP_ENABLE 0x01
269#define DMA_PBL_1 1
270#define DMA_PBL_2 2
271#define DMA_PBL_4 4
272#define DMA_PBL_8 8
273#define DMA_PBL_16 16
274#define DMA_PBL_32 32
275#define DMA_PBL_64 64
276#define DMA_PBL_128 128
277#define DMA_PBL_256 256
278#define DMA_PBL_X8_DISABLE 0x00
279#define DMA_PBL_X8_ENABLE 0x01
280
281
282#define MAC_TCR 0x0000
283#define MAC_RCR 0x0004
284#define MAC_PFR 0x0008
285#define MAC_WTR 0x000c
286#define MAC_HTR0 0x0010
287#define MAC_VLANTR 0x0050
288#define MAC_VLANHTR 0x0058
289#define MAC_VLANIR 0x0060
290#define MAC_IVLANIR 0x0064
291#define MAC_RETMR 0x006c
292#define MAC_Q0TFCR 0x0070
293#define MAC_RFCR 0x0090
294#define MAC_RQC0R 0x00a0
295#define MAC_RQC1R 0x00a4
296#define MAC_RQC2R 0x00a8
297#define MAC_RQC3R 0x00ac
298#define MAC_ISR 0x00b0
299#define MAC_IER 0x00b4
300#define MAC_RTSR 0x00b8
301#define MAC_PMTCSR 0x00c0
302#define MAC_RWKPFR 0x00c4
303#define MAC_LPICSR 0x00d0
304#define MAC_LPITCR 0x00d4
305#define MAC_TIR 0x00e0
306#define MAC_VR 0x0110
307#define MAC_DR 0x0114
308#define MAC_HWF0R 0x011c
309#define MAC_HWF1R 0x0120
310#define MAC_HWF2R 0x0124
311#define MAC_MDIOSCAR 0x0200
312#define MAC_MDIOSCCDR 0x0204
313#define MAC_MDIOISR 0x0214
314#define MAC_MDIOIER 0x0218
315#define MAC_MDIOCL22R 0x0220
316#define MAC_GPIOCR 0x0278
317#define MAC_GPIOSR 0x027c
318#define MAC_MACA0HR 0x0300
319#define MAC_MACA0LR 0x0304
320#define MAC_MACA1HR 0x0308
321#define MAC_MACA1LR 0x030c
322#define MAC_RSSCR 0x0c80
323#define MAC_RSSAR 0x0c88
324#define MAC_RSSDR 0x0c8c
325#define MAC_TSCR 0x0d00
326#define MAC_SSIR 0x0d04
327#define MAC_STSR 0x0d08
328#define MAC_STNR 0x0d0c
329#define MAC_STSUR 0x0d10
330#define MAC_STNUR 0x0d14
331#define MAC_TSAR 0x0d18
332#define MAC_TSSR 0x0d20
333#define MAC_TXSNR 0x0d30
334#define MAC_TXSSR 0x0d34
335
336#define MAC_QTFCR_INC 4
337#define MAC_MACA_INC 4
338#define MAC_HTR_INC 4
339
340#define MAC_RQC2_INC 4
341#define MAC_RQC2_Q_PER_REG 4
342
343
344#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
345#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
346#define MAC_HWF0R_ARPOFFSEL_INDEX 9
347#define MAC_HWF0R_ARPOFFSEL_WIDTH 1
348#define MAC_HWF0R_EEESEL_INDEX 13
349#define MAC_HWF0R_EEESEL_WIDTH 1
350#define MAC_HWF0R_GMIISEL_INDEX 1
351#define MAC_HWF0R_GMIISEL_WIDTH 1
352#define MAC_HWF0R_MGKSEL_INDEX 7
353#define MAC_HWF0R_MGKSEL_WIDTH 1
354#define MAC_HWF0R_MMCSEL_INDEX 8
355#define MAC_HWF0R_MMCSEL_WIDTH 1
356#define MAC_HWF0R_RWKSEL_INDEX 6
357#define MAC_HWF0R_RWKSEL_WIDTH 1
358#define MAC_HWF0R_RXCOESEL_INDEX 16
359#define MAC_HWF0R_RXCOESEL_WIDTH 1
360#define MAC_HWF0R_SAVLANINS_INDEX 27
361#define MAC_HWF0R_SAVLANINS_WIDTH 1
362#define MAC_HWF0R_SMASEL_INDEX 5
363#define MAC_HWF0R_SMASEL_WIDTH 1
364#define MAC_HWF0R_TSSEL_INDEX 12
365#define MAC_HWF0R_TSSEL_WIDTH 1
366#define MAC_HWF0R_TSSTSSEL_INDEX 25
367#define MAC_HWF0R_TSSTSSEL_WIDTH 2
368#define MAC_HWF0R_TXCOESEL_INDEX 14
369#define MAC_HWF0R_TXCOESEL_WIDTH 1
370#define MAC_HWF0R_VLHASH_INDEX 4
371#define MAC_HWF0R_VLHASH_WIDTH 1
372#define MAC_HWF0R_VXN_INDEX 29
373#define MAC_HWF0R_VXN_WIDTH 1
374#define MAC_HWF1R_ADDR64_INDEX 14
375#define MAC_HWF1R_ADDR64_WIDTH 2
376#define MAC_HWF1R_ADVTHWORD_INDEX 13
377#define MAC_HWF1R_ADVTHWORD_WIDTH 1
378#define MAC_HWF1R_DBGMEMA_INDEX 19
379#define MAC_HWF1R_DBGMEMA_WIDTH 1
380#define MAC_HWF1R_DCBEN_INDEX 16
381#define MAC_HWF1R_DCBEN_WIDTH 1
382#define MAC_HWF1R_HASHTBLSZ_INDEX 24
383#define MAC_HWF1R_HASHTBLSZ_WIDTH 3
384#define MAC_HWF1R_L3L4FNUM_INDEX 27
385#define MAC_HWF1R_L3L4FNUM_WIDTH 4
386#define MAC_HWF1R_NUMTC_INDEX 21
387#define MAC_HWF1R_NUMTC_WIDTH 3
388#define MAC_HWF1R_RSSEN_INDEX 20
389#define MAC_HWF1R_RSSEN_WIDTH 1
390#define MAC_HWF1R_RXFIFOSIZE_INDEX 0
391#define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
392#define MAC_HWF1R_SPHEN_INDEX 17
393#define MAC_HWF1R_SPHEN_WIDTH 1
394#define MAC_HWF1R_TSOEN_INDEX 18
395#define MAC_HWF1R_TSOEN_WIDTH 1
396#define MAC_HWF1R_TXFIFOSIZE_INDEX 6
397#define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
398#define MAC_HWF2R_AUXSNAPNUM_INDEX 28
399#define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
400#define MAC_HWF2R_PPSOUTNUM_INDEX 24
401#define MAC_HWF2R_PPSOUTNUM_WIDTH 3
402#define MAC_HWF2R_RXCHCNT_INDEX 12
403#define MAC_HWF2R_RXCHCNT_WIDTH 4
404#define MAC_HWF2R_RXQCNT_INDEX 0
405#define MAC_HWF2R_RXQCNT_WIDTH 4
406#define MAC_HWF2R_TXCHCNT_INDEX 18
407#define MAC_HWF2R_TXCHCNT_WIDTH 4
408#define MAC_HWF2R_TXQCNT_INDEX 6
409#define MAC_HWF2R_TXQCNT_WIDTH 4
410#define MAC_IER_TSIE_INDEX 12
411#define MAC_IER_TSIE_WIDTH 1
412#define MAC_ISR_MMCRXIS_INDEX 9
413#define MAC_ISR_MMCRXIS_WIDTH 1
414#define MAC_ISR_MMCTXIS_INDEX 10
415#define MAC_ISR_MMCTXIS_WIDTH 1
416#define MAC_ISR_PMTIS_INDEX 4
417#define MAC_ISR_PMTIS_WIDTH 1
418#define MAC_ISR_SMI_INDEX 1
419#define MAC_ISR_SMI_WIDTH 1
420#define MAC_ISR_TSIS_INDEX 12
421#define MAC_ISR_TSIS_WIDTH 1
422#define MAC_MACA1HR_AE_INDEX 31
423#define MAC_MACA1HR_AE_WIDTH 1
424#define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
425#define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
426#define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
427#define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
428#define MAC_MDIOSCAR_DA_INDEX 21
429#define MAC_MDIOSCAR_DA_WIDTH 5
430#define MAC_MDIOSCAR_PA_INDEX 16
431#define MAC_MDIOSCAR_PA_WIDTH 5
432#define MAC_MDIOSCAR_RA_INDEX 0
433#define MAC_MDIOSCAR_RA_WIDTH 16
434#define MAC_MDIOSCCDR_BUSY_INDEX 22
435#define MAC_MDIOSCCDR_BUSY_WIDTH 1
436#define MAC_MDIOSCCDR_CMD_INDEX 16
437#define MAC_MDIOSCCDR_CMD_WIDTH 2
438#define MAC_MDIOSCCDR_CR_INDEX 19
439#define MAC_MDIOSCCDR_CR_WIDTH 3
440#define MAC_MDIOSCCDR_DATA_INDEX 0
441#define MAC_MDIOSCCDR_DATA_WIDTH 16
442#define MAC_MDIOSCCDR_SADDR_INDEX 18
443#define MAC_MDIOSCCDR_SADDR_WIDTH 1
444#define MAC_PFR_HMC_INDEX 2
445#define MAC_PFR_HMC_WIDTH 1
446#define MAC_PFR_HPF_INDEX 10
447#define MAC_PFR_HPF_WIDTH 1
448#define MAC_PFR_HUC_INDEX 1
449#define MAC_PFR_HUC_WIDTH 1
450#define MAC_PFR_PM_INDEX 4
451#define MAC_PFR_PM_WIDTH 1
452#define MAC_PFR_PR_INDEX 0
453#define MAC_PFR_PR_WIDTH 1
454#define MAC_PFR_VTFE_INDEX 16
455#define MAC_PFR_VTFE_WIDTH 1
456#define MAC_PFR_VUCC_INDEX 22
457#define MAC_PFR_VUCC_WIDTH 1
458#define MAC_PMTCSR_MGKPKTEN_INDEX 1
459#define MAC_PMTCSR_MGKPKTEN_WIDTH 1
460#define MAC_PMTCSR_PWRDWN_INDEX 0
461#define MAC_PMTCSR_PWRDWN_WIDTH 1
462#define MAC_PMTCSR_RWKFILTRST_INDEX 31
463#define MAC_PMTCSR_RWKFILTRST_WIDTH 1
464#define MAC_PMTCSR_RWKPKTEN_INDEX 2
465#define MAC_PMTCSR_RWKPKTEN_WIDTH 1
466#define MAC_Q0TFCR_PT_INDEX 16
467#define MAC_Q0TFCR_PT_WIDTH 16
468#define MAC_Q0TFCR_TFE_INDEX 1
469#define MAC_Q0TFCR_TFE_WIDTH 1
470#define MAC_RCR_ACS_INDEX 1
471#define MAC_RCR_ACS_WIDTH 1
472#define MAC_RCR_CST_INDEX 2
473#define MAC_RCR_CST_WIDTH 1
474#define MAC_RCR_DCRCC_INDEX 3
475#define MAC_RCR_DCRCC_WIDTH 1
476#define MAC_RCR_HDSMS_INDEX 12
477#define MAC_RCR_HDSMS_WIDTH 3
478#define MAC_RCR_IPC_INDEX 9
479#define MAC_RCR_IPC_WIDTH 1
480#define MAC_RCR_JE_INDEX 8
481#define MAC_RCR_JE_WIDTH 1
482#define MAC_RCR_LM_INDEX 10
483#define MAC_RCR_LM_WIDTH 1
484#define MAC_RCR_RE_INDEX 0
485#define MAC_RCR_RE_WIDTH 1
486#define MAC_RFCR_PFCE_INDEX 8
487#define MAC_RFCR_PFCE_WIDTH 1
488#define MAC_RFCR_RFE_INDEX 0
489#define MAC_RFCR_RFE_WIDTH 1
490#define MAC_RFCR_UP_INDEX 1
491#define MAC_RFCR_UP_WIDTH 1
492#define MAC_RQC0R_RXQ0EN_INDEX 0
493#define MAC_RQC0R_RXQ0EN_WIDTH 2
494#define MAC_RSSAR_ADDRT_INDEX 2
495#define MAC_RSSAR_ADDRT_WIDTH 1
496#define MAC_RSSAR_CT_INDEX 1
497#define MAC_RSSAR_CT_WIDTH 1
498#define MAC_RSSAR_OB_INDEX 0
499#define MAC_RSSAR_OB_WIDTH 1
500#define MAC_RSSAR_RSSIA_INDEX 8
501#define MAC_RSSAR_RSSIA_WIDTH 8
502#define MAC_RSSCR_IP2TE_INDEX 1
503#define MAC_RSSCR_IP2TE_WIDTH 1
504#define MAC_RSSCR_RSSE_INDEX 0
505#define MAC_RSSCR_RSSE_WIDTH 1
506#define MAC_RSSCR_TCP4TE_INDEX 2
507#define MAC_RSSCR_TCP4TE_WIDTH 1
508#define MAC_RSSCR_UDP4TE_INDEX 3
509#define MAC_RSSCR_UDP4TE_WIDTH 1
510#define MAC_RSSDR_DMCH_INDEX 0
511#define MAC_RSSDR_DMCH_WIDTH 4
512#define MAC_SSIR_SNSINC_INDEX 8
513#define MAC_SSIR_SNSINC_WIDTH 8
514#define MAC_SSIR_SSINC_INDEX 16
515#define MAC_SSIR_SSINC_WIDTH 8
516#define MAC_TCR_SS_INDEX 29
517#define MAC_TCR_SS_WIDTH 2
518#define MAC_TCR_TE_INDEX 0
519#define MAC_TCR_TE_WIDTH 1
520#define MAC_TCR_VNE_INDEX 24
521#define MAC_TCR_VNE_WIDTH 1
522#define MAC_TCR_VNM_INDEX 25
523#define MAC_TCR_VNM_WIDTH 1
524#define MAC_TIR_TNID_INDEX 0
525#define MAC_TIR_TNID_WIDTH 16
526#define MAC_TSCR_AV8021ASMEN_INDEX 28
527#define MAC_TSCR_AV8021ASMEN_WIDTH 1
528#define MAC_TSCR_SNAPTYPSEL_INDEX 16
529#define MAC_TSCR_SNAPTYPSEL_WIDTH 2
530#define MAC_TSCR_TSADDREG_INDEX 5
531#define MAC_TSCR_TSADDREG_WIDTH 1
532#define MAC_TSCR_TSCFUPDT_INDEX 1
533#define MAC_TSCR_TSCFUPDT_WIDTH 1
534#define MAC_TSCR_TSCTRLSSR_INDEX 9
535#define MAC_TSCR_TSCTRLSSR_WIDTH 1
536#define MAC_TSCR_TSENA_INDEX 0
537#define MAC_TSCR_TSENA_WIDTH 1
538#define MAC_TSCR_TSENALL_INDEX 8
539#define MAC_TSCR_TSENALL_WIDTH 1
540#define MAC_TSCR_TSEVNTENA_INDEX 14
541#define MAC_TSCR_TSEVNTENA_WIDTH 1
542#define MAC_TSCR_TSINIT_INDEX 2
543#define MAC_TSCR_TSINIT_WIDTH 1
544#define MAC_TSCR_TSIPENA_INDEX 11
545#define MAC_TSCR_TSIPENA_WIDTH 1
546#define MAC_TSCR_TSIPV4ENA_INDEX 13
547#define MAC_TSCR_TSIPV4ENA_WIDTH 1
548#define MAC_TSCR_TSIPV6ENA_INDEX 12
549#define MAC_TSCR_TSIPV6ENA_WIDTH 1
550#define MAC_TSCR_TSMSTRENA_INDEX 15
551#define MAC_TSCR_TSMSTRENA_WIDTH 1
552#define MAC_TSCR_TSVER2ENA_INDEX 10
553#define MAC_TSCR_TSVER2ENA_WIDTH 1
554#define MAC_TSCR_TXTSSTSM_INDEX 24
555#define MAC_TSCR_TXTSSTSM_WIDTH 1
556#define MAC_TSSR_TXTSC_INDEX 15
557#define MAC_TSSR_TXTSC_WIDTH 1
558#define MAC_TXSNR_TXTSSTSMIS_INDEX 31
559#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
560#define MAC_VLANHTR_VLHT_INDEX 0
561#define MAC_VLANHTR_VLHT_WIDTH 16
562#define MAC_VLANIR_VLTI_INDEX 20
563#define MAC_VLANIR_VLTI_WIDTH 1
564#define MAC_VLANIR_CSVL_INDEX 19
565#define MAC_VLANIR_CSVL_WIDTH 1
566#define MAC_VLANTR_DOVLTC_INDEX 20
567#define MAC_VLANTR_DOVLTC_WIDTH 1
568#define MAC_VLANTR_ERSVLM_INDEX 19
569#define MAC_VLANTR_ERSVLM_WIDTH 1
570#define MAC_VLANTR_ESVL_INDEX 18
571#define MAC_VLANTR_ESVL_WIDTH 1
572#define MAC_VLANTR_ETV_INDEX 16
573#define MAC_VLANTR_ETV_WIDTH 1
574#define MAC_VLANTR_EVLS_INDEX 21
575#define MAC_VLANTR_EVLS_WIDTH 2
576#define MAC_VLANTR_EVLRXS_INDEX 24
577#define MAC_VLANTR_EVLRXS_WIDTH 1
578#define MAC_VLANTR_VL_INDEX 0
579#define MAC_VLANTR_VL_WIDTH 16
580#define MAC_VLANTR_VTHM_INDEX 25
581#define MAC_VLANTR_VTHM_WIDTH 1
582#define MAC_VLANTR_VTIM_INDEX 17
583#define MAC_VLANTR_VTIM_WIDTH 1
584#define MAC_VR_DEVID_INDEX 8
585#define MAC_VR_DEVID_WIDTH 8
586#define MAC_VR_SNPSVER_INDEX 0
587#define MAC_VR_SNPSVER_WIDTH 8
588#define MAC_VR_USERVER_INDEX 16
589#define MAC_VR_USERVER_WIDTH 8
590
591
592#define MMC_CR 0x0800
593#define MMC_RISR 0x0804
594#define MMC_TISR 0x0808
595#define MMC_RIER 0x080c
596#define MMC_TIER 0x0810
597#define MMC_TXOCTETCOUNT_GB_LO 0x0814
598#define MMC_TXOCTETCOUNT_GB_HI 0x0818
599#define MMC_TXFRAMECOUNT_GB_LO 0x081c
600#define MMC_TXFRAMECOUNT_GB_HI 0x0820
601#define MMC_TXBROADCASTFRAMES_G_LO 0x0824
602#define MMC_TXBROADCASTFRAMES_G_HI 0x0828
603#define MMC_TXMULTICASTFRAMES_G_LO 0x082c
604#define MMC_TXMULTICASTFRAMES_G_HI 0x0830
605#define MMC_TX64OCTETS_GB_LO 0x0834
606#define MMC_TX64OCTETS_GB_HI 0x0838
607#define MMC_TX65TO127OCTETS_GB_LO 0x083c
608#define MMC_TX65TO127OCTETS_GB_HI 0x0840
609#define MMC_TX128TO255OCTETS_GB_LO 0x0844
610#define MMC_TX128TO255OCTETS_GB_HI 0x0848
611#define MMC_TX256TO511OCTETS_GB_LO 0x084c
612#define MMC_TX256TO511OCTETS_GB_HI 0x0850
613#define MMC_TX512TO1023OCTETS_GB_LO 0x0854
614#define MMC_TX512TO1023OCTETS_GB_HI 0x0858
615#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
616#define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
617#define MMC_TXUNICASTFRAMES_GB_LO 0x0864
618#define MMC_TXUNICASTFRAMES_GB_HI 0x0868
619#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
620#define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
621#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
622#define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
623#define MMC_TXUNDERFLOWERROR_LO 0x087c
624#define MMC_TXUNDERFLOWERROR_HI 0x0880
625#define MMC_TXOCTETCOUNT_G_LO 0x0884
626#define MMC_TXOCTETCOUNT_G_HI 0x0888
627#define MMC_TXFRAMECOUNT_G_LO 0x088c
628#define MMC_TXFRAMECOUNT_G_HI 0x0890
629#define MMC_TXPAUSEFRAMES_LO 0x0894
630#define MMC_TXPAUSEFRAMES_HI 0x0898
631#define MMC_TXVLANFRAMES_G_LO 0x089c
632#define MMC_TXVLANFRAMES_G_HI 0x08a0
633#define MMC_RXFRAMECOUNT_GB_LO 0x0900
634#define MMC_RXFRAMECOUNT_GB_HI 0x0904
635#define MMC_RXOCTETCOUNT_GB_LO 0x0908
636#define MMC_RXOCTETCOUNT_GB_HI 0x090c
637#define MMC_RXOCTETCOUNT_G_LO 0x0910
638#define MMC_RXOCTETCOUNT_G_HI 0x0914
639#define MMC_RXBROADCASTFRAMES_G_LO 0x0918
640#define MMC_RXBROADCASTFRAMES_G_HI 0x091c
641#define MMC_RXMULTICASTFRAMES_G_LO 0x0920
642#define MMC_RXMULTICASTFRAMES_G_HI 0x0924
643#define MMC_RXCRCERROR_LO 0x0928
644#define MMC_RXCRCERROR_HI 0x092c
645#define MMC_RXRUNTERROR 0x0930
646#define MMC_RXJABBERERROR 0x0934
647#define MMC_RXUNDERSIZE_G 0x0938
648#define MMC_RXOVERSIZE_G 0x093c
649#define MMC_RX64OCTETS_GB_LO 0x0940
650#define MMC_RX64OCTETS_GB_HI 0x0944
651#define MMC_RX65TO127OCTETS_GB_LO 0x0948
652#define MMC_RX65TO127OCTETS_GB_HI 0x094c
653#define MMC_RX128TO255OCTETS_GB_LO 0x0950
654#define MMC_RX128TO255OCTETS_GB_HI 0x0954
655#define MMC_RX256TO511OCTETS_GB_LO 0x0958
656#define MMC_RX256TO511OCTETS_GB_HI 0x095c
657#define MMC_RX512TO1023OCTETS_GB_LO 0x0960
658#define MMC_RX512TO1023OCTETS_GB_HI 0x0964
659#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
660#define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
661#define MMC_RXUNICASTFRAMES_G_LO 0x0970
662#define MMC_RXUNICASTFRAMES_G_HI 0x0974
663#define MMC_RXLENGTHERROR_LO 0x0978
664#define MMC_RXLENGTHERROR_HI 0x097c
665#define MMC_RXOUTOFRANGETYPE_LO 0x0980
666#define MMC_RXOUTOFRANGETYPE_HI 0x0984
667#define MMC_RXPAUSEFRAMES_LO 0x0988
668#define MMC_RXPAUSEFRAMES_HI 0x098c
669#define MMC_RXFIFOOVERFLOW_LO 0x0990
670#define MMC_RXFIFOOVERFLOW_HI 0x0994
671#define MMC_RXVLANFRAMES_GB_LO 0x0998
672#define MMC_RXVLANFRAMES_GB_HI 0x099c
673#define MMC_RXWATCHDOGERROR 0x09a0
674
675
676#define MMC_CR_CR_INDEX 0
677#define MMC_CR_CR_WIDTH 1
678#define MMC_CR_CSR_INDEX 1
679#define MMC_CR_CSR_WIDTH 1
680#define MMC_CR_ROR_INDEX 2
681#define MMC_CR_ROR_WIDTH 1
682#define MMC_CR_MCF_INDEX 3
683#define MMC_CR_MCF_WIDTH 1
684#define MMC_CR_MCT_INDEX 4
685#define MMC_CR_MCT_WIDTH 2
686#define MMC_RIER_ALL_INTERRUPTS_INDEX 0
687#define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
688#define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
689#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
690#define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
691#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
692#define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
693#define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
694#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
695#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
696#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
697#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
698#define MMC_RISR_RXCRCERROR_INDEX 5
699#define MMC_RISR_RXCRCERROR_WIDTH 1
700#define MMC_RISR_RXRUNTERROR_INDEX 6
701#define MMC_RISR_RXRUNTERROR_WIDTH 1
702#define MMC_RISR_RXJABBERERROR_INDEX 7
703#define MMC_RISR_RXJABBERERROR_WIDTH 1
704#define MMC_RISR_RXUNDERSIZE_G_INDEX 8
705#define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
706#define MMC_RISR_RXOVERSIZE_G_INDEX 9
707#define MMC_RISR_RXOVERSIZE_G_WIDTH 1
708#define MMC_RISR_RX64OCTETS_GB_INDEX 10
709#define MMC_RISR_RX64OCTETS_GB_WIDTH 1
710#define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
711#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
712#define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
713#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
714#define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
715#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
716#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
717#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
718#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
719#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
720#define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
721#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
722#define MMC_RISR_RXLENGTHERROR_INDEX 17
723#define MMC_RISR_RXLENGTHERROR_WIDTH 1
724#define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
725#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
726#define MMC_RISR_RXPAUSEFRAMES_INDEX 19
727#define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
728#define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
729#define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
730#define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
731#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
732#define MMC_RISR_RXWATCHDOGERROR_INDEX 22
733#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
734#define MMC_TIER_ALL_INTERRUPTS_INDEX 0
735#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
736#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
737#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
738#define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
739#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
740#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
741#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
742#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
743#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
744#define MMC_TISR_TX64OCTETS_GB_INDEX 4
745#define MMC_TISR_TX64OCTETS_GB_WIDTH 1
746#define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
747#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
748#define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
749#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
750#define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
751#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
752#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
753#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
754#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
755#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
756#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
757#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
758#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
759#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
760#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
761#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
762#define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
763#define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
764#define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
765#define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
766#define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
767#define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
768#define MMC_TISR_TXPAUSEFRAMES_INDEX 16
769#define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
770#define MMC_TISR_TXVLANFRAMES_G_INDEX 17
771#define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
772
773
774#define MTL_OMR 0x1000
775#define MTL_FDCR 0x1008
776#define MTL_FDSR 0x100c
777#define MTL_FDDR 0x1010
778#define MTL_ISR 0x1020
779#define MTL_RQDCM0R 0x1030
780#define MTL_TCPM0R 0x1040
781#define MTL_TCPM1R 0x1044
782
783#define MTL_RQDCM_INC 4
784#define MTL_RQDCM_Q_PER_REG 4
785#define MTL_TCPM_INC 4
786#define MTL_TCPM_TC_PER_REG 4
787
788
789#define MTL_OMR_ETSALG_INDEX 5
790#define MTL_OMR_ETSALG_WIDTH 2
791#define MTL_OMR_RAA_INDEX 2
792#define MTL_OMR_RAA_WIDTH 1
793
794
795
796
797
798
799#define MTL_Q_BASE 0x1100
800#define MTL_Q_INC 0x80
801
802#define MTL_Q_TQOMR 0x00
803#define MTL_Q_TQUR 0x04
804#define MTL_Q_TQDR 0x08
805#define MTL_Q_RQOMR 0x40
806#define MTL_Q_RQMPOCR 0x44
807#define MTL_Q_RQDR 0x48
808#define MTL_Q_RQFCR 0x50
809#define MTL_Q_IER 0x70
810#define MTL_Q_ISR 0x74
811
812
813#define MTL_Q_RQDR_PRXQ_INDEX 16
814#define MTL_Q_RQDR_PRXQ_WIDTH 14
815#define MTL_Q_RQDR_RXQSTS_INDEX 4
816#define MTL_Q_RQDR_RXQSTS_WIDTH 2
817#define MTL_Q_RQFCR_RFA_INDEX 1
818#define MTL_Q_RQFCR_RFA_WIDTH 6
819#define MTL_Q_RQFCR_RFD_INDEX 17
820#define MTL_Q_RQFCR_RFD_WIDTH 6
821#define MTL_Q_RQOMR_EHFC_INDEX 7
822#define MTL_Q_RQOMR_EHFC_WIDTH 1
823#define MTL_Q_RQOMR_RQS_INDEX 16
824#define MTL_Q_RQOMR_RQS_WIDTH 9
825#define MTL_Q_RQOMR_RSF_INDEX 5
826#define MTL_Q_RQOMR_RSF_WIDTH 1
827#define MTL_Q_RQOMR_RTC_INDEX 0
828#define MTL_Q_RQOMR_RTC_WIDTH 2
829#define MTL_Q_TQDR_TRCSTS_INDEX 1
830#define MTL_Q_TQDR_TRCSTS_WIDTH 2
831#define MTL_Q_TQDR_TXQSTS_INDEX 4
832#define MTL_Q_TQDR_TXQSTS_WIDTH 1
833#define MTL_Q_TQOMR_FTQ_INDEX 0
834#define MTL_Q_TQOMR_FTQ_WIDTH 1
835#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
836#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
837#define MTL_Q_TQOMR_TQS_INDEX 16
838#define MTL_Q_TQOMR_TQS_WIDTH 10
839#define MTL_Q_TQOMR_TSF_INDEX 1
840#define MTL_Q_TQOMR_TSF_WIDTH 1
841#define MTL_Q_TQOMR_TTC_INDEX 4
842#define MTL_Q_TQOMR_TTC_WIDTH 3
843#define MTL_Q_TQOMR_TXQEN_INDEX 2
844#define MTL_Q_TQOMR_TXQEN_WIDTH 2
845
846
847#define MTL_RSF_DISABLE 0x00
848#define MTL_RSF_ENABLE 0x01
849#define MTL_TSF_DISABLE 0x00
850#define MTL_TSF_ENABLE 0x01
851
852#define MTL_RX_THRESHOLD_64 0x00
853#define MTL_RX_THRESHOLD_96 0x02
854#define MTL_RX_THRESHOLD_128 0x03
855#define MTL_TX_THRESHOLD_32 0x01
856#define MTL_TX_THRESHOLD_64 0x00
857#define MTL_TX_THRESHOLD_96 0x02
858#define MTL_TX_THRESHOLD_128 0x03
859#define MTL_TX_THRESHOLD_192 0x04
860#define MTL_TX_THRESHOLD_256 0x05
861#define MTL_TX_THRESHOLD_384 0x06
862#define MTL_TX_THRESHOLD_512 0x07
863
864#define MTL_ETSALG_WRR 0x00
865#define MTL_ETSALG_WFQ 0x01
866#define MTL_ETSALG_DWRR 0x02
867#define MTL_RAA_SP 0x00
868#define MTL_RAA_WSP 0x01
869
870#define MTL_Q_DISABLED 0x00
871#define MTL_Q_ENABLED 0x02
872
873
874
875
876
877
878#define MTL_TC_BASE MTL_Q_BASE
879#define MTL_TC_INC MTL_Q_INC
880
881#define MTL_TC_ETSCR 0x10
882#define MTL_TC_ETSSR 0x14
883#define MTL_TC_QWR 0x18
884
885
886#define MTL_TC_ETSCR_TSA_INDEX 0
887#define MTL_TC_ETSCR_TSA_WIDTH 2
888#define MTL_TC_QWR_QW_INDEX 0
889#define MTL_TC_QWR_QW_WIDTH 21
890
891
892#define MTL_TSA_SP 0x00
893#define MTL_TSA_ETS 0x02
894
895
896#define PCS_V1_WINDOW_SELECT 0x03fc
897#define PCS_V2_WINDOW_DEF 0x9060
898#define PCS_V2_WINDOW_SELECT 0x9064
899#define PCS_V2_RV_WINDOW_DEF 0x1060
900#define PCS_V2_RV_WINDOW_SELECT 0x1064
901
902
903#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
904#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
905#define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
906#define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
907
908
909#define SIR0_KR_RT_1 0x002c
910#define SIR0_STATUS 0x0040
911#define SIR1_SPEED 0x0000
912
913
914#define SIR0_KR_RT_1_RESET_INDEX 11
915#define SIR0_KR_RT_1_RESET_WIDTH 1
916#define SIR0_STATUS_RX_READY_INDEX 0
917#define SIR0_STATUS_RX_READY_WIDTH 1
918#define SIR0_STATUS_TX_READY_INDEX 8
919#define SIR0_STATUS_TX_READY_WIDTH 1
920#define SIR1_SPEED_CDR_RATE_INDEX 12
921#define SIR1_SPEED_CDR_RATE_WIDTH 4
922#define SIR1_SPEED_DATARATE_INDEX 4
923#define SIR1_SPEED_DATARATE_WIDTH 2
924#define SIR1_SPEED_PLLSEL_INDEX 3
925#define SIR1_SPEED_PLLSEL_WIDTH 1
926#define SIR1_SPEED_RATECHANGE_INDEX 6
927#define SIR1_SPEED_RATECHANGE_WIDTH 1
928#define SIR1_SPEED_TXAMP_INDEX 8
929#define SIR1_SPEED_TXAMP_WIDTH 4
930#define SIR1_SPEED_WORDMODE_INDEX 0
931#define SIR1_SPEED_WORDMODE_WIDTH 3
932
933
934#define RXTX_REG6 0x0018
935#define RXTX_REG20 0x0050
936#define RXTX_REG22 0x0058
937#define RXTX_REG114 0x01c8
938#define RXTX_REG129 0x0204
939
940
941#define RXTX_REG6_RESETB_RXD_INDEX 8
942#define RXTX_REG6_RESETB_RXD_WIDTH 1
943#define RXTX_REG20_BLWC_ENA_INDEX 2
944#define RXTX_REG20_BLWC_ENA_WIDTH 1
945#define RXTX_REG114_PQ_REG_INDEX 9
946#define RXTX_REG114_PQ_REG_WIDTH 7
947#define RXTX_REG129_RXDFE_CONFIG_INDEX 14
948#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
949
950
951#define XP_PROP_0 0x0000
952#define XP_PROP_1 0x0004
953#define XP_PROP_2 0x0008
954#define XP_PROP_3 0x000c
955#define XP_PROP_4 0x0010
956#define XP_PROP_5 0x0014
957#define XP_MAC_ADDR_LO 0x0020
958#define XP_MAC_ADDR_HI 0x0024
959#define XP_ECC_ISR 0x0030
960#define XP_ECC_IER 0x0034
961#define XP_ECC_CNT0 0x003c
962#define XP_ECC_CNT1 0x0040
963#define XP_DRIVER_INT_REQ 0x0060
964#define XP_DRIVER_INT_RO 0x0064
965#define XP_DRIVER_SCRATCH_0 0x0068
966#define XP_DRIVER_SCRATCH_1 0x006c
967#define XP_INT_REISSUE_EN 0x0074
968#define XP_INT_EN 0x0078
969#define XP_I2C_MUTEX 0x0080
970#define XP_MDIO_MUTEX 0x0084
971
972
973#define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
974#define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
975#define XP_DRIVER_INT_RO_STATUS_INDEX 0
976#define XP_DRIVER_INT_RO_STATUS_WIDTH 1
977#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
978#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
979#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
980#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
981#define XP_ECC_CNT0_RX_DED_INDEX 24
982#define XP_ECC_CNT0_RX_DED_WIDTH 8
983#define XP_ECC_CNT0_RX_SEC_INDEX 16
984#define XP_ECC_CNT0_RX_SEC_WIDTH 8
985#define XP_ECC_CNT0_TX_DED_INDEX 8
986#define XP_ECC_CNT0_TX_DED_WIDTH 8
987#define XP_ECC_CNT0_TX_SEC_INDEX 0
988#define XP_ECC_CNT0_TX_SEC_WIDTH 8
989#define XP_ECC_CNT1_DESC_DED_INDEX 8
990#define XP_ECC_CNT1_DESC_DED_WIDTH 8
991#define XP_ECC_CNT1_DESC_SEC_INDEX 0
992#define XP_ECC_CNT1_DESC_SEC_WIDTH 8
993#define XP_ECC_IER_DESC_DED_INDEX 5
994#define XP_ECC_IER_DESC_DED_WIDTH 1
995#define XP_ECC_IER_DESC_SEC_INDEX 4
996#define XP_ECC_IER_DESC_SEC_WIDTH 1
997#define XP_ECC_IER_RX_DED_INDEX 3
998#define XP_ECC_IER_RX_DED_WIDTH 1
999#define XP_ECC_IER_RX_SEC_INDEX 2
1000#define XP_ECC_IER_RX_SEC_WIDTH 1
1001#define XP_ECC_IER_TX_DED_INDEX 1
1002#define XP_ECC_IER_TX_DED_WIDTH 1
1003#define XP_ECC_IER_TX_SEC_INDEX 0
1004#define XP_ECC_IER_TX_SEC_WIDTH 1
1005#define XP_ECC_ISR_DESC_DED_INDEX 5
1006#define XP_ECC_ISR_DESC_DED_WIDTH 1
1007#define XP_ECC_ISR_DESC_SEC_INDEX 4
1008#define XP_ECC_ISR_DESC_SEC_WIDTH 1
1009#define XP_ECC_ISR_RX_DED_INDEX 3
1010#define XP_ECC_ISR_RX_DED_WIDTH 1
1011#define XP_ECC_ISR_RX_SEC_INDEX 2
1012#define XP_ECC_ISR_RX_SEC_WIDTH 1
1013#define XP_ECC_ISR_TX_DED_INDEX 1
1014#define XP_ECC_ISR_TX_DED_WIDTH 1
1015#define XP_ECC_ISR_TX_SEC_INDEX 0
1016#define XP_ECC_ISR_TX_SEC_WIDTH 1
1017#define XP_I2C_MUTEX_BUSY_INDEX 31
1018#define XP_I2C_MUTEX_BUSY_WIDTH 1
1019#define XP_I2C_MUTEX_ID_INDEX 29
1020#define XP_I2C_MUTEX_ID_WIDTH 2
1021#define XP_I2C_MUTEX_ACTIVE_INDEX 0
1022#define XP_I2C_MUTEX_ACTIVE_WIDTH 1
1023#define XP_MAC_ADDR_HI_VALID_INDEX 31
1024#define XP_MAC_ADDR_HI_VALID_WIDTH 1
1025#define XP_PROP_0_CONN_TYPE_INDEX 28
1026#define XP_PROP_0_CONN_TYPE_WIDTH 3
1027#define XP_PROP_0_MDIO_ADDR_INDEX 16
1028#define XP_PROP_0_MDIO_ADDR_WIDTH 5
1029#define XP_PROP_0_PORT_ID_INDEX 0
1030#define XP_PROP_0_PORT_ID_WIDTH 8
1031#define XP_PROP_0_PORT_MODE_INDEX 8
1032#define XP_PROP_0_PORT_MODE_WIDTH 4
1033#define XP_PROP_0_PORT_SPEEDS_INDEX 23
1034#define XP_PROP_0_PORT_SPEEDS_WIDTH 4
1035#define XP_PROP_1_MAX_RX_DMA_INDEX 24
1036#define XP_PROP_1_MAX_RX_DMA_WIDTH 5
1037#define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
1038#define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
1039#define XP_PROP_1_MAX_TX_DMA_INDEX 16
1040#define XP_PROP_1_MAX_TX_DMA_WIDTH 5
1041#define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1042#define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
1043#define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
1044#define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
1045#define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1046#define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
1047#define XP_PROP_3_GPIO_MASK_INDEX 28
1048#define XP_PROP_3_GPIO_MASK_WIDTH 4
1049#define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
1050#define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
1051#define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
1052#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
1053#define XP_PROP_3_GPIO_RX_LOS_INDEX 24
1054#define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
1055#define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
1056#define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1057#define XP_PROP_3_GPIO_ADDR_INDEX 8
1058#define XP_PROP_3_GPIO_ADDR_WIDTH 3
1059#define XP_PROP_3_MDIO_RESET_INDEX 0
1060#define XP_PROP_3_MDIO_RESET_WIDTH 2
1061#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1062#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1063#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1064#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1065#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1066#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1067#define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1068#define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1069#define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1070#define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1071#define XP_PROP_4_MUX_CHAN_INDEX 4
1072#define XP_PROP_4_MUX_CHAN_WIDTH 3
1073#define XP_PROP_4_REDRV_ADDR_INDEX 16
1074#define XP_PROP_4_REDRV_ADDR_WIDTH 7
1075#define XP_PROP_4_REDRV_IF_INDEX 23
1076#define XP_PROP_4_REDRV_IF_WIDTH 1
1077#define XP_PROP_4_REDRV_LANE_INDEX 24
1078#define XP_PROP_4_REDRV_LANE_WIDTH 3
1079#define XP_PROP_4_REDRV_MODEL_INDEX 28
1080#define XP_PROP_4_REDRV_MODEL_WIDTH 3
1081#define XP_PROP_4_REDRV_PRESENT_INDEX 31
1082#define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1083
1084
1085#define IC_CON 0x0000
1086#define IC_TAR 0x0004
1087#define IC_DATA_CMD 0x0010
1088#define IC_INTR_STAT 0x002c
1089#define IC_INTR_MASK 0x0030
1090#define IC_RAW_INTR_STAT 0x0034
1091#define IC_CLR_INTR 0x0040
1092#define IC_CLR_TX_ABRT 0x0054
1093#define IC_CLR_STOP_DET 0x0060
1094#define IC_ENABLE 0x006c
1095#define IC_TXFLR 0x0074
1096#define IC_RXFLR 0x0078
1097#define IC_TX_ABRT_SOURCE 0x0080
1098#define IC_ENABLE_STATUS 0x009c
1099#define IC_COMP_PARAM_1 0x00f4
1100
1101
1102#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1103#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1104#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1105#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1106#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1107#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1108#define IC_CON_MASTER_MODE_INDEX 0
1109#define IC_CON_MASTER_MODE_WIDTH 1
1110#define IC_CON_RESTART_EN_INDEX 5
1111#define IC_CON_RESTART_EN_WIDTH 1
1112#define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1113#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1114#define IC_CON_SLAVE_DISABLE_INDEX 6
1115#define IC_CON_SLAVE_DISABLE_WIDTH 1
1116#define IC_CON_SPEED_INDEX 1
1117#define IC_CON_SPEED_WIDTH 2
1118#define IC_DATA_CMD_CMD_INDEX 8
1119#define IC_DATA_CMD_CMD_WIDTH 1
1120#define IC_DATA_CMD_STOP_INDEX 9
1121#define IC_DATA_CMD_STOP_WIDTH 1
1122#define IC_ENABLE_ABORT_INDEX 1
1123#define IC_ENABLE_ABORT_WIDTH 1
1124#define IC_ENABLE_EN_INDEX 0
1125#define IC_ENABLE_EN_WIDTH 1
1126#define IC_ENABLE_STATUS_EN_INDEX 0
1127#define IC_ENABLE_STATUS_EN_WIDTH 1
1128#define IC_INTR_MASK_TX_EMPTY_INDEX 4
1129#define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1130#define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1131#define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1132#define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1133#define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1134#define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1135#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1136#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1137#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1138
1139
1140#define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1141#define IC_TX_ABRT_ARB_LOST 0x1000
1142
1143
1144#define RX_PACKET_ERRORS_CRC_INDEX 2
1145#define RX_PACKET_ERRORS_CRC_WIDTH 1
1146#define RX_PACKET_ERRORS_FRAME_INDEX 3
1147#define RX_PACKET_ERRORS_FRAME_WIDTH 1
1148#define RX_PACKET_ERRORS_LENGTH_INDEX 0
1149#define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1150#define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1151#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1152
1153#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1154#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1155#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1156#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1157#define RX_PACKET_ATTRIBUTES_LAST_INDEX 2
1158#define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1
1159#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1160#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1161#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1162#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1163#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1164#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1165#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1166#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1167#define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7
1168#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1
1169#define RX_PACKET_ATTRIBUTES_TNP_INDEX 8
1170#define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1
1171#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9
1172#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1
1173
1174#define RX_NORMAL_DESC0_OVT_INDEX 0
1175#define RX_NORMAL_DESC0_OVT_WIDTH 16
1176#define RX_NORMAL_DESC2_HL_INDEX 0
1177#define RX_NORMAL_DESC2_HL_WIDTH 10
1178#define RX_NORMAL_DESC2_TNP_INDEX 11
1179#define RX_NORMAL_DESC2_TNP_WIDTH 1
1180#define RX_NORMAL_DESC3_CDA_INDEX 27
1181#define RX_NORMAL_DESC3_CDA_WIDTH 1
1182#define RX_NORMAL_DESC3_CTXT_INDEX 30
1183#define RX_NORMAL_DESC3_CTXT_WIDTH 1
1184#define RX_NORMAL_DESC3_ES_INDEX 15
1185#define RX_NORMAL_DESC3_ES_WIDTH 1
1186#define RX_NORMAL_DESC3_ETLT_INDEX 16
1187#define RX_NORMAL_DESC3_ETLT_WIDTH 4
1188#define RX_NORMAL_DESC3_FD_INDEX 29
1189#define RX_NORMAL_DESC3_FD_WIDTH 1
1190#define RX_NORMAL_DESC3_INTE_INDEX 30
1191#define RX_NORMAL_DESC3_INTE_WIDTH 1
1192#define RX_NORMAL_DESC3_L34T_INDEX 20
1193#define RX_NORMAL_DESC3_L34T_WIDTH 4
1194#define RX_NORMAL_DESC3_LD_INDEX 28
1195#define RX_NORMAL_DESC3_LD_WIDTH 1
1196#define RX_NORMAL_DESC3_OWN_INDEX 31
1197#define RX_NORMAL_DESC3_OWN_WIDTH 1
1198#define RX_NORMAL_DESC3_PL_INDEX 0
1199#define RX_NORMAL_DESC3_PL_WIDTH 14
1200#define RX_NORMAL_DESC3_RSV_INDEX 26
1201#define RX_NORMAL_DESC3_RSV_WIDTH 1
1202
1203#define RX_DESC3_L34T_IPV4_TCP 1
1204#define RX_DESC3_L34T_IPV4_UDP 2
1205#define RX_DESC3_L34T_IPV4_ICMP 3
1206#define RX_DESC3_L34T_IPV4_UNKNOWN 7
1207#define RX_DESC3_L34T_IPV6_TCP 9
1208#define RX_DESC3_L34T_IPV6_UDP 10
1209#define RX_DESC3_L34T_IPV6_ICMP 11
1210#define RX_DESC3_L34T_IPV6_UNKNOWN 15
1211
1212#define RX_CONTEXT_DESC3_TSA_INDEX 4
1213#define RX_CONTEXT_DESC3_TSA_WIDTH 1
1214#define RX_CONTEXT_DESC3_TSD_INDEX 6
1215#define RX_CONTEXT_DESC3_TSD_WIDTH 1
1216
1217#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1218#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1219#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1220#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1221#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1222#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1223#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1224#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1225#define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4
1226#define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1
1227
1228#define TX_CONTEXT_DESC2_MSS_INDEX 0
1229#define TX_CONTEXT_DESC2_MSS_WIDTH 15
1230#define TX_CONTEXT_DESC3_CTXT_INDEX 30
1231#define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1232#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1233#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1234#define TX_CONTEXT_DESC3_VLTV_INDEX 16
1235#define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1236#define TX_CONTEXT_DESC3_VT_INDEX 0
1237#define TX_CONTEXT_DESC3_VT_WIDTH 16
1238
1239#define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1240#define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1241#define TX_NORMAL_DESC2_IC_INDEX 31
1242#define TX_NORMAL_DESC2_IC_WIDTH 1
1243#define TX_NORMAL_DESC2_TTSE_INDEX 30
1244#define TX_NORMAL_DESC2_TTSE_WIDTH 1
1245#define TX_NORMAL_DESC2_VTIR_INDEX 14
1246#define TX_NORMAL_DESC2_VTIR_WIDTH 2
1247#define TX_NORMAL_DESC3_CIC_INDEX 16
1248#define TX_NORMAL_DESC3_CIC_WIDTH 2
1249#define TX_NORMAL_DESC3_CPC_INDEX 26
1250#define TX_NORMAL_DESC3_CPC_WIDTH 2
1251#define TX_NORMAL_DESC3_CTXT_INDEX 30
1252#define TX_NORMAL_DESC3_CTXT_WIDTH 1
1253#define TX_NORMAL_DESC3_FD_INDEX 29
1254#define TX_NORMAL_DESC3_FD_WIDTH 1
1255#define TX_NORMAL_DESC3_FL_INDEX 0
1256#define TX_NORMAL_DESC3_FL_WIDTH 15
1257#define TX_NORMAL_DESC3_LD_INDEX 28
1258#define TX_NORMAL_DESC3_LD_WIDTH 1
1259#define TX_NORMAL_DESC3_OWN_INDEX 31
1260#define TX_NORMAL_DESC3_OWN_WIDTH 1
1261#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1262#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1263#define TX_NORMAL_DESC3_TCPPL_INDEX 0
1264#define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1265#define TX_NORMAL_DESC3_TSE_INDEX 18
1266#define TX_NORMAL_DESC3_TSE_WIDTH 1
1267#define TX_NORMAL_DESC3_VNP_INDEX 23
1268#define TX_NORMAL_DESC3_VNP_WIDTH 3
1269
1270#define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1271#define TX_NORMAL_DESC3_VXLAN_PACKET 0x3
1272
1273
1274#ifndef MDIO_PMA_10GBR_PMD_CTRL
1275#define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1276#endif
1277
1278#ifndef MDIO_PMA_10GBR_FECCTRL
1279#define MDIO_PMA_10GBR_FECCTRL 0x00ab
1280#endif
1281
1282#ifndef MDIO_PCS_DIG_CTRL
1283#define MDIO_PCS_DIG_CTRL 0x8000
1284#endif
1285
1286#ifndef MDIO_AN_XNP
1287#define MDIO_AN_XNP 0x0016
1288#endif
1289
1290#ifndef MDIO_AN_LPX
1291#define MDIO_AN_LPX 0x0019
1292#endif
1293
1294#ifndef MDIO_AN_COMP_STAT
1295#define MDIO_AN_COMP_STAT 0x0030
1296#endif
1297
1298#ifndef MDIO_AN_INTMASK
1299#define MDIO_AN_INTMASK 0x8001
1300#endif
1301
1302#ifndef MDIO_AN_INT
1303#define MDIO_AN_INT 0x8002
1304#endif
1305
1306#ifndef MDIO_VEND2_AN_ADVERTISE
1307#define MDIO_VEND2_AN_ADVERTISE 0x0004
1308#endif
1309
1310#ifndef MDIO_VEND2_AN_LP_ABILITY
1311#define MDIO_VEND2_AN_LP_ABILITY 0x0005
1312#endif
1313
1314#ifndef MDIO_VEND2_AN_CTRL
1315#define MDIO_VEND2_AN_CTRL 0x8001
1316#endif
1317
1318#ifndef MDIO_VEND2_AN_STAT
1319#define MDIO_VEND2_AN_STAT 0x8002
1320#endif
1321
1322#ifndef MDIO_VEND2_PMA_CDR_CONTROL
1323#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1324#endif
1325
1326#ifndef MDIO_CTRL1_SPEED1G
1327#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1328#endif
1329
1330#ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1331#define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1332#endif
1333
1334#ifndef MDIO_VEND2_CTRL1_AN_RESTART
1335#define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1336#endif
1337
1338#ifndef MDIO_VEND2_CTRL1_SS6
1339#define MDIO_VEND2_CTRL1_SS6 BIT(6)
1340#endif
1341
1342#ifndef MDIO_VEND2_CTRL1_SS13
1343#define MDIO_VEND2_CTRL1_SS13 BIT(13)
1344#endif
1345
1346
1347#define XGBE_AN_CL73_INT_CMPLT BIT(0)
1348#define XGBE_AN_CL73_INC_LINK BIT(1)
1349#define XGBE_AN_CL73_PG_RCV BIT(2)
1350#define XGBE_AN_CL73_INT_MASK 0x07
1351
1352#define XGBE_XNP_MCF_NULL_MESSAGE 0x001
1353#define XGBE_XNP_ACK_PROCESSED BIT(12)
1354#define XGBE_XNP_MP_FORMATTED BIT(13)
1355#define XGBE_XNP_NP_EXCHANGE BIT(15)
1356
1357#define XGBE_KR_TRAINING_START BIT(0)
1358#define XGBE_KR_TRAINING_ENABLE BIT(1)
1359
1360#define XGBE_PCS_CL37_BP BIT(12)
1361
1362#define XGBE_AN_CL37_INT_CMPLT BIT(0)
1363#define XGBE_AN_CL37_INT_MASK 0x01
1364
1365#define XGBE_AN_CL37_HD_MASK 0x40
1366#define XGBE_AN_CL37_FD_MASK 0x20
1367
1368#define XGBE_AN_CL37_PCS_MODE_MASK 0x06
1369#define XGBE_AN_CL37_PCS_MODE_BASEX 0x00
1370#define XGBE_AN_CL37_PCS_MODE_SGMII 0x04
1371#define XGBE_AN_CL37_TX_CONFIG_MASK 0x08
1372#define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1373
1374#define XGBE_PMA_CDR_TRACK_EN_MASK 0x01
1375#define XGBE_PMA_CDR_TRACK_EN_OFF 0x00
1376#define XGBE_PMA_CDR_TRACK_EN_ON 0x01
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386#define GET_BITS(_var, _index, _width) \
1387 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1388
1389#define SET_BITS(_var, _index, _width, _val) \
1390do { \
1391 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1392 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1393} while (0)
1394
1395#define GET_BITS_LE(_var, _index, _width) \
1396 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1397
1398#define SET_BITS_LE(_var, _index, _width, _val) \
1399do { \
1400 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1401 (_var) |= cpu_to_le32((((_val) & \
1402 ((0x1 << (_width)) - 1)) << (_index))); \
1403} while (0)
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413#define XGMAC_GET_BITS(_var, _prefix, _field) \
1414 GET_BITS((_var), \
1415 _prefix##_##_field##_INDEX, \
1416 _prefix##_##_field##_WIDTH)
1417
1418#define XGMAC_SET_BITS(_var, _prefix, _field, _val) \
1419 SET_BITS((_var), \
1420 _prefix##_##_field##_INDEX, \
1421 _prefix##_##_field##_WIDTH, (_val))
1422
1423#define XGMAC_GET_BITS_LE(_var, _prefix, _field) \
1424 GET_BITS_LE((_var), \
1425 _prefix##_##_field##_INDEX, \
1426 _prefix##_##_field##_WIDTH)
1427
1428#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1429 SET_BITS_LE((_var), \
1430 _prefix##_##_field##_INDEX, \
1431 _prefix##_##_field##_WIDTH, (_val))
1432
1433
1434
1435
1436
1437
1438
1439
1440#define XGMAC_IOREAD(_pdata, _reg) \
1441 ioread32((_pdata)->xgmac_regs + _reg)
1442
1443#define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1444 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1445 _reg##_##_field##_INDEX, \
1446 _reg##_##_field##_WIDTH)
1447
1448#define XGMAC_IOWRITE(_pdata, _reg, _val) \
1449 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1450
1451#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1452do { \
1453 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
1454 SET_BITS(reg_val, \
1455 _reg##_##_field##_INDEX, \
1456 _reg##_##_field##_WIDTH, (_val)); \
1457 XGMAC_IOWRITE((_pdata), _reg, reg_val); \
1458} while (0)
1459
1460
1461
1462
1463
1464#define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1465 ioread32((_pdata)->xgmac_regs + \
1466 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1467
1468#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1469 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
1470 _reg##_##_field##_INDEX, \
1471 _reg##_##_field##_WIDTH)
1472
1473#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1474 iowrite32((_val), (_pdata)->xgmac_regs + \
1475 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1476
1477#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1478do { \
1479 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1480 SET_BITS(reg_val, \
1481 _reg##_##_field##_INDEX, \
1482 _reg##_##_field##_WIDTH, (_val)); \
1483 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1484} while (0)
1485
1486
1487
1488
1489
1490#define XGMAC_DMA_IOREAD(_channel, _reg) \
1491 ioread32((_channel)->dma_regs + _reg)
1492
1493#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1494 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
1495 _reg##_##_field##_INDEX, \
1496 _reg##_##_field##_WIDTH)
1497
1498#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1499 iowrite32((_val), (_channel)->dma_regs + _reg)
1500
1501#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1502do { \
1503 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
1504 SET_BITS(reg_val, \
1505 _reg##_##_field##_INDEX, \
1506 _reg##_##_field##_WIDTH, (_val)); \
1507 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1508} while (0)
1509
1510
1511
1512
1513#define XPCS_GET_BITS(_var, _prefix, _field) \
1514 GET_BITS((_var), \
1515 _prefix##_##_field##_INDEX, \
1516 _prefix##_##_field##_WIDTH)
1517
1518#define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1519 SET_BITS((_var), \
1520 _prefix##_##_field##_INDEX, \
1521 _prefix##_##_field##_WIDTH, (_val))
1522
1523#define XPCS32_IOWRITE(_pdata, _off, _val) \
1524 iowrite32(_val, (_pdata)->xpcs_regs + (_off))
1525
1526#define XPCS32_IOREAD(_pdata, _off) \
1527 ioread32((_pdata)->xpcs_regs + (_off))
1528
1529#define XPCS16_IOWRITE(_pdata, _off, _val) \
1530 iowrite16(_val, (_pdata)->xpcs_regs + (_off))
1531
1532#define XPCS16_IOREAD(_pdata, _off) \
1533 ioread16((_pdata)->xpcs_regs + (_off))
1534
1535
1536
1537
1538#define XSIR_GET_BITS(_var, _prefix, _field) \
1539 GET_BITS((_var), \
1540 _prefix##_##_field##_INDEX, \
1541 _prefix##_##_field##_WIDTH)
1542
1543#define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1544 SET_BITS((_var), \
1545 _prefix##_##_field##_INDEX, \
1546 _prefix##_##_field##_WIDTH, (_val))
1547
1548#define XSIR0_IOREAD(_pdata, _reg) \
1549 ioread16((_pdata)->sir0_regs + _reg)
1550
1551#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1552 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1553 _reg##_##_field##_INDEX, \
1554 _reg##_##_field##_WIDTH)
1555
1556#define XSIR0_IOWRITE(_pdata, _reg, _val) \
1557 iowrite16((_val), (_pdata)->sir0_regs + _reg)
1558
1559#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1560do { \
1561 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1562 SET_BITS(reg_val, \
1563 _reg##_##_field##_INDEX, \
1564 _reg##_##_field##_WIDTH, (_val)); \
1565 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1566} while (0)
1567
1568#define XSIR1_IOREAD(_pdata, _reg) \
1569 ioread16((_pdata)->sir1_regs + _reg)
1570
1571#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1572 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1573 _reg##_##_field##_INDEX, \
1574 _reg##_##_field##_WIDTH)
1575
1576#define XSIR1_IOWRITE(_pdata, _reg, _val) \
1577 iowrite16((_val), (_pdata)->sir1_regs + _reg)
1578
1579#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1580do { \
1581 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1582 SET_BITS(reg_val, \
1583 _reg##_##_field##_INDEX, \
1584 _reg##_##_field##_WIDTH, (_val)); \
1585 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1586} while (0)
1587
1588
1589
1590
1591#define XRXTX_IOREAD(_pdata, _reg) \
1592 ioread16((_pdata)->rxtx_regs + _reg)
1593
1594#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1595 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1596 _reg##_##_field##_INDEX, \
1597 _reg##_##_field##_WIDTH)
1598
1599#define XRXTX_IOWRITE(_pdata, _reg, _val) \
1600 iowrite16((_val), (_pdata)->rxtx_regs + _reg)
1601
1602#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1603do { \
1604 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1605 SET_BITS(reg_val, \
1606 _reg##_##_field##_INDEX, \
1607 _reg##_##_field##_WIDTH, (_val)); \
1608 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1609} while (0)
1610
1611
1612
1613
1614#define XP_GET_BITS(_var, _prefix, _field) \
1615 GET_BITS((_var), \
1616 _prefix##_##_field##_INDEX, \
1617 _prefix##_##_field##_WIDTH)
1618
1619#define XP_SET_BITS(_var, _prefix, _field, _val) \
1620 SET_BITS((_var), \
1621 _prefix##_##_field##_INDEX, \
1622 _prefix##_##_field##_WIDTH, (_val))
1623
1624#define XP_IOREAD(_pdata, _reg) \
1625 ioread32((_pdata)->xprop_regs + (_reg))
1626
1627#define XP_IOREAD_BITS(_pdata, _reg, _field) \
1628 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1629 _reg##_##_field##_INDEX, \
1630 _reg##_##_field##_WIDTH)
1631
1632#define XP_IOWRITE(_pdata, _reg, _val) \
1633 iowrite32((_val), (_pdata)->xprop_regs + (_reg))
1634
1635#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1636do { \
1637 u32 reg_val = XP_IOREAD((_pdata), (_reg)); \
1638 SET_BITS(reg_val, \
1639 _reg##_##_field##_INDEX, \
1640 _reg##_##_field##_WIDTH, (_val)); \
1641 XP_IOWRITE((_pdata), (_reg), reg_val); \
1642} while (0)
1643
1644
1645
1646
1647#define XI2C_GET_BITS(_var, _prefix, _field) \
1648 GET_BITS((_var), \
1649 _prefix##_##_field##_INDEX, \
1650 _prefix##_##_field##_WIDTH)
1651
1652#define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1653 SET_BITS((_var), \
1654 _prefix##_##_field##_INDEX, \
1655 _prefix##_##_field##_WIDTH, (_val))
1656
1657#define XI2C_IOREAD(_pdata, _reg) \
1658 ioread32((_pdata)->xi2c_regs + (_reg))
1659
1660#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1661 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1662 _reg##_##_field##_INDEX, \
1663 _reg##_##_field##_WIDTH)
1664
1665#define XI2C_IOWRITE(_pdata, _reg, _val) \
1666 iowrite32((_val), (_pdata)->xi2c_regs + (_reg))
1667
1668#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1669do { \
1670 u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1671 SET_BITS(reg_val, \
1672 _reg##_##_field##_INDEX, \
1673 _reg##_##_field##_WIDTH, (_val)); \
1674 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1675} while (0)
1676
1677
1678
1679
1680
1681
1682#define XMDIO_READ(_pdata, _mmd, _reg) \
1683 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1684 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1685
1686#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1687 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1688
1689#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1690 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1691 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1692
1693#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1694do { \
1695 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
1696 mmd_val &= ~_mask; \
1697 mmd_val |= (_val); \
1698 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \
1699} while (0)
1700
1701#endif
1702