1/* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13#ifndef _BNXT_HSI_H_ 14#define _BNXT_HSI_H_ 15 16/* hwrm_cmd_hdr (size:128b/16B) */ 17struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23}; 24 25/* hwrm_resp_hdr (size:64b/8B) */ 26struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31}; 32 33#define CMD_DISCR_TLV_ENCAP 0x8000UL 34#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37#define TLV_TYPE_HWRM_REQUEST 0x1UL 38#define TLV_TYPE_HWRM_RESPONSE 0x2UL 39#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 41#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 42#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 43#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 44#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 48#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 49#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 51 52 53/* tlv (size:64b/8B) */ 54struct tlv { 55 __le16 cmd_discr; 56 u8 reserved_8b; 57 u8 flags; 58 #define TLV_FLAGS_MORE 0x1UL 59 #define TLV_FLAGS_MORE_LAST 0x0UL 60 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 61 #define TLV_FLAGS_REQUIRED 0x2UL 62 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 63 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 64 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 65 __le16 tlv_type; 66 __le16 length; 67}; 68 69/* input (size:128b/16B) */ 70struct input { 71 __le16 req_type; 72 __le16 cmpl_ring; 73 __le16 seq_id; 74 __le16 target_id; 75 __le64 resp_addr; 76}; 77 78/* output (size:64b/8B) */ 79struct output { 80 __le16 error_code; 81 __le16 req_type; 82 __le16 seq_id; 83 __le16 resp_len; 84}; 85 86/* hwrm_short_input (size:128b/16B) */ 87struct hwrm_short_input { 88 __le16 req_type; 89 __le16 signature; 90 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 91 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 92 __le16 unused_0; 93 __le16 size; 94 __le64 req_addr; 95}; 96 97/* cmd_nums (size:64b/8B) */ 98struct cmd_nums { 99 __le16 req_type; 100 #define HWRM_VER_GET 0x0UL 101 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 102 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 103 #define HWRM_FUNC_VF_CFG 0xfUL 104 #define HWRM_RESERVED1 0x10UL 105 #define HWRM_FUNC_RESET 0x11UL 106 #define HWRM_FUNC_GETFID 0x12UL 107 #define HWRM_FUNC_VF_ALLOC 0x13UL 108 #define HWRM_FUNC_VF_FREE 0x14UL 109 #define HWRM_FUNC_QCAPS 0x15UL 110 #define HWRM_FUNC_QCFG 0x16UL 111 #define HWRM_FUNC_CFG 0x17UL 112 #define HWRM_FUNC_QSTATS 0x18UL 113 #define HWRM_FUNC_CLR_STATS 0x19UL 114 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 115 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 116 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 117 #define HWRM_FUNC_DRV_RGTR 0x1dUL 118 #define HWRM_FUNC_DRV_QVER 0x1eUL 119 #define HWRM_FUNC_BUF_RGTR 0x1fUL 120 #define HWRM_PORT_PHY_CFG 0x20UL 121 #define HWRM_PORT_MAC_CFG 0x21UL 122 #define HWRM_PORT_TS_QUERY 0x22UL 123 #define HWRM_PORT_QSTATS 0x23UL 124 #define HWRM_PORT_LPBK_QSTATS 0x24UL 125 #define HWRM_PORT_CLR_STATS 0x25UL 126 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 127 #define HWRM_PORT_PHY_QCFG 0x27UL 128 #define HWRM_PORT_MAC_QCFG 0x28UL 129 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 130 #define HWRM_PORT_PHY_QCAPS 0x2aUL 131 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 132 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 133 #define HWRM_PORT_LED_CFG 0x2dUL 134 #define HWRM_PORT_LED_QCFG 0x2eUL 135 #define HWRM_PORT_LED_QCAPS 0x2fUL 136 #define HWRM_QUEUE_QPORTCFG 0x30UL 137 #define HWRM_QUEUE_QCFG 0x31UL 138 #define HWRM_QUEUE_CFG 0x32UL 139 #define HWRM_FUNC_VLAN_CFG 0x33UL 140 #define HWRM_FUNC_VLAN_QCFG 0x34UL 141 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 142 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 143 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 144 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 145 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 146 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 147 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 148 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 149 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 150 #define HWRM_VNIC_ALLOC 0x40UL 151 #define HWRM_VNIC_FREE 0x41UL 152 #define HWRM_VNIC_CFG 0x42UL 153 #define HWRM_VNIC_QCFG 0x43UL 154 #define HWRM_VNIC_TPA_CFG 0x44UL 155 #define HWRM_VNIC_TPA_QCFG 0x45UL 156 #define HWRM_VNIC_RSS_CFG 0x46UL 157 #define HWRM_VNIC_RSS_QCFG 0x47UL 158 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 159 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 160 #define HWRM_VNIC_QCAPS 0x4aUL 161 #define HWRM_RING_ALLOC 0x50UL 162 #define HWRM_RING_FREE 0x51UL 163 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 164 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 165 #define HWRM_RING_AGGINT_QCAPS 0x54UL 166 #define HWRM_RING_RESET 0x5eUL 167 #define HWRM_RING_GRP_ALLOC 0x60UL 168 #define HWRM_RING_GRP_FREE 0x61UL 169 #define HWRM_RESERVED5 0x64UL 170 #define HWRM_RESERVED6 0x65UL 171 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 172 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 173 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 174 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 175 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 176 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 177 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 178 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 179 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 180 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 181 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 183 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 184 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 185 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 186 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 187 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 188 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 189 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 190 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 191 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 192 #define HWRM_STAT_CTX_ALLOC 0xb0UL 193 #define HWRM_STAT_CTX_FREE 0xb1UL 194 #define HWRM_STAT_CTX_QUERY 0xb2UL 195 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 196 #define HWRM_PORT_QSTATS_EXT 0xb4UL 197 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 198 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 199 #define HWRM_FW_RESET 0xc0UL 200 #define HWRM_FW_QSTATUS 0xc1UL 201 #define HWRM_FW_HEALTH_CHECK 0xc2UL 202 #define HWRM_FW_SYNC 0xc3UL 203 #define HWRM_FW_SET_TIME 0xc8UL 204 #define HWRM_FW_GET_TIME 0xc9UL 205 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 206 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 207 #define HWRM_FW_IPC_MAILBOX 0xccUL 208 #define HWRM_EXEC_FWD_RESP 0xd0UL 209 #define HWRM_REJECT_FWD_RESP 0xd1UL 210 #define HWRM_FWD_RESP 0xd2UL 211 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 212 #define HWRM_OEM_CMD 0xd4UL 213 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 214 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 215 #define HWRM_WOL_FILTER_FREE 0xf1UL 216 #define HWRM_WOL_FILTER_QCFG 0xf2UL 217 #define HWRM_WOL_REASON_QCFG 0xf3UL 218 #define HWRM_CFA_METER_QCAPS 0xf4UL 219 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 220 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 221 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 222 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 223 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 224 #define HWRM_CFA_VFR_ALLOC 0xfdUL 225 #define HWRM_CFA_VFR_FREE 0xfeUL 226 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 227 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 228 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 229 #define HWRM_CFA_FLOW_ALLOC 0x103UL 230 #define HWRM_CFA_FLOW_FREE 0x104UL 231 #define HWRM_CFA_FLOW_FLUSH 0x105UL 232 #define HWRM_CFA_FLOW_STATS 0x106UL 233 #define HWRM_CFA_FLOW_INFO 0x107UL 234 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 235 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 236 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 237 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 238 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 239 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 240 #define HWRM_CFA_PAIR_FREE 0x10eUL 241 #define HWRM_CFA_PAIR_INFO 0x10fUL 242 #define HWRM_FW_IPC_MSG 0x110UL 243 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 244 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 245 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 246 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 247 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 248 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 249 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 250 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 251 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 252 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 253 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 254 #define HWRM_CFA_COUNTER_CFG 0x11cUL 255 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 256 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 257 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 258 #define HWRM_CFA_EEM_QCAPS 0x120UL 259 #define HWRM_CFA_EEM_CFG 0x121UL 260 #define HWRM_CFA_EEM_QCFG 0x122UL 261 #define HWRM_CFA_EEM_OP 0x123UL 262 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 263 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 264 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 265 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 266 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 267 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 268 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 269 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 270 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 271 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 272 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 273 #define HWRM_ENGINE_QG_QUERY 0x13dUL 274 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 275 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 276 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 277 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 278 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 279 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 280 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 281 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 282 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 283 #define HWRM_ENGINE_SG_QUERY 0x147UL 284 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 285 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 286 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 287 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 288 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 289 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 290 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 291 #define HWRM_ENGINE_STATS_QUERY 0x157UL 292 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 293 #define HWRM_ENGINE_RQ_FREE 0x15fUL 294 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 295 #define HWRM_ENGINE_CQ_FREE 0x161UL 296 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 297 #define HWRM_ENGINE_NQ_FREE 0x163UL 298 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 299 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 300 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 301 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 302 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 303 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 304 #define HWRM_FUNC_VF_BW_CFG 0x195UL 305 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 306 #define HWRM_SELFTEST_QLIST 0x200UL 307 #define HWRM_SELFTEST_EXEC 0x201UL 308 #define HWRM_SELFTEST_IRQ 0x202UL 309 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 310 #define HWRM_PCIE_QSTATS 0x204UL 311 #define HWRM_DBG_READ_DIRECT 0xff10UL 312 #define HWRM_DBG_READ_INDIRECT 0xff11UL 313 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 314 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 315 #define HWRM_DBG_DUMP 0xff14UL 316 #define HWRM_DBG_ERASE_NVM 0xff15UL 317 #define HWRM_DBG_CFG 0xff16UL 318 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 319 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 320 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 321 #define HWRM_DBG_FW_CLI 0xff1aUL 322 #define HWRM_DBG_I2C_CMD 0xff1bUL 323 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 324 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 325 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 326 #define HWRM_NVM_FLUSH 0xfff0UL 327 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 328 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 329 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 330 #define HWRM_NVM_MODIFY 0xfff4UL 331 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 332 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 333 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 334 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 335 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 336 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 337 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 338 #define HWRM_NVM_RAW_DUMP 0xfffcUL 339 #define HWRM_NVM_READ 0xfffdUL 340 #define HWRM_NVM_WRITE 0xfffeUL 341 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 342 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 343 __le16 unused_0[3]; 344}; 345 346/* ret_codes (size:64b/8B) */ 347struct ret_codes { 348 __le16 error_code; 349 #define HWRM_ERR_CODE_SUCCESS 0x0UL 350 #define HWRM_ERR_CODE_FAIL 0x1UL 351 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 352 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 353 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 354 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 355 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 356 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 357 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 358 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 359 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 360 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 361 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 362 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 363 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 364 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 365 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 366 __le16 unused_0[3]; 367}; 368 369/* hwrm_err_output (size:128b/16B) */ 370struct hwrm_err_output { 371 __le16 error_code; 372 __le16 req_type; 373 __le16 seq_id; 374 __le16 resp_len; 375 __le32 opaque_0; 376 __le16 opaque_1; 377 u8 cmd_err; 378 u8 valid; 379}; 380#define HWRM_NA_SIGNATURE ((__le32)(-1)) 381#define HWRM_MAX_REQ_LEN 128 382#define HWRM_MAX_RESP_LEN 280 383#define HW_HASH_INDEX_SIZE 0x80 384#define HW_HASH_KEY_SIZE 40 385#define HWRM_RESP_VALID_KEY 1 386#define HWRM_VERSION_MAJOR 1 387#define HWRM_VERSION_MINOR 10 388#define HWRM_VERSION_UPDATE 0 389#define HWRM_VERSION_RSVD 35 390#define HWRM_VERSION_STR "1.10.0.35" 391 392/* hwrm_ver_get_input (size:192b/24B) */ 393struct hwrm_ver_get_input { 394 __le16 req_type; 395 __le16 cmpl_ring; 396 __le16 seq_id; 397 __le16 target_id; 398 __le64 resp_addr; 399 u8 hwrm_intf_maj; 400 u8 hwrm_intf_min; 401 u8 hwrm_intf_upd; 402 u8 unused_0[5]; 403}; 404 405/* hwrm_ver_get_output (size:1408b/176B) */ 406struct hwrm_ver_get_output { 407 __le16 error_code; 408 __le16 req_type; 409 __le16 seq_id; 410 __le16 resp_len; 411 u8 hwrm_intf_maj_8b; 412 u8 hwrm_intf_min_8b; 413 u8 hwrm_intf_upd_8b; 414 u8 hwrm_intf_rsvd_8b; 415 u8 hwrm_fw_maj_8b; 416 u8 hwrm_fw_min_8b; 417 u8 hwrm_fw_bld_8b; 418 u8 hwrm_fw_rsvd_8b; 419 u8 mgmt_fw_maj_8b; 420 u8 mgmt_fw_min_8b; 421 u8 mgmt_fw_bld_8b; 422 u8 mgmt_fw_rsvd_8b; 423 u8 netctrl_fw_maj_8b; 424 u8 netctrl_fw_min_8b; 425 u8 netctrl_fw_bld_8b; 426 u8 netctrl_fw_rsvd_8b; 427 __le32 dev_caps_cfg; 428 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 429 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 430 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 431 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 432 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 433 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 434 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 435 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 436 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 437 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 438 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 439 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 440 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 441 u8 roce_fw_maj_8b; 442 u8 roce_fw_min_8b; 443 u8 roce_fw_bld_8b; 444 u8 roce_fw_rsvd_8b; 445 char hwrm_fw_name[16]; 446 char mgmt_fw_name[16]; 447 char netctrl_fw_name[16]; 448 u8 reserved2[16]; 449 char roce_fw_name[16]; 450 __le16 chip_num; 451 u8 chip_rev; 452 u8 chip_metal; 453 u8 chip_bond_id; 454 u8 chip_platform_type; 455 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 456 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 457 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 458 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 459 __le16 max_req_win_len; 460 __le16 max_resp_len; 461 __le16 def_req_timeout; 462 u8 flags; 463 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 464 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 465 u8 unused_0[2]; 466 u8 always_1; 467 __le16 hwrm_intf_major; 468 __le16 hwrm_intf_minor; 469 __le16 hwrm_intf_build; 470 __le16 hwrm_intf_patch; 471 __le16 hwrm_fw_major; 472 __le16 hwrm_fw_minor; 473 __le16 hwrm_fw_build; 474 __le16 hwrm_fw_patch; 475 __le16 mgmt_fw_major; 476 __le16 mgmt_fw_minor; 477 __le16 mgmt_fw_build; 478 __le16 mgmt_fw_patch; 479 __le16 netctrl_fw_major; 480 __le16 netctrl_fw_minor; 481 __le16 netctrl_fw_build; 482 __le16 netctrl_fw_patch; 483 __le16 roce_fw_major; 484 __le16 roce_fw_minor; 485 __le16 roce_fw_build; 486 __le16 roce_fw_patch; 487 __le16 max_ext_req_len; 488 u8 unused_1[5]; 489 u8 valid; 490}; 491 492/* eject_cmpl (size:128b/16B) */ 493struct eject_cmpl { 494 __le16 type; 495 #define EJECT_CMPL_TYPE_MASK 0x3fUL 496 #define EJECT_CMPL_TYPE_SFT 0 497 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 498 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 499 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 500 #define EJECT_CMPL_FLAGS_SFT 6 501 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 502 __le16 len; 503 __le32 opaque; 504 __le16 v; 505 #define EJECT_CMPL_V 0x1UL 506 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 507 #define EJECT_CMPL_ERRORS_SFT 1 508 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 509 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 510 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 511 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 512 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 513 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 514 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 515 __le16 reserved16; 516 __le32 unused_2; 517}; 518 519/* hwrm_cmpl (size:128b/16B) */ 520struct hwrm_cmpl { 521 __le16 type; 522 #define CMPL_TYPE_MASK 0x3fUL 523 #define CMPL_TYPE_SFT 0 524 #define CMPL_TYPE_HWRM_DONE 0x20UL 525 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 526 __le16 sequence_id; 527 __le32 unused_1; 528 __le32 v; 529 #define CMPL_V 0x1UL 530 __le32 unused_3; 531}; 532 533/* hwrm_fwd_req_cmpl (size:128b/16B) */ 534struct hwrm_fwd_req_cmpl { 535 __le16 req_len_type; 536 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 537 #define FWD_REQ_CMPL_TYPE_SFT 0 538 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 539 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 540 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 541 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 542 __le16 source_id; 543 __le32 unused0; 544 __le32 req_buf_addr_v[2]; 545 #define FWD_REQ_CMPL_V 0x1UL 546 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 547 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 548}; 549 550/* hwrm_fwd_resp_cmpl (size:128b/16B) */ 551struct hwrm_fwd_resp_cmpl { 552 __le16 type; 553 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 554 #define FWD_RESP_CMPL_TYPE_SFT 0 555 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 556 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 557 __le16 source_id; 558 __le16 resp_len; 559 __le16 unused_1; 560 __le32 resp_buf_addr_v[2]; 561 #define FWD_RESP_CMPL_V 0x1UL 562 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 563 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 564}; 565 566/* hwrm_async_event_cmpl (size:128b/16B) */ 567struct hwrm_async_event_cmpl { 568 __le16 type; 569 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 570 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 571 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 572 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 573 __le16 event_id; 574 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 575 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 576 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 577 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 578 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 579 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 580 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 581 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 582 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 583 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 584 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 585 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 586 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 587 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 588 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 589 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 590 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 591 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 592 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 593 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 594 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 595 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 596 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 597 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 598 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 599 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 600 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 601 __le32 event_data2; 602 u8 opaque_v; 603 #define ASYNC_EVENT_CMPL_V 0x1UL 604 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 605 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 606 u8 timestamp_lo; 607 __le16 timestamp_hi; 608 __le32 event_data1; 609}; 610 611/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 612struct hwrm_async_event_cmpl_link_status_change { 613 __le16 type; 614 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 615 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 616 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 617 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 618 __le16 event_id; 619 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 620 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 621 __le32 event_data2; 622 u8 opaque_v; 623 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 624 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 625 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 626 u8 timestamp_lo; 627 __le16 timestamp_hi; 628 __le32 event_data1; 629 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 630 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 631 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 632 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 633 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 634 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 635 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 636 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 637 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 638 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 639}; 640 641/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 642struct hwrm_async_event_cmpl_port_conn_not_allowed { 643 __le16 type; 644 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 645 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 646 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 647 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 648 __le16 event_id; 649 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 650 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 651 __le32 event_data2; 652 u8 opaque_v; 653 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 654 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 655 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 656 u8 timestamp_lo; 657 __le16 timestamp_hi; 658 __le32 event_data1; 659 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 660 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 661 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 662 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 663 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 664 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 665 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 666 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 667 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 668}; 669 670/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 671struct hwrm_async_event_cmpl_link_speed_cfg_change { 672 __le16 type; 673 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 674 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 675 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 676 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 677 __le16 event_id; 678 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 679 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 680 __le32 event_data2; 681 u8 opaque_v; 682 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 683 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 684 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 685 u8 timestamp_lo; 686 __le16 timestamp_hi; 687 __le32 event_data1; 688 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 689 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 690 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 691 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 692}; 693 694/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 695struct hwrm_async_event_cmpl_reset_notify { 696 __le16 type; 697 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 698 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 699 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 700 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 701 __le16 event_id; 702 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 703 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 704 __le32 event_data2; 705 u8 opaque_v; 706 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 707 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 708 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 709 u8 timestamp_lo; 710 __le16 timestamp_hi; 711 __le32 event_data1; 712 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 713 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 714 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 715 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 716 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 717 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 718 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 719 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 720 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 721 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 722 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 723 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 724 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 725}; 726 727/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 728struct hwrm_async_event_cmpl_vf_cfg_change { 729 __le16 type; 730 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 731 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 732 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 733 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 734 __le16 event_id; 735 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 736 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 737 __le32 event_data2; 738 u8 opaque_v; 739 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 740 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 741 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 742 u8 timestamp_lo; 743 __le16 timestamp_hi; 744 __le32 event_data1; 745 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 746 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 747 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 748 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 749 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 750}; 751 752/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 753struct hwrm_async_event_cmpl_hw_flow_aged { 754 __le16 type; 755 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 756 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 757 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 758 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 759 __le16 event_id; 760 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 761 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 762 __le32 event_data2; 763 u8 opaque_v; 764 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 765 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 766 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 767 u8 timestamp_lo; 768 __le16 timestamp_hi; 769 __le32 event_data1; 770 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 771 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 772 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 773 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 774 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 775 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 776}; 777 778/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 779struct hwrm_async_event_cmpl_eem_cache_flush_req { 780 __le16 type; 781 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 782 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 783 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 784 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 785 __le16 event_id; 786 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 787 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 788 __le32 event_data2; 789 u8 opaque_v; 790 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 791 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 792 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 793 u8 timestamp_lo; 794 __le16 timestamp_hi; 795 __le32 event_data1; 796}; 797 798/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 799struct hwrm_async_event_cmpl_eem_cache_flush_done { 800 __le16 type; 801 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 802 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 803 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 804 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 805 __le16 event_id; 806 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 807 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 808 __le32 event_data2; 809 u8 opaque_v; 810 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 811 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 812 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 813 u8 timestamp_lo; 814 __le16 timestamp_hi; 815 __le32 event_data1; 816 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 817 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 818}; 819 820/* hwrm_func_reset_input (size:192b/24B) */ 821struct hwrm_func_reset_input { 822 __le16 req_type; 823 __le16 cmpl_ring; 824 __le16 seq_id; 825 __le16 target_id; 826 __le64 resp_addr; 827 __le32 enables; 828 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 829 __le16 vf_id; 830 u8 func_reset_level; 831 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 832 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 833 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 834 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 835 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 836 u8 unused_0; 837}; 838 839/* hwrm_func_reset_output (size:128b/16B) */ 840struct hwrm_func_reset_output { 841 __le16 error_code; 842 __le16 req_type; 843 __le16 seq_id; 844 __le16 resp_len; 845 u8 unused_0[7]; 846 u8 valid; 847}; 848 849/* hwrm_func_getfid_input (size:192b/24B) */ 850struct hwrm_func_getfid_input { 851 __le16 req_type; 852 __le16 cmpl_ring; 853 __le16 seq_id; 854 __le16 target_id; 855 __le64 resp_addr; 856 __le32 enables; 857 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 858 __le16 pci_id; 859 u8 unused_0[2]; 860}; 861 862/* hwrm_func_getfid_output (size:128b/16B) */ 863struct hwrm_func_getfid_output { 864 __le16 error_code; 865 __le16 req_type; 866 __le16 seq_id; 867 __le16 resp_len; 868 __le16 fid; 869 u8 unused_0[5]; 870 u8 valid; 871}; 872 873/* hwrm_func_vf_alloc_input (size:192b/24B) */ 874struct hwrm_func_vf_alloc_input { 875 __le16 req_type; 876 __le16 cmpl_ring; 877 __le16 seq_id; 878 __le16 target_id; 879 __le64 resp_addr; 880 __le32 enables; 881 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 882 __le16 first_vf_id; 883 __le16 num_vfs; 884}; 885 886/* hwrm_func_vf_alloc_output (size:128b/16B) */ 887struct hwrm_func_vf_alloc_output { 888 __le16 error_code; 889 __le16 req_type; 890 __le16 seq_id; 891 __le16 resp_len; 892 __le16 first_vf_id; 893 u8 unused_0[5]; 894 u8 valid; 895}; 896 897/* hwrm_func_vf_free_input (size:192b/24B) */ 898struct hwrm_func_vf_free_input { 899 __le16 req_type; 900 __le16 cmpl_ring; 901 __le16 seq_id; 902 __le16 target_id; 903 __le64 resp_addr; 904 __le32 enables; 905 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 906 __le16 first_vf_id; 907 __le16 num_vfs; 908}; 909 910/* hwrm_func_vf_free_output (size:128b/16B) */ 911struct hwrm_func_vf_free_output { 912 __le16 error_code; 913 __le16 req_type; 914 __le16 seq_id; 915 __le16 resp_len; 916 u8 unused_0[7]; 917 u8 valid; 918}; 919 920/* hwrm_func_vf_cfg_input (size:448b/56B) */ 921struct hwrm_func_vf_cfg_input { 922 __le16 req_type; 923 __le16 cmpl_ring; 924 __le16 seq_id; 925 __le16 target_id; 926 __le64 resp_addr; 927 __le32 enables; 928 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 929 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 930 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 931 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 932 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 933 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 934 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 935 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 936 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 937 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 938 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 939 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 940 __le16 mtu; 941 __le16 guest_vlan; 942 __le16 async_event_cr; 943 u8 dflt_mac_addr[6]; 944 __le32 flags; 945 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 946 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 947 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 948 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 949 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 950 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 951 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 952 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 953 __le16 num_rsscos_ctxs; 954 __le16 num_cmpl_rings; 955 __le16 num_tx_rings; 956 __le16 num_rx_rings; 957 __le16 num_l2_ctxs; 958 __le16 num_vnics; 959 __le16 num_stat_ctxs; 960 __le16 num_hw_ring_grps; 961 u8 unused_0[4]; 962}; 963 964/* hwrm_func_vf_cfg_output (size:128b/16B) */ 965struct hwrm_func_vf_cfg_output { 966 __le16 error_code; 967 __le16 req_type; 968 __le16 seq_id; 969 __le16 resp_len; 970 u8 unused_0[7]; 971 u8 valid; 972}; 973 974/* hwrm_func_qcaps_input (size:192b/24B) */ 975struct hwrm_func_qcaps_input { 976 __le16 req_type; 977 __le16 cmpl_ring; 978 __le16 seq_id; 979 __le16 target_id; 980 __le64 resp_addr; 981 __le16 fid; 982 u8 unused_0[6]; 983}; 984 985/* hwrm_func_qcaps_output (size:640b/80B) */ 986struct hwrm_func_qcaps_output { 987 __le16 error_code; 988 __le16 req_type; 989 __le16 seq_id; 990 __le16 resp_len; 991 __le16 fid; 992 __le16 port_id; 993 __le32 flags; 994 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 995 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 996 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 997 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 998 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 999 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1000 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1001 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1002 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1003 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1004 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1005 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1006 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1007 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1008 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1009 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1010 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1011 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1012 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1013 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1014 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1015 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1016 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1017 u8 mac_address[6]; 1018 __le16 max_rsscos_ctx; 1019 __le16 max_cmpl_rings; 1020 __le16 max_tx_rings; 1021 __le16 max_rx_rings; 1022 __le16 max_l2_ctxs; 1023 __le16 max_vnics; 1024 __le16 first_vf_id; 1025 __le16 max_vfs; 1026 __le16 max_stat_ctx; 1027 __le32 max_encap_records; 1028 __le32 max_decap_records; 1029 __le32 max_tx_em_flows; 1030 __le32 max_tx_wm_flows; 1031 __le32 max_rx_em_flows; 1032 __le32 max_rx_wm_flows; 1033 __le32 max_mcast_filters; 1034 __le32 max_flow_id; 1035 __le32 max_hw_ring_grps; 1036 __le16 max_sp_tx_rings; 1037 u8 unused_0; 1038 u8 valid; 1039}; 1040 1041/* hwrm_func_qcfg_input (size:192b/24B) */ 1042struct hwrm_func_qcfg_input { 1043 __le16 req_type; 1044 __le16 cmpl_ring; 1045 __le16 seq_id; 1046 __le16 target_id; 1047 __le64 resp_addr; 1048 __le16 fid; 1049 u8 unused_0[6]; 1050}; 1051 1052/* hwrm_func_qcfg_output (size:704b/88B) */ 1053struct hwrm_func_qcfg_output { 1054 __le16 error_code; 1055 __le16 req_type; 1056 __le16 seq_id; 1057 __le16 resp_len; 1058 __le16 fid; 1059 __le16 port_id; 1060 __le16 vlan; 1061 __le16 flags; 1062 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1063 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1064 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1065 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1066 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1067 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1068 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1069 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1070 u8 mac_address[6]; 1071 __le16 pci_id; 1072 __le16 alloc_rsscos_ctx; 1073 __le16 alloc_cmpl_rings; 1074 __le16 alloc_tx_rings; 1075 __le16 alloc_rx_rings; 1076 __le16 alloc_l2_ctx; 1077 __le16 alloc_vnics; 1078 __le16 mtu; 1079 __le16 mru; 1080 __le16 stat_ctx_id; 1081 u8 port_partition_type; 1082 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1083 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1084 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1085 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1086 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1087 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1088 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1089 u8 port_pf_cnt; 1090 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1091 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1092 __le16 dflt_vnic_id; 1093 __le16 max_mtu_configured; 1094 __le32 min_bw; 1095 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1096 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1097 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1098 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1099 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1100 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1101 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1102 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1103 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1104 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1105 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1106 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1107 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1108 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1109 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1110 __le32 max_bw; 1111 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1112 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1113 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1114 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1115 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1116 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1117 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1118 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1119 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1120 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1121 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1122 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1123 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1124 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1125 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1126 u8 evb_mode; 1127 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1128 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1129 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1130 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1131 u8 options; 1132 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1133 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1134 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1135 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1136 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1137 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1138 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1139 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1140 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1141 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1142 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1143 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1144 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1145 __le16 alloc_vfs; 1146 __le32 alloc_mcast_filters; 1147 __le32 alloc_hw_ring_grps; 1148 __le16 alloc_sp_tx_rings; 1149 __le16 alloc_stat_ctx; 1150 __le16 alloc_msix; 1151 __le16 registered_vfs; 1152 u8 unused_1[3]; 1153 u8 always_1; 1154 __le32 reset_addr_poll; 1155 u8 unused_2[3]; 1156 u8 valid; 1157}; 1158 1159/* hwrm_func_cfg_input (size:704b/88B) */ 1160struct hwrm_func_cfg_input { 1161 __le16 req_type; 1162 __le16 cmpl_ring; 1163 __le16 seq_id; 1164 __le16 target_id; 1165 __le64 resp_addr; 1166 __le16 fid; 1167 __le16 num_msix; 1168 __le32 flags; 1169 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1170 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1171 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1172 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1173 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1174 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1175 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1176 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1177 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1178 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1179 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1180 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1181 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1182 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1183 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1184 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1185 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1186 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1187 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1188 __le32 enables; 1189 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1190 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1191 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1192 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1193 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1194 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1195 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1196 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1197 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1198 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1199 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1200 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1201 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1202 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1203 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1204 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1205 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1206 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1207 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1208 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1209 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1210 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1211 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1212 __le16 mtu; 1213 __le16 mru; 1214 __le16 num_rsscos_ctxs; 1215 __le16 num_cmpl_rings; 1216 __le16 num_tx_rings; 1217 __le16 num_rx_rings; 1218 __le16 num_l2_ctxs; 1219 __le16 num_vnics; 1220 __le16 num_stat_ctxs; 1221 __le16 num_hw_ring_grps; 1222 u8 dflt_mac_addr[6]; 1223 __le16 dflt_vlan; 1224 __be32 dflt_ip_addr[4]; 1225 __le32 min_bw; 1226 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1227 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1228 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1229 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1230 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1231 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1232 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1233 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1234 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1235 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1236 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1237 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1238 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1239 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1240 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1241 __le32 max_bw; 1242 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1243 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1244 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1245 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1246 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1247 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1248 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1249 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1250 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1251 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1252 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1253 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1254 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1255 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1256 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1257 __le16 async_event_cr; 1258 u8 vlan_antispoof_mode; 1259 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1260 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1261 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1262 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1263 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1264 u8 allowed_vlan_pris; 1265 u8 evb_mode; 1266 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1267 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1268 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1269 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1270 u8 options; 1271 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1272 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1273 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1274 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1275 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1276 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1277 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1278 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1279 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1280 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1281 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1282 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1283 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1284 __le16 num_mcast_filters; 1285}; 1286 1287/* hwrm_func_cfg_output (size:128b/16B) */ 1288struct hwrm_func_cfg_output { 1289 __le16 error_code; 1290 __le16 req_type; 1291 __le16 seq_id; 1292 __le16 resp_len; 1293 u8 unused_0[7]; 1294 u8 valid; 1295}; 1296 1297/* hwrm_func_qstats_input (size:192b/24B) */ 1298struct hwrm_func_qstats_input { 1299 __le16 req_type; 1300 __le16 cmpl_ring; 1301 __le16 seq_id; 1302 __le16 target_id; 1303 __le64 resp_addr; 1304 __le16 fid; 1305 u8 unused_0[6]; 1306}; 1307 1308/* hwrm_func_qstats_output (size:1408b/176B) */ 1309struct hwrm_func_qstats_output { 1310 __le16 error_code; 1311 __le16 req_type; 1312 __le16 seq_id; 1313 __le16 resp_len; 1314 __le64 tx_ucast_pkts; 1315 __le64 tx_mcast_pkts; 1316 __le64 tx_bcast_pkts; 1317 __le64 tx_discard_pkts; 1318 __le64 tx_drop_pkts; 1319 __le64 tx_ucast_bytes; 1320 __le64 tx_mcast_bytes; 1321 __le64 tx_bcast_bytes; 1322 __le64 rx_ucast_pkts; 1323 __le64 rx_mcast_pkts; 1324 __le64 rx_bcast_pkts; 1325 __le64 rx_discard_pkts; 1326 __le64 rx_drop_pkts; 1327 __le64 rx_ucast_bytes; 1328 __le64 rx_mcast_bytes; 1329 __le64 rx_bcast_bytes; 1330 __le64 rx_agg_pkts; 1331 __le64 rx_agg_bytes; 1332 __le64 rx_agg_events; 1333 __le64 rx_agg_aborts; 1334 u8 unused_0[7]; 1335 u8 valid; 1336}; 1337 1338/* hwrm_func_clr_stats_input (size:192b/24B) */ 1339struct hwrm_func_clr_stats_input { 1340 __le16 req_type; 1341 __le16 cmpl_ring; 1342 __le16 seq_id; 1343 __le16 target_id; 1344 __le64 resp_addr; 1345 __le16 fid; 1346 u8 unused_0[6]; 1347}; 1348 1349/* hwrm_func_clr_stats_output (size:128b/16B) */ 1350struct hwrm_func_clr_stats_output { 1351 __le16 error_code; 1352 __le16 req_type; 1353 __le16 seq_id; 1354 __le16 resp_len; 1355 u8 unused_0[7]; 1356 u8 valid; 1357}; 1358 1359/* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1360struct hwrm_func_vf_resc_free_input { 1361 __le16 req_type; 1362 __le16 cmpl_ring; 1363 __le16 seq_id; 1364 __le16 target_id; 1365 __le64 resp_addr; 1366 __le16 vf_id; 1367 u8 unused_0[6]; 1368}; 1369 1370/* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1371struct hwrm_func_vf_resc_free_output { 1372 __le16 error_code; 1373 __le16 req_type; 1374 __le16 seq_id; 1375 __le16 resp_len; 1376 u8 unused_0[7]; 1377 u8 valid; 1378}; 1379 1380/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1381struct hwrm_func_drv_rgtr_input { 1382 __le16 req_type; 1383 __le16 cmpl_ring; 1384 __le16 seq_id; 1385 __le16 target_id; 1386 __le64 resp_addr; 1387 __le32 flags; 1388 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1389 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1390 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1391 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1392 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1393 __le32 enables; 1394 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1395 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1396 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1397 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1398 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1399 __le16 os_type; 1400 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1401 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1402 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1403 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1404 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1405 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1406 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1407 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1408 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1409 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1410 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1411 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1412 u8 ver_maj_8b; 1413 u8 ver_min_8b; 1414 u8 ver_upd_8b; 1415 u8 unused_0[3]; 1416 __le32 timestamp; 1417 u8 unused_1[4]; 1418 __le32 vf_req_fwd[8]; 1419 __le32 async_event_fwd[8]; 1420 __le16 ver_maj; 1421 __le16 ver_min; 1422 __le16 ver_upd; 1423 __le16 ver_patch; 1424}; 1425 1426/* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1427struct hwrm_func_drv_rgtr_output { 1428 __le16 error_code; 1429 __le16 req_type; 1430 __le16 seq_id; 1431 __le16 resp_len; 1432 __le32 flags; 1433 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1434 u8 unused_0[3]; 1435 u8 valid; 1436}; 1437 1438/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1439struct hwrm_func_drv_unrgtr_input { 1440 __le16 req_type; 1441 __le16 cmpl_ring; 1442 __le16 seq_id; 1443 __le16 target_id; 1444 __le64 resp_addr; 1445 __le32 flags; 1446 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1447 u8 unused_0[4]; 1448}; 1449 1450/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1451struct hwrm_func_drv_unrgtr_output { 1452 __le16 error_code; 1453 __le16 req_type; 1454 __le16 seq_id; 1455 __le16 resp_len; 1456 u8 unused_0[7]; 1457 u8 valid; 1458}; 1459 1460/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1461struct hwrm_func_buf_rgtr_input { 1462 __le16 req_type; 1463 __le16 cmpl_ring; 1464 __le16 seq_id; 1465 __le16 target_id; 1466 __le64 resp_addr; 1467 __le32 enables; 1468 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1469 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1470 __le16 vf_id; 1471 __le16 req_buf_num_pages; 1472 __le16 req_buf_page_size; 1473 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1474 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1475 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1476 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1477 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1478 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1479 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1480 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1481 __le16 req_buf_len; 1482 __le16 resp_buf_len; 1483 u8 unused_0[2]; 1484 __le64 req_buf_page_addr0; 1485 __le64 req_buf_page_addr1; 1486 __le64 req_buf_page_addr2; 1487 __le64 req_buf_page_addr3; 1488 __le64 req_buf_page_addr4; 1489 __le64 req_buf_page_addr5; 1490 __le64 req_buf_page_addr6; 1491 __le64 req_buf_page_addr7; 1492 __le64 req_buf_page_addr8; 1493 __le64 req_buf_page_addr9; 1494 __le64 error_buf_addr; 1495 __le64 resp_buf_addr; 1496}; 1497 1498/* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1499struct hwrm_func_buf_rgtr_output { 1500 __le16 error_code; 1501 __le16 req_type; 1502 __le16 seq_id; 1503 __le16 resp_len; 1504 u8 unused_0[7]; 1505 u8 valid; 1506}; 1507 1508/* hwrm_func_drv_qver_input (size:192b/24B) */ 1509struct hwrm_func_drv_qver_input { 1510 __le16 req_type; 1511 __le16 cmpl_ring; 1512 __le16 seq_id; 1513 __le16 target_id; 1514 __le64 resp_addr; 1515 __le32 reserved; 1516 __le16 fid; 1517 u8 unused_0[2]; 1518}; 1519 1520/* hwrm_func_drv_qver_output (size:256b/32B) */ 1521struct hwrm_func_drv_qver_output { 1522 __le16 error_code; 1523 __le16 req_type; 1524 __le16 seq_id; 1525 __le16 resp_len; 1526 __le16 os_type; 1527 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1528 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1529 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1530 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1531 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1532 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1533 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1534 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1535 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1536 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1537 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1538 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1539 u8 ver_maj_8b; 1540 u8 ver_min_8b; 1541 u8 ver_upd_8b; 1542 u8 unused_0[3]; 1543 __le16 ver_maj; 1544 __le16 ver_min; 1545 __le16 ver_upd; 1546 __le16 ver_patch; 1547 u8 unused_1[7]; 1548 u8 valid; 1549}; 1550 1551/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1552struct hwrm_func_resource_qcaps_input { 1553 __le16 req_type; 1554 __le16 cmpl_ring; 1555 __le16 seq_id; 1556 __le16 target_id; 1557 __le64 resp_addr; 1558 __le16 fid; 1559 u8 unused_0[6]; 1560}; 1561 1562/* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1563struct hwrm_func_resource_qcaps_output { 1564 __le16 error_code; 1565 __le16 req_type; 1566 __le16 seq_id; 1567 __le16 resp_len; 1568 __le16 max_vfs; 1569 __le16 max_msix; 1570 __le16 vf_reservation_strategy; 1571 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1572 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1573 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1574 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1575 __le16 min_rsscos_ctx; 1576 __le16 max_rsscos_ctx; 1577 __le16 min_cmpl_rings; 1578 __le16 max_cmpl_rings; 1579 __le16 min_tx_rings; 1580 __le16 max_tx_rings; 1581 __le16 min_rx_rings; 1582 __le16 max_rx_rings; 1583 __le16 min_l2_ctxs; 1584 __le16 max_l2_ctxs; 1585 __le16 min_vnics; 1586 __le16 max_vnics; 1587 __le16 min_stat_ctx; 1588 __le16 max_stat_ctx; 1589 __le16 min_hw_ring_grps; 1590 __le16 max_hw_ring_grps; 1591 __le16 max_tx_scheduler_inputs; 1592 __le16 flags; 1593 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1594 u8 unused_0[5]; 1595 u8 valid; 1596}; 1597 1598/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1599struct hwrm_func_vf_resource_cfg_input { 1600 __le16 req_type; 1601 __le16 cmpl_ring; 1602 __le16 seq_id; 1603 __le16 target_id; 1604 __le64 resp_addr; 1605 __le16 vf_id; 1606 __le16 max_msix; 1607 __le16 min_rsscos_ctx; 1608 __le16 max_rsscos_ctx; 1609 __le16 min_cmpl_rings; 1610 __le16 max_cmpl_rings; 1611 __le16 min_tx_rings; 1612 __le16 max_tx_rings; 1613 __le16 min_rx_rings; 1614 __le16 max_rx_rings; 1615 __le16 min_l2_ctxs; 1616 __le16 max_l2_ctxs; 1617 __le16 min_vnics; 1618 __le16 max_vnics; 1619 __le16 min_stat_ctx; 1620 __le16 max_stat_ctx; 1621 __le16 min_hw_ring_grps; 1622 __le16 max_hw_ring_grps; 1623 __le16 flags; 1624 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1625 u8 unused_0[2]; 1626}; 1627 1628/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1629struct hwrm_func_vf_resource_cfg_output { 1630 __le16 error_code; 1631 __le16 req_type; 1632 __le16 seq_id; 1633 __le16 resp_len; 1634 __le16 reserved_rsscos_ctx; 1635 __le16 reserved_cmpl_rings; 1636 __le16 reserved_tx_rings; 1637 __le16 reserved_rx_rings; 1638 __le16 reserved_l2_ctxs; 1639 __le16 reserved_vnics; 1640 __le16 reserved_stat_ctx; 1641 __le16 reserved_hw_ring_grps; 1642 u8 unused_0[7]; 1643 u8 valid; 1644}; 1645 1646/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1647struct hwrm_func_backing_store_qcaps_input { 1648 __le16 req_type; 1649 __le16 cmpl_ring; 1650 __le16 seq_id; 1651 __le16 target_id; 1652 __le64 resp_addr; 1653}; 1654 1655/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ 1656struct hwrm_func_backing_store_qcaps_output { 1657 __le16 error_code; 1658 __le16 req_type; 1659 __le16 seq_id; 1660 __le16 resp_len; 1661 __le32 qp_max_entries; 1662 __le16 qp_min_qp1_entries; 1663 __le16 qp_max_l2_entries; 1664 __le16 qp_entry_size; 1665 __le16 srq_max_l2_entries; 1666 __le32 srq_max_entries; 1667 __le16 srq_entry_size; 1668 __le16 cq_max_l2_entries; 1669 __le32 cq_max_entries; 1670 __le16 cq_entry_size; 1671 __le16 vnic_max_vnic_entries; 1672 __le16 vnic_max_ring_table_entries; 1673 __le16 vnic_entry_size; 1674 __le32 stat_max_entries; 1675 __le16 stat_entry_size; 1676 __le16 tqm_entry_size; 1677 __le32 tqm_min_entries_per_ring; 1678 __le32 tqm_max_entries_per_ring; 1679 __le32 mrav_max_entries; 1680 __le16 mrav_entry_size; 1681 __le16 tim_entry_size; 1682 __le32 tim_max_entries; 1683 u8 unused_0[2]; 1684 u8 tqm_entries_multiple; 1685 u8 valid; 1686}; 1687 1688/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1689struct hwrm_func_backing_store_cfg_input { 1690 __le16 req_type; 1691 __le16 cmpl_ring; 1692 __le16 seq_id; 1693 __le16 target_id; 1694 __le64 resp_addr; 1695 __le32 flags; 1696 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1697 __le32 enables; 1698 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1699 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1700 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1701 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1702 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1703 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1704 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1705 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1706 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1707 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1708 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1709 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1710 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1711 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1712 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1713 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1714 u8 qpc_pg_size_qpc_lvl; 1715 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1716 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1717 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1718 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1719 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1720 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1721 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1722 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1723 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1724 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1725 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1726 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1727 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1728 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1729 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1730 u8 srq_pg_size_srq_lvl; 1731 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1732 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1733 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1734 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1735 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1736 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1737 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1738 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1739 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1740 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1741 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1742 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1743 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1744 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1745 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1746 u8 cq_pg_size_cq_lvl; 1747 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1748 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1749 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1750 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1751 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1752 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1753 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1754 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1755 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1756 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1757 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1758 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1759 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1760 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1761 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1762 u8 vnic_pg_size_vnic_lvl; 1763 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1764 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1765 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1766 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1767 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1768 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1769 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1770 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1771 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1772 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1773 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 1774 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 1775 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 1776 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 1777 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 1778 u8 stat_pg_size_stat_lvl; 1779 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 1780 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 1781 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 1782 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 1783 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 1784 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 1785 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 1786 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 1787 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 1788 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 1789 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 1790 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 1791 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 1792 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 1793 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 1794 u8 tqm_sp_pg_size_tqm_sp_lvl; 1795 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 1796 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 1797 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 1798 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 1799 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 1800 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 1801 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 1802 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 1803 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 1804 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 1805 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 1806 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 1807 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 1808 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 1809 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 1810 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 1811 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 1812 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 1813 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 1814 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 1815 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 1816 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 1817 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 1818 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 1819 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 1820 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 1821 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 1822 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 1823 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 1824 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 1825 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 1826 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 1827 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 1828 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 1829 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 1830 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 1831 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 1832 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 1833 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 1834 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 1835 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 1836 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 1837 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 1838 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 1839 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 1840 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 1841 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 1842 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 1843 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 1844 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 1845 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 1846 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 1847 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 1848 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 1849 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 1850 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 1851 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 1852 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 1853 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 1854 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 1855 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 1856 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 1857 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 1858 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 1859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 1860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 1861 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 1862 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 1863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 1864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 1865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 1866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 1867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 1868 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 1869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 1870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 1871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 1872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 1873 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 1874 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 1875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 1876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 1877 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 1878 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 1879 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 1880 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 1881 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 1882 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 1883 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 1884 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 1885 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 1886 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 1887 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 1888 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 1889 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 1890 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 1891 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 1892 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 1893 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 1894 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 1895 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 1896 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 1897 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 1898 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 1899 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 1900 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 1901 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 1902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 1903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 1904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 1905 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 1906 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 1907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 1908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 1909 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 1910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 1911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 1912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 1913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 1914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 1915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 1916 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 1917 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 1918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 1919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 1920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 1921 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 1922 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 1925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 1932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 1937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 1938 u8 mrav_pg_size_mrav_lvl; 1939 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 1940 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 1941 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 1942 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 1943 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 1944 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 1945 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 1946 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 1947 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 1948 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 1949 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 1950 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 1951 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 1952 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 1953 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 1954 u8 tim_pg_size_tim_lvl; 1955 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 1956 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 1957 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 1958 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 1959 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 1960 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 1961 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 1962 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 1963 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 1964 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 1965 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 1966 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 1967 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 1968 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 1969 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 1970 __le64 qpc_page_dir; 1971 __le64 srq_page_dir; 1972 __le64 cq_page_dir; 1973 __le64 vnic_page_dir; 1974 __le64 stat_page_dir; 1975 __le64 tqm_sp_page_dir; 1976 __le64 tqm_ring0_page_dir; 1977 __le64 tqm_ring1_page_dir; 1978 __le64 tqm_ring2_page_dir; 1979 __le64 tqm_ring3_page_dir; 1980 __le64 tqm_ring4_page_dir; 1981 __le64 tqm_ring5_page_dir; 1982 __le64 tqm_ring6_page_dir; 1983 __le64 tqm_ring7_page_dir; 1984 __le64 mrav_page_dir; 1985 __le64 tim_page_dir; 1986 __le32 qp_num_entries; 1987 __le32 srq_num_entries; 1988 __le32 cq_num_entries; 1989 __le32 stat_num_entries; 1990 __le32 tqm_sp_num_entries; 1991 __le32 tqm_ring0_num_entries; 1992 __le32 tqm_ring1_num_entries; 1993 __le32 tqm_ring2_num_entries; 1994 __le32 tqm_ring3_num_entries; 1995 __le32 tqm_ring4_num_entries; 1996 __le32 tqm_ring5_num_entries; 1997 __le32 tqm_ring6_num_entries; 1998 __le32 tqm_ring7_num_entries; 1999 __le32 mrav_num_entries; 2000 __le32 tim_num_entries;
2001 __le16 qp_num_qp1_entries; 2002 __le16 qp_num_l2_entries; 2003 __le16 qp_entry_size; 2004 __le16 srq_num_l2_entries; 2005 __le16 srq_entry_size; 2006 __le16 cq_num_l2_entries; 2007 __le16 cq_entry_size; 2008 __le16 vnic_num_vnic_entries; 2009 __le16 vnic_num_ring_table_entries; 2010 __le16 vnic_entry_size; 2011 __le16 stat_entry_size; 2012 __le16 tqm_entry_size; 2013 __le16 mrav_entry_size; 2014 __le16 tim_entry_size; 2015}; 2016 2017/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2018struct hwrm_func_backing_store_cfg_output { 2019 __le16 error_code; 2020 __le16 req_type; 2021 __le16 seq_id; 2022 __le16 resp_len; 2023 u8 unused_0[7]; 2024 u8 valid; 2025}; 2026 2027/* hwrm_func_drv_if_change_input (size:192b/24B) */ 2028struct hwrm_func_drv_if_change_input { 2029 __le16 req_type; 2030 __le16 cmpl_ring; 2031 __le16 seq_id; 2032 __le16 target_id; 2033 __le64 resp_addr; 2034 __le32 flags; 2035 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2036 __le32 unused; 2037}; 2038 2039/* hwrm_func_drv_if_change_output (size:128b/16B) */ 2040struct hwrm_func_drv_if_change_output { 2041 __le16 error_code; 2042 __le16 req_type; 2043 __le16 seq_id; 2044 __le16 resp_len; 2045 __le32 flags; 2046 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2047 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2048 u8 unused_0[3]; 2049 u8 valid; 2050}; 2051 2052/* hwrm_port_phy_cfg_input (size:448b/56B) */ 2053struct hwrm_port_phy_cfg_input { 2054 __le16 req_type; 2055 __le16 cmpl_ring; 2056 __le16 seq_id; 2057 __le16 target_id; 2058 __le64 resp_addr; 2059 __le32 flags; 2060 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2061 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2062 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2063 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2064 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2065 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2066 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2067 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2068 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2069 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2070 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2071 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2072 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2073 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2074 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2075 __le32 enables; 2076 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2077 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2078 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2079 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2080 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2081 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2082 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2083 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2084 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2085 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2086 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2087 __le16 port_id; 2088 __le16 force_link_speed; 2089 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2090 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2091 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2092 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2093 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2094 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2095 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2096 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2097 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2098 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2099 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 2100 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2101 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2102 u8 auto_mode; 2103 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2104 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2105 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2106 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2107 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2108 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2109 u8 auto_duplex; 2110 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2111 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2112 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2113 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2114 u8 auto_pause; 2115 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2116 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2117 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2118 u8 unused_0; 2119 __le16 auto_link_speed; 2120 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2121 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2122 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2123 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2124 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2125 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2126 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2127 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2128 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2129 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2130 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 2131 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2132 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2133 __le16 auto_link_speed_mask; 2134 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2135 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2136 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2137 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2138 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2139 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2140 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2141 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2142 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2143 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2144 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2145 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2146 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2147 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2148 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2149 u8 wirespeed; 2150 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2151 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2152 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2153 u8 lpbk; 2154 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2155 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2156 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2157 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2158 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2159 u8 force_pause; 2160 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2161 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2162 u8 unused_1; 2163 __le32 preemphasis; 2164 __le16 eee_link_speed_mask; 2165 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2166 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2167 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2168 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2169 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2170 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2171 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2172 u8 unused_2[2]; 2173 __le32 tx_lpi_timer; 2174 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2175 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2176 __le32 unused_3; 2177}; 2178 2179/* hwrm_port_phy_cfg_output (size:128b/16B) */ 2180struct hwrm_port_phy_cfg_output { 2181 __le16 error_code; 2182 __le16 req_type; 2183 __le16 seq_id; 2184 __le16 resp_len; 2185 u8 unused_0[7]; 2186 u8 valid; 2187}; 2188 2189/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2190struct hwrm_port_phy_cfg_cmd_err { 2191 u8 code; 2192 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2193 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2194 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2195 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2196 u8 unused_0[7]; 2197}; 2198 2199/* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2200struct hwrm_port_phy_qcfg_input { 2201 __le16 req_type; 2202 __le16 cmpl_ring; 2203 __le16 seq_id; 2204 __le16 target_id; 2205 __le64 resp_addr; 2206 __le16 port_id; 2207 u8 unused_0[6]; 2208}; 2209 2210/* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2211struct hwrm_port_phy_qcfg_output { 2212 __le16 error_code; 2213 __le16 req_type; 2214 __le16 seq_id; 2215 __le16 resp_len; 2216 u8 link; 2217 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2218 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2219 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2220 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2221 u8 unused_0; 2222 __le16 link_speed; 2223 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2224 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2225 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2226 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2227 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2228 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2229 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2230 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2231 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2232 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2233 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2234 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2235 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2236 u8 duplex_cfg; 2237 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2238 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2239 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2240 u8 pause; 2241 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2242 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2243 __le16 support_speeds; 2244 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2245 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2246 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2247 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2248 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2249 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2250 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2251 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2252 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2253 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2254 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2255 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2256 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2257 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2258 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2259 __le16 force_link_speed; 2260 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2261 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2262 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2263 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2264 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2265 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2266 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2267 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2268 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2269 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2270 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2271 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2272 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2273 u8 auto_mode; 2274 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2275 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2276 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2277 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2278 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2279 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2280 u8 auto_pause; 2281 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2282 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2283 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2284 __le16 auto_link_speed; 2285 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2286 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2287 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2288 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2289 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2290 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2291 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2292 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2293 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2294 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2295 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2296 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2297 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2298 __le16 auto_link_speed_mask; 2299 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2300 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2301 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2302 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2303 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2304 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2305 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2306 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2307 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2308 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2309 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2310 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2311 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2312 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2313 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2314 u8 wirespeed; 2315 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2316 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2317 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2318 u8 lpbk; 2319 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2320 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2321 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2322 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2323 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2324 u8 force_pause; 2325 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2326 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2327 u8 module_status; 2328 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2329 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2330 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2331 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2332 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2333 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2334 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2335 __le32 preemphasis; 2336 u8 phy_maj; 2337 u8 phy_min; 2338 u8 phy_bld; 2339 u8 phy_type; 2340 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2341 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2342 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2343 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2344 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2345 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2346 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2347 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2348 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2349 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2350 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2351 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2352 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2353 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2354 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2355 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2356 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2357 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2358 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2359 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2360 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2361 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2362 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2363 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2364 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2365 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2366 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2367 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2368 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2369 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2370 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2371 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2372 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2373 u8 media_type; 2374 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2375 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2376 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2377 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2378 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2379 u8 xcvr_pkg_type; 2380 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2381 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2382 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2383 u8 eee_config_phy_addr; 2384 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2385 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2386 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2387 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2388 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2389 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2390 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2391 u8 parallel_detect; 2392 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2393 __le16 link_partner_adv_speeds; 2394 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2395 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2396 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2397 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2398 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2399 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2400 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2401 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2402 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2403 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2404 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2405 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2406 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2407 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2408 u8 link_partner_adv_auto_mode; 2409 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2410 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2411 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2412 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2413 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2414 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2415 u8 link_partner_adv_pause; 2416 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2417 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2418 __le16 adv_eee_link_speed_mask; 2419 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2420 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2421 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2422 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2423 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2424 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2425 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2426 __le16 link_partner_adv_eee_link_speed_mask; 2427 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2428 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2429 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2430 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2431 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2432 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2433 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2434 __le32 xcvr_identifier_type_tx_lpi_timer; 2435 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2436 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2437 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2438 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2439 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2440 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2441 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2442 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2443 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2444 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2445 __le16 fec_cfg; 2446 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2447 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2448 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2449 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2450 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2451 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2452 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2453 u8 duplex_state; 2454 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2455 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2456 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2457 u8 option_flags; 2458 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2459 char phy_vendor_name[16]; 2460 char phy_vendor_partnumber[16]; 2461 u8 unused_2[7]; 2462 u8 valid; 2463}; 2464 2465/* hwrm_port_mac_cfg_input (size:320b/40B) */ 2466struct hwrm_port_mac_cfg_input { 2467 __le16 req_type; 2468 __le16 cmpl_ring; 2469 __le16 seq_id; 2470 __le16 target_id; 2471 __le64 resp_addr; 2472 __le32 flags; 2473 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2474 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2475 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2476 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2477 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2478 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2479 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2480 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2481 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2482 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2483 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2484 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2485 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2486 __le32 enables; 2487 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2488 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2489 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2490 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2491 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2492 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2493 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2494 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2495 __le16 port_id; 2496 u8 ipg; 2497 u8 lpbk; 2498 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2499 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2500 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2501 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2502 u8 vlan_pri2cos_map_pri; 2503 u8 reserved1; 2504 u8 tunnel_pri2cos_map_pri; 2505 u8 dscp2pri_map_pri; 2506 __le16 rx_ts_capture_ptp_msg_type; 2507 __le16 tx_ts_capture_ptp_msg_type; 2508 u8 cos_field_cfg; 2509 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2510 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2511 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2512 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2513 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2514 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2515 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2516 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2517 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2518 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2519 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2520 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2521 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2522 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2523 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2524 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2525 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2526 u8 unused_0[3]; 2527}; 2528 2529/* hwrm_port_mac_cfg_output (size:128b/16B) */ 2530struct hwrm_port_mac_cfg_output { 2531 __le16 error_code; 2532 __le16 req_type; 2533 __le16 seq_id; 2534 __le16 resp_len; 2535 __le16 mru; 2536 __le16 mtu; 2537 u8 ipg; 2538 u8 lpbk; 2539 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2540 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2541 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2542 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2543 u8 unused_0; 2544 u8 valid; 2545}; 2546 2547/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2548struct hwrm_port_mac_ptp_qcfg_input { 2549 __le16 req_type; 2550 __le16 cmpl_ring; 2551 __le16 seq_id; 2552 __le16 target_id; 2553 __le64 resp_addr; 2554 __le16 port_id; 2555 u8 unused_0[6]; 2556}; 2557 2558/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2559struct hwrm_port_mac_ptp_qcfg_output { 2560 __le16 error_code; 2561 __le16 req_type; 2562 __le16 seq_id; 2563 __le16 resp_len; 2564 u8 flags; 2565 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2566 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 2567 u8 unused_0[3]; 2568 __le32 rx_ts_reg_off_lower; 2569 __le32 rx_ts_reg_off_upper; 2570 __le32 rx_ts_reg_off_seq_id; 2571 __le32 rx_ts_reg_off_src_id_0; 2572 __le32 rx_ts_reg_off_src_id_1; 2573 __le32 rx_ts_reg_off_src_id_2; 2574 __le32 rx_ts_reg_off_domain_id; 2575 __le32 rx_ts_reg_off_fifo; 2576 __le32 rx_ts_reg_off_fifo_adv; 2577 __le32 rx_ts_reg_off_granularity; 2578 __le32 tx_ts_reg_off_lower; 2579 __le32 tx_ts_reg_off_upper; 2580 __le32 tx_ts_reg_off_seq_id; 2581 __le32 tx_ts_reg_off_fifo; 2582 __le32 tx_ts_reg_off_granularity; 2583 u8 unused_1[7]; 2584 u8 valid; 2585}; 2586 2587/* tx_port_stats (size:3264b/408B) */ 2588struct tx_port_stats { 2589 __le64 tx_64b_frames; 2590 __le64 tx_65b_127b_frames; 2591 __le64 tx_128b_255b_frames; 2592 __le64 tx_256b_511b_frames; 2593 __le64 tx_512b_1023b_frames; 2594 __le64 tx_1024b_1518b_frames; 2595 __le64 tx_good_vlan_frames; 2596 __le64 tx_1519b_2047b_frames; 2597 __le64 tx_2048b_4095b_frames; 2598 __le64 tx_4096b_9216b_frames; 2599 __le64 tx_9217b_16383b_frames; 2600 __le64 tx_good_frames; 2601 __le64 tx_total_frames; 2602 __le64 tx_ucast_frames; 2603 __le64 tx_mcast_frames; 2604 __le64 tx_bcast_frames; 2605 __le64 tx_pause_frames; 2606 __le64 tx_pfc_frames; 2607 __le64 tx_jabber_frames; 2608 __le64 tx_fcs_err_frames; 2609 __le64 tx_control_frames; 2610 __le64 tx_oversz_frames; 2611 __le64 tx_single_dfrl_frames; 2612 __le64 tx_multi_dfrl_frames; 2613 __le64 tx_single_coll_frames; 2614 __le64 tx_multi_coll_frames; 2615 __le64 tx_late_coll_frames; 2616 __le64 tx_excessive_coll_frames; 2617 __le64 tx_frag_frames; 2618 __le64 tx_err; 2619 __le64 tx_tagged_frames; 2620 __le64 tx_dbl_tagged_frames; 2621 __le64 tx_runt_frames; 2622 __le64 tx_fifo_underruns; 2623 __le64 tx_pfc_ena_frames_pri0; 2624 __le64 tx_pfc_ena_frames_pri1; 2625 __le64 tx_pfc_ena_frames_pri2; 2626 __le64 tx_pfc_ena_frames_pri3; 2627 __le64 tx_pfc_ena_frames_pri4; 2628 __le64 tx_pfc_ena_frames_pri5; 2629 __le64 tx_pfc_ena_frames_pri6; 2630 __le64 tx_pfc_ena_frames_pri7; 2631 __le64 tx_eee_lpi_events; 2632 __le64 tx_eee_lpi_duration; 2633 __le64 tx_llfc_logical_msgs; 2634 __le64 tx_hcfc_msgs; 2635 __le64 tx_total_collisions; 2636 __le64 tx_bytes; 2637 __le64 tx_xthol_frames; 2638 __le64 tx_stat_discard; 2639 __le64 tx_stat_error; 2640}; 2641 2642/* rx_port_stats (size:4224b/528B) */ 2643struct rx_port_stats { 2644 __le64 rx_64b_frames; 2645 __le64 rx_65b_127b_frames; 2646 __le64 rx_128b_255b_frames; 2647 __le64 rx_256b_511b_frames; 2648 __le64 rx_512b_1023b_frames; 2649 __le64 rx_1024b_1518b_frames; 2650 __le64 rx_good_vlan_frames; 2651 __le64 rx_1519b_2047b_frames; 2652 __le64 rx_2048b_4095b_frames; 2653 __le64 rx_4096b_9216b_frames; 2654 __le64 rx_9217b_16383b_frames; 2655 __le64 rx_total_frames; 2656 __le64 rx_ucast_frames; 2657 __le64 rx_mcast_frames; 2658 __le64 rx_bcast_frames; 2659 __le64 rx_fcs_err_frames; 2660 __le64 rx_ctrl_frames; 2661 __le64 rx_pause_frames; 2662 __le64 rx_pfc_frames; 2663 __le64 rx_unsupported_opcode_frames; 2664 __le64 rx_unsupported_da_pausepfc_frames; 2665 __le64 rx_wrong_sa_frames; 2666 __le64 rx_align_err_frames; 2667 __le64 rx_oor_len_frames; 2668 __le64 rx_code_err_frames; 2669 __le64 rx_false_carrier_frames; 2670 __le64 rx_ovrsz_frames; 2671 __le64 rx_jbr_frames; 2672 __le64 rx_mtu_err_frames; 2673 __le64 rx_match_crc_frames; 2674 __le64 rx_promiscuous_frames; 2675 __le64 rx_tagged_frames; 2676 __le64 rx_double_tagged_frames; 2677 __le64 rx_trunc_frames; 2678 __le64 rx_good_frames; 2679 __le64 rx_pfc_xon2xoff_frames_pri0; 2680 __le64 rx_pfc_xon2xoff_frames_pri1; 2681 __le64 rx_pfc_xon2xoff_frames_pri2; 2682 __le64 rx_pfc_xon2xoff_frames_pri3; 2683 __le64 rx_pfc_xon2xoff_frames_pri4; 2684 __le64 rx_pfc_xon2xoff_frames_pri5; 2685 __le64 rx_pfc_xon2xoff_frames_pri6; 2686 __le64 rx_pfc_xon2xoff_frames_pri7; 2687 __le64 rx_pfc_ena_frames_pri0; 2688 __le64 rx_pfc_ena_frames_pri1; 2689 __le64 rx_pfc_ena_frames_pri2; 2690 __le64 rx_pfc_ena_frames_pri3; 2691 __le64 rx_pfc_ena_frames_pri4; 2692 __le64 rx_pfc_ena_frames_pri5; 2693 __le64 rx_pfc_ena_frames_pri6; 2694 __le64 rx_pfc_ena_frames_pri7; 2695 __le64 rx_sch_crc_err_frames; 2696 __le64 rx_undrsz_frames; 2697 __le64 rx_frag_frames; 2698 __le64 rx_eee_lpi_events; 2699 __le64 rx_eee_lpi_duration; 2700 __le64 rx_llfc_physical_msgs; 2701 __le64 rx_llfc_logical_msgs; 2702 __le64 rx_llfc_msgs_with_crc_err; 2703 __le64 rx_hcfc_msgs; 2704 __le64 rx_hcfc_msgs_with_crc_err; 2705 __le64 rx_bytes; 2706 __le64 rx_runt_bytes; 2707 __le64 rx_runt_frames; 2708 __le64 rx_stat_discard; 2709 __le64 rx_stat_err; 2710}; 2711 2712/* hwrm_port_qstats_input (size:320b/40B) */ 2713struct hwrm_port_qstats_input { 2714 __le16 req_type; 2715 __le16 cmpl_ring; 2716 __le16 seq_id; 2717 __le16 target_id; 2718 __le64 resp_addr; 2719 __le16 port_id; 2720 u8 unused_0[6]; 2721 __le64 tx_stat_host_addr; 2722 __le64 rx_stat_host_addr; 2723}; 2724 2725/* hwrm_port_qstats_output (size:128b/16B) */ 2726struct hwrm_port_qstats_output { 2727 __le16 error_code; 2728 __le16 req_type; 2729 __le16 seq_id; 2730 __le16 resp_len; 2731 __le16 tx_stat_size; 2732 __le16 rx_stat_size; 2733 u8 unused_0[3]; 2734 u8 valid; 2735}; 2736 2737/* tx_port_stats_ext (size:2048b/256B) */ 2738struct tx_port_stats_ext { 2739 __le64 tx_bytes_cos0; 2740 __le64 tx_bytes_cos1; 2741 __le64 tx_bytes_cos2; 2742 __le64 tx_bytes_cos3; 2743 __le64 tx_bytes_cos4; 2744 __le64 tx_bytes_cos5; 2745 __le64 tx_bytes_cos6; 2746 __le64 tx_bytes_cos7; 2747 __le64 tx_packets_cos0; 2748 __le64 tx_packets_cos1; 2749 __le64 tx_packets_cos2; 2750 __le64 tx_packets_cos3; 2751 __le64 tx_packets_cos4; 2752 __le64 tx_packets_cos5; 2753 __le64 tx_packets_cos6; 2754 __le64 tx_packets_cos7; 2755 __le64 pfc_pri0_tx_duration_us; 2756 __le64 pfc_pri0_tx_transitions; 2757 __le64 pfc_pri1_tx_duration_us; 2758 __le64 pfc_pri1_tx_transitions; 2759 __le64 pfc_pri2_tx_duration_us; 2760 __le64 pfc_pri2_tx_transitions; 2761 __le64 pfc_pri3_tx_duration_us; 2762 __le64 pfc_pri3_tx_transitions; 2763 __le64 pfc_pri4_tx_duration_us; 2764 __le64 pfc_pri4_tx_transitions; 2765 __le64 pfc_pri5_tx_duration_us; 2766 __le64 pfc_pri5_tx_transitions; 2767 __le64 pfc_pri6_tx_duration_us; 2768 __le64 pfc_pri6_tx_transitions; 2769 __le64 pfc_pri7_tx_duration_us; 2770 __le64 pfc_pri7_tx_transitions; 2771}; 2772 2773/* rx_port_stats_ext (size:2368b/296B) */ 2774struct rx_port_stats_ext { 2775 __le64 link_down_events; 2776 __le64 continuous_pause_events; 2777 __le64 resume_pause_events; 2778 __le64 continuous_roce_pause_events; 2779 __le64 resume_roce_pause_events; 2780 __le64 rx_bytes_cos0; 2781 __le64 rx_bytes_cos1; 2782 __le64 rx_bytes_cos2; 2783 __le64 rx_bytes_cos3; 2784 __le64 rx_bytes_cos4; 2785 __le64 rx_bytes_cos5; 2786 __le64 rx_bytes_cos6; 2787 __le64 rx_bytes_cos7; 2788 __le64 rx_packets_cos0; 2789 __le64 rx_packets_cos1; 2790 __le64 rx_packets_cos2; 2791 __le64 rx_packets_cos3; 2792 __le64 rx_packets_cos4; 2793 __le64 rx_packets_cos5; 2794 __le64 rx_packets_cos6; 2795 __le64 rx_packets_cos7; 2796 __le64 pfc_pri0_rx_duration_us; 2797 __le64 pfc_pri0_rx_transitions; 2798 __le64 pfc_pri1_rx_duration_us; 2799 __le64 pfc_pri1_rx_transitions; 2800 __le64 pfc_pri2_rx_duration_us; 2801 __le64 pfc_pri2_rx_transitions; 2802 __le64 pfc_pri3_rx_duration_us; 2803 __le64 pfc_pri3_rx_transitions; 2804 __le64 pfc_pri4_rx_duration_us; 2805 __le64 pfc_pri4_rx_transitions; 2806 __le64 pfc_pri5_rx_duration_us; 2807 __le64 pfc_pri5_rx_transitions; 2808 __le64 pfc_pri6_rx_duration_us; 2809 __le64 pfc_pri6_rx_transitions; 2810 __le64 pfc_pri7_rx_duration_us; 2811 __le64 pfc_pri7_rx_transitions; 2812}; 2813 2814/* hwrm_port_qstats_ext_input (size:320b/40B) */ 2815struct hwrm_port_qstats_ext_input { 2816 __le16 req_type; 2817 __le16 cmpl_ring; 2818 __le16 seq_id; 2819 __le16 target_id; 2820 __le64 resp_addr; 2821 __le16 port_id; 2822 __le16 tx_stat_size; 2823 __le16 rx_stat_size; 2824 u8 unused_0[2]; 2825 __le64 tx_stat_host_addr; 2826 __le64 rx_stat_host_addr; 2827}; 2828 2829/* hwrm_port_qstats_ext_output (size:128b/16B) */ 2830struct hwrm_port_qstats_ext_output { 2831 __le16 error_code; 2832 __le16 req_type; 2833 __le16 seq_id; 2834 __le16 resp_len; 2835 __le16 tx_stat_size; 2836 __le16 rx_stat_size; 2837 __le16 total_active_cos_queues; 2838 u8 flags; 2839 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 2840 u8 valid; 2841}; 2842 2843/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2844struct hwrm_port_lpbk_qstats_input { 2845 __le16 req_type; 2846 __le16 cmpl_ring; 2847 __le16 seq_id; 2848 __le16 target_id; 2849 __le64 resp_addr; 2850}; 2851 2852/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 2853struct hwrm_port_lpbk_qstats_output { 2854 __le16 error_code; 2855 __le16 req_type; 2856 __le16 seq_id; 2857 __le16 resp_len; 2858 __le64 lpbk_ucast_frames; 2859 __le64 lpbk_mcast_frames; 2860 __le64 lpbk_bcast_frames; 2861 __le64 lpbk_ucast_bytes; 2862 __le64 lpbk_mcast_bytes; 2863 __le64 lpbk_bcast_bytes; 2864 __le64 tx_stat_discard; 2865 __le64 tx_stat_error; 2866 __le64 rx_stat_discard; 2867 __le64 rx_stat_error; 2868 u8 unused_0[7]; 2869 u8 valid; 2870}; 2871 2872/* hwrm_port_clr_stats_input (size:192b/24B) */ 2873struct hwrm_port_clr_stats_input { 2874 __le16 req_type; 2875 __le16 cmpl_ring; 2876 __le16 seq_id; 2877 __le16 target_id; 2878 __le64 resp_addr; 2879 __le16 port_id; 2880 u8 flags; 2881 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 2882 u8 unused_0[5]; 2883}; 2884 2885/* hwrm_port_clr_stats_output (size:128b/16B) */ 2886struct hwrm_port_clr_stats_output { 2887 __le16 error_code; 2888 __le16 req_type; 2889 __le16 seq_id; 2890 __le16 resp_len; 2891 u8 unused_0[7]; 2892 u8 valid; 2893}; 2894 2895/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 2896struct hwrm_port_lpbk_clr_stats_input { 2897 __le16 req_type; 2898 __le16 cmpl_ring; 2899 __le16 seq_id; 2900 __le16 target_id; 2901 __le64 resp_addr; 2902}; 2903 2904/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 2905struct hwrm_port_lpbk_clr_stats_output { 2906 __le16 error_code; 2907 __le16 req_type; 2908 __le16 seq_id; 2909 __le16 resp_len; 2910 u8 unused_0[7]; 2911 u8 valid; 2912}; 2913 2914/* hwrm_port_phy_qcaps_input (size:192b/24B) */ 2915struct hwrm_port_phy_qcaps_input { 2916 __le16 req_type; 2917 __le16 cmpl_ring; 2918 __le16 seq_id; 2919 __le16 target_id; 2920 __le64 resp_addr; 2921 __le16 port_id; 2922 u8 unused_0[6]; 2923}; 2924 2925/* hwrm_port_phy_qcaps_output (size:192b/24B) */ 2926struct hwrm_port_phy_qcaps_output { 2927 __le16 error_code; 2928 __le16 req_type; 2929 __le16 seq_id; 2930 __le16 resp_len; 2931 u8 flags; 2932 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2933 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 2934 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL 2935 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2 2936 u8 port_cnt; 2937 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2938 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2939 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 2940 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 2941 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 2942 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 2943 __le16 supported_speeds_force_mode; 2944 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2945 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2946 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2947 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2948 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2949 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2950 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2951 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2952 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2953 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2954 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2955 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2956 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2957 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2958 __le16 supported_speeds_auto_mode; 2959 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2960 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2961 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2962 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2963 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2964 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2965 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2966 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2967 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2968 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2969 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2970 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2971 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2972 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2973 __le16 supported_speeds_eee_mode; 2974 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2975 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2976 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2977 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2978 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2979 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2980 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2981 __le32 tx_lpi_timer_low; 2982 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2983 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2984 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2985 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2986 __le32 valid_tx_lpi_timer_high; 2987 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2988 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2989 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2990 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2991}; 2992 2993/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 2994struct hwrm_port_phy_i2c_read_input { 2995 __le16 req_type; 2996 __le16 cmpl_ring; 2997 __le16 seq_id; 2998 __le16 target_id; 2999 __le64 resp_addr; 3000 __le32 flags;
3001 __le32 enables; 3002 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3003 __le16 port_id; 3004 u8 i2c_slave_addr; 3005 u8 unused_0; 3006 __le16 page_number; 3007 __le16 page_offset; 3008 u8 data_length; 3009 u8 unused_1[7]; 3010}; 3011 3012/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3013struct hwrm_port_phy_i2c_read_output { 3014 __le16 error_code; 3015 __le16 req_type; 3016 __le16 seq_id; 3017 __le16 resp_len; 3018 __le32 data[16]; 3019 u8 unused_0[7]; 3020 u8 valid; 3021}; 3022 3023/* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3024struct hwrm_port_phy_mdio_write_input { 3025 __le16 req_type; 3026 __le16 cmpl_ring; 3027 __le16 seq_id; 3028 __le16 target_id; 3029 __le64 resp_addr; 3030 __le32 unused_0[2]; 3031 __le16 port_id; 3032 u8 phy_addr; 3033 u8 dev_addr; 3034 __le16 reg_addr; 3035 __le16 reg_data; 3036 u8 cl45_mdio; 3037 u8 unused_1[7]; 3038}; 3039 3040/* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3041struct hwrm_port_phy_mdio_write_output { 3042 __le16 error_code; 3043 __le16 req_type; 3044 __le16 seq_id; 3045 __le16 resp_len; 3046 u8 unused_0[7]; 3047 u8 valid; 3048}; 3049 3050/* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3051struct hwrm_port_phy_mdio_read_input { 3052 __le16 req_type; 3053 __le16 cmpl_ring; 3054 __le16 seq_id; 3055 __le16 target_id; 3056 __le64 resp_addr; 3057 __le32 unused_0[2]; 3058 __le16 port_id; 3059 u8 phy_addr; 3060 u8 dev_addr; 3061 __le16 reg_addr; 3062 u8 cl45_mdio; 3063 u8 unused_1; 3064}; 3065 3066/* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3067struct hwrm_port_phy_mdio_read_output { 3068 __le16 error_code; 3069 __le16 req_type; 3070 __le16 seq_id; 3071 __le16 resp_len; 3072 __le16 reg_data; 3073 u8 unused_0[5]; 3074 u8 valid; 3075}; 3076 3077/* hwrm_port_led_cfg_input (size:512b/64B) */ 3078struct hwrm_port_led_cfg_input { 3079 __le16 req_type; 3080 __le16 cmpl_ring; 3081 __le16 seq_id; 3082 __le16 target_id; 3083 __le64 resp_addr; 3084 __le32 enables; 3085 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3086 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3087 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3088 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3089 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3090 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3091 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3092 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3093 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3094 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3095 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3096 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3097 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3098 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3099 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3100 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3101 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3102 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3103 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3104 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3105 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3106 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3107 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3108 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3109 __le16 port_id; 3110 u8 num_leds; 3111 u8 rsvd; 3112 u8 led0_id; 3113 u8 led0_state; 3114 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3115 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3116 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3117 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3118 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3119 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3120 u8 led0_color; 3121 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3122 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3123 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3124 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3125 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3126 u8 unused_0; 3127 __le16 led0_blink_on; 3128 __le16 led0_blink_off; 3129 u8 led0_group_id; 3130 u8 rsvd0; 3131 u8 led1_id; 3132 u8 led1_state; 3133 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3134 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3135 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3136 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3137 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3138 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3139 u8 led1_color; 3140 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3141 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3142 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3143 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3144 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3145 u8 unused_1; 3146 __le16 led1_blink_on; 3147 __le16 led1_blink_off; 3148 u8 led1_group_id; 3149 u8 rsvd1; 3150 u8 led2_id; 3151 u8 led2_state; 3152 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3153 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3154 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3155 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3156 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3157 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3158 u8 led2_color; 3159 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3160 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3161 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3162 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3163 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3164 u8 unused_2; 3165 __le16 led2_blink_on; 3166 __le16 led2_blink_off; 3167 u8 led2_group_id; 3168 u8 rsvd2; 3169 u8 led3_id; 3170 u8 led3_state; 3171 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3172 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3173 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3174 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3175 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3176 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3177 u8 led3_color; 3178 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3179 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3180 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3181 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3182 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3183 u8 unused_3; 3184 __le16 led3_blink_on; 3185 __le16 led3_blink_off; 3186 u8 led3_group_id; 3187 u8 rsvd3; 3188}; 3189 3190/* hwrm_port_led_cfg_output (size:128b/16B) */ 3191struct hwrm_port_led_cfg_output { 3192 __le16 error_code; 3193 __le16 req_type; 3194 __le16 seq_id; 3195 __le16 resp_len; 3196 u8 unused_0[7]; 3197 u8 valid; 3198}; 3199 3200/* hwrm_port_led_qcfg_input (size:192b/24B) */ 3201struct hwrm_port_led_qcfg_input { 3202 __le16 req_type; 3203 __le16 cmpl_ring; 3204 __le16 seq_id; 3205 __le16 target_id; 3206 __le64 resp_addr; 3207 __le16 port_id; 3208 u8 unused_0[6]; 3209}; 3210 3211/* hwrm_port_led_qcfg_output (size:448b/56B) */ 3212struct hwrm_port_led_qcfg_output { 3213 __le16 error_code; 3214 __le16 req_type; 3215 __le16 seq_id; 3216 __le16 resp_len; 3217 u8 num_leds; 3218 u8 led0_id; 3219 u8 led0_type; 3220 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3221 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3222 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3223 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3224 u8 led0_state; 3225 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3226 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3227 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3228 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3229 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3230 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3231 u8 led0_color; 3232 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3233 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3234 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3235 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3236 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3237 u8 unused_0; 3238 __le16 led0_blink_on; 3239 __le16 led0_blink_off; 3240 u8 led0_group_id; 3241 u8 led1_id; 3242 u8 led1_type; 3243 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3244 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3245 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3246 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3247 u8 led1_state; 3248 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3249 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3250 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3251 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3252 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3253 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3254 u8 led1_color; 3255 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3256 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3257 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3258 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3259 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3260 u8 unused_1; 3261 __le16 led1_blink_on; 3262 __le16 led1_blink_off; 3263 u8 led1_group_id; 3264 u8 led2_id; 3265 u8 led2_type; 3266 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3267 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3268 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3269 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3270 u8 led2_state; 3271 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3272 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3273 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3274 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3275 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3276 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3277 u8 led2_color; 3278 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3279 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3280 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3281 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3282 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3283 u8 unused_2; 3284 __le16 led2_blink_on; 3285 __le16 led2_blink_off; 3286 u8 led2_group_id; 3287 u8 led3_id; 3288 u8 led3_type; 3289 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3290 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3291 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3292 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3293 u8 led3_state; 3294 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3295 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3296 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3297 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3298 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3299 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3300 u8 led3_color; 3301 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3302 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3303 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3304 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3305 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3306 u8 unused_3; 3307 __le16 led3_blink_on; 3308 __le16 led3_blink_off; 3309 u8 led3_group_id; 3310 u8 unused_4[6]; 3311 u8 valid; 3312}; 3313 3314/* hwrm_port_led_qcaps_input (size:192b/24B) */ 3315struct hwrm_port_led_qcaps_input { 3316 __le16 req_type; 3317 __le16 cmpl_ring; 3318 __le16 seq_id; 3319 __le16 target_id; 3320 __le64 resp_addr; 3321 __le16 port_id; 3322 u8 unused_0[6]; 3323}; 3324 3325/* hwrm_port_led_qcaps_output (size:384b/48B) */ 3326struct hwrm_port_led_qcaps_output { 3327 __le16 error_code; 3328 __le16 req_type; 3329 __le16 seq_id; 3330 __le16 resp_len; 3331 u8 num_leds; 3332 u8 unused[3]; 3333 u8 led0_id; 3334 u8 led0_type; 3335 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3336 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3337 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3338 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3339 u8 led0_group_id; 3340 u8 unused_0; 3341 __le16 led0_state_caps; 3342 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3343 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3344 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3345 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3346 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3347 __le16 led0_color_caps; 3348 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3349 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3350 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3351 u8 led1_id; 3352 u8 led1_type; 3353 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3354 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3355 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3356 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3357 u8 led1_group_id; 3358 u8 unused_1; 3359 __le16 led1_state_caps; 3360 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3361 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3362 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3363 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3364 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3365 __le16 led1_color_caps; 3366 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3367 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3368 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3369 u8 led2_id; 3370 u8 led2_type; 3371 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3372 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3373 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3374 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3375 u8 led2_group_id; 3376 u8 unused_2; 3377 __le16 led2_state_caps; 3378 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3379 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3380 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3381 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3382 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3383 __le16 led2_color_caps; 3384 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3385 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3386 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3387 u8 led3_id; 3388 u8 led3_type; 3389 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3390 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3391 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3392 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3393 u8 led3_group_id; 3394 u8 unused_3; 3395 __le16 led3_state_caps; 3396 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3397 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3398 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3399 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3400 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3401 __le16 led3_color_caps; 3402 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3403 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3404 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3405 u8 unused_4[3]; 3406 u8 valid; 3407}; 3408 3409/* hwrm_queue_qportcfg_input (size:192b/24B) */ 3410struct hwrm_queue_qportcfg_input { 3411 __le16 req_type; 3412 __le16 cmpl_ring; 3413 __le16 seq_id; 3414 __le16 target_id; 3415 __le64 resp_addr; 3416 __le32 flags; 3417 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3418 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3419 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3420 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3421 __le16 port_id; 3422 u8 drv_qmap_cap; 3423 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3424 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3425 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3426 u8 unused_0; 3427}; 3428 3429/* hwrm_queue_qportcfg_output (size:256b/32B) */ 3430struct hwrm_queue_qportcfg_output { 3431 __le16 error_code; 3432 __le16 req_type; 3433 __le16 seq_id; 3434 __le16 resp_len; 3435 u8 max_configurable_queues; 3436 u8 max_configurable_lossless_queues; 3437 u8 queue_cfg_allowed; 3438 u8 queue_cfg_info; 3439 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3440 u8 queue_pfcenable_cfg_allowed; 3441 u8 queue_pri2cos_cfg_allowed; 3442 u8 queue_cos2bw_cfg_allowed; 3443 u8 queue_id0; 3444 u8 queue_id0_service_profile; 3445 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3446 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3447 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3448 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3449 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3450 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3451 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3452 u8 queue_id1; 3453 u8 queue_id1_service_profile; 3454 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3455 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3456 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3457 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3458 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3459 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3460 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3461 u8 queue_id2; 3462 u8 queue_id2_service_profile; 3463 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3464 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3465 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3466 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3467 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3468 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3469 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3470 u8 queue_id3; 3471 u8 queue_id3_service_profile; 3472 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3473 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3474 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3475 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3476 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3477 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3478 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3479 u8 queue_id4; 3480 u8 queue_id4_service_profile; 3481 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3482 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3483 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3484 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3485 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3486 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3487 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3488 u8 queue_id5; 3489 u8 queue_id5_service_profile; 3490 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3491 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3492 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3493 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3494 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3495 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3496 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3497 u8 queue_id6; 3498 u8 queue_id6_service_profile; 3499 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3500 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3501 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3502 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3503 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3504 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3505 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3506 u8 queue_id7; 3507 u8 queue_id7_service_profile; 3508 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3509 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3510 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3511 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3512 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3513 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3514 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3515 u8 valid; 3516}; 3517 3518/* hwrm_queue_cfg_input (size:320b/40B) */ 3519struct hwrm_queue_cfg_input { 3520 __le16 req_type; 3521 __le16 cmpl_ring; 3522 __le16 seq_id; 3523 __le16 target_id; 3524 __le64 resp_addr; 3525 __le32 flags; 3526 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3527 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3528 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3529 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3530 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3531 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3532 __le32 enables; 3533 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3534 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3535 __le32 queue_id; 3536 __le32 dflt_len; 3537 u8 service_profile; 3538 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3539 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3540 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3541 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3542 u8 unused_0[7]; 3543}; 3544 3545/* hwrm_queue_cfg_output (size:128b/16B) */ 3546struct hwrm_queue_cfg_output { 3547 __le16 error_code; 3548 __le16 req_type; 3549 __le16 seq_id; 3550 __le16 resp_len; 3551 u8 unused_0[7]; 3552 u8 valid; 3553}; 3554 3555/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3556struct hwrm_queue_pfcenable_qcfg_input { 3557 __le16 req_type; 3558 __le16 cmpl_ring; 3559 __le16 seq_id; 3560 __le16 target_id; 3561 __le64 resp_addr; 3562 __le16 port_id; 3563 u8 unused_0[6]; 3564}; 3565 3566/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3567struct hwrm_queue_pfcenable_qcfg_output { 3568 __le16 error_code; 3569 __le16 req_type; 3570 __le16 seq_id; 3571 __le16 resp_len; 3572 __le32 flags; 3573 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3574 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3575 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3576 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3577 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3578 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3579 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3580 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3581 u8 unused_0[3]; 3582 u8 valid; 3583}; 3584 3585/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3586struct hwrm_queue_pfcenable_cfg_input { 3587 __le16 req_type; 3588 __le16 cmpl_ring; 3589 __le16 seq_id; 3590 __le16 target_id; 3591 __le64 resp_addr; 3592 __le32 flags; 3593 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3594 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3595 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3596 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3597 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3598 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3599 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3600 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3601 __le16 port_id; 3602 u8 unused_0[2]; 3603}; 3604 3605/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 3606struct hwrm_queue_pfcenable_cfg_output { 3607 __le16 error_code; 3608 __le16 req_type; 3609 __le16 seq_id; 3610 __le16 resp_len; 3611 u8 unused_0[7]; 3612 u8 valid; 3613}; 3614 3615/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 3616struct hwrm_queue_pri2cos_qcfg_input { 3617 __le16 req_type; 3618 __le16 cmpl_ring; 3619 __le16 seq_id; 3620 __le16 target_id; 3621 __le64 resp_addr; 3622 __le32 flags; 3623 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 3624 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 3625 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 3626 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 3627 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 3628 u8 port_id; 3629 u8 unused_0[3]; 3630}; 3631 3632/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 3633struct hwrm_queue_pri2cos_qcfg_output { 3634 __le16 error_code; 3635 __le16 req_type; 3636 __le16 seq_id; 3637 __le16 resp_len; 3638 u8 pri0_cos_queue_id; 3639 u8 pri1_cos_queue_id; 3640 u8 pri2_cos_queue_id; 3641 u8 pri3_cos_queue_id; 3642 u8 pri4_cos_queue_id; 3643 u8 pri5_cos_queue_id; 3644 u8 pri6_cos_queue_id; 3645 u8 pri7_cos_queue_id; 3646 u8 queue_cfg_info; 3647 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3648 u8 unused_0[6]; 3649 u8 valid; 3650}; 3651 3652/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 3653struct hwrm_queue_pri2cos_cfg_input { 3654 __le16 req_type; 3655 __le16 cmpl_ring; 3656 __le16 seq_id; 3657 __le16 target_id; 3658 __le64 resp_addr; 3659 __le32 flags; 3660 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3661 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 3662 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 3663 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 3664 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3665 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 3666 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 3667 __le32 enables; 3668 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 3669 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 3670 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 3671 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 3672 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 3673 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 3674 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 3675 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 3676 u8 port_id; 3677 u8 pri0_cos_queue_id; 3678 u8 pri1_cos_queue_id; 3679 u8 pri2_cos_queue_id; 3680 u8 pri3_cos_queue_id; 3681 u8 pri4_cos_queue_id; 3682 u8 pri5_cos_queue_id; 3683 u8 pri6_cos_queue_id; 3684 u8 pri7_cos_queue_id; 3685 u8 unused_0[7]; 3686}; 3687 3688/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 3689struct hwrm_queue_pri2cos_cfg_output { 3690 __le16 error_code; 3691 __le16 req_type; 3692 __le16 seq_id; 3693 __le16 resp_len; 3694 u8 unused_0[7]; 3695 u8 valid; 3696}; 3697 3698/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 3699struct hwrm_queue_cos2bw_qcfg_input { 3700 __le16 req_type; 3701 __le16 cmpl_ring; 3702 __le16 seq_id; 3703 __le16 target_id; 3704 __le64 resp_addr; 3705 __le16 port_id; 3706 u8 unused_0[6]; 3707}; 3708 3709/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 3710struct hwrm_queue_cos2bw_qcfg_output { 3711 __le16 error_code; 3712 __le16 req_type; 3713 __le16 seq_id; 3714 __le16 resp_len; 3715 u8 queue_id0; 3716 u8 unused_0; 3717 __le16 unused_1; 3718 __le32 queue_id0_min_bw; 3719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 3725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3734 __le32 queue_id0_max_bw; 3735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 3741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3750 u8 queue_id0_tsa_assign; 3751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3755 u8 queue_id0_pri_lvl; 3756 u8 queue_id0_bw_weight; 3757 u8 queue_id1; 3758 __le32 queue_id1_min_bw; 3759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 3765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3774 __le32 queue_id1_max_bw; 3775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 3781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3790 u8 queue_id1_tsa_assign; 3791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3795 u8 queue_id1_pri_lvl; 3796 u8 queue_id1_bw_weight; 3797 u8 queue_id2; 3798 __le32 queue_id2_min_bw; 3799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 3805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3814 __le32 queue_id2_max_bw; 3815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 3821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3830 u8 queue_id2_tsa_assign; 3831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3835 u8 queue_id2_pri_lvl; 3836 u8 queue_id2_bw_weight; 3837 u8 queue_id3; 3838 __le32 queue_id3_min_bw; 3839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 3845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3854 __le32 queue_id3_max_bw; 3855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 3861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3870 u8 queue_id3_tsa_assign; 3871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3875 u8 queue_id3_pri_lvl; 3876 u8 queue_id3_bw_weight; 3877 u8 queue_id4; 3878 __le32 queue_id4_min_bw; 3879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 3885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3894 __le32 queue_id4_max_bw; 3895 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 3901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3910 u8 queue_id4_tsa_assign; 3911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3915 u8 queue_id4_pri_lvl; 3916 u8 queue_id4_bw_weight; 3917 u8 queue_id5; 3918 __le32 queue_id5_min_bw; 3919 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 3925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3934 __le32 queue_id5_max_bw; 3935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 3941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3950 u8 queue_id5_tsa_assign; 3951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3955 u8 queue_id5_pri_lvl; 3956 u8 queue_id5_bw_weight; 3957 u8 queue_id6; 3958 __le32 queue_id6_min_bw; 3959 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 3965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3974 __le32 queue_id6_max_bw; 3975 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 3981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3990 u8 queue_id6_tsa_assign; 3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3995 u8 queue_id6_pri_lvl; 3996 u8 queue_id6_bw_weight; 3997 u8 queue_id7; 3998 __le32 queue_id7_min_bw; 3999 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4014 __le32 queue_id7_max_bw; 4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4030 u8 queue_id7_tsa_assign; 4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4035 u8 queue_id7_pri_lvl; 4036 u8 queue_id7_bw_weight; 4037 u8 unused_2[4]; 4038 u8 valid; 4039}; 4040 4041/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4042struct hwrm_queue_cos2bw_cfg_input { 4043 __le16 req_type; 4044 __le16 cmpl_ring; 4045 __le16 seq_id; 4046 __le16 target_id; 4047 __le64 resp_addr; 4048 __le32 flags; 4049 __le32 enables; 4050 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4051 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4052 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4053 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4054 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4055 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4056 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4057 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4058 __le16 port_id; 4059 u8 queue_id0; 4060 u8 unused_0; 4061 __le32 queue_id0_min_bw; 4062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4077 __le32 queue_id0_max_bw; 4078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4093 u8 queue_id0_tsa_assign; 4094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4098 u8 queue_id0_pri_lvl; 4099 u8 queue_id0_bw_weight; 4100 u8 queue_id1; 4101 __le32 queue_id1_min_bw; 4102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4117 __le32 queue_id1_max_bw; 4118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4133 u8 queue_id1_tsa_assign; 4134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4138 u8 queue_id1_pri_lvl; 4139 u8 queue_id1_bw_weight; 4140 u8 queue_id2; 4141 __le32 queue_id2_min_bw; 4142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4157 __le32 queue_id2_max_bw; 4158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4173 u8 queue_id2_tsa_assign; 4174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4178 u8 queue_id2_pri_lvl; 4179 u8 queue_id2_bw_weight; 4180 u8 queue_id3; 4181 __le32 queue_id3_min_bw; 4182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4197 __le32 queue_id3_max_bw; 4198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4213 u8 queue_id3_tsa_assign; 4214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4218 u8 queue_id3_pri_lvl; 4219 u8 queue_id3_bw_weight; 4220 u8 queue_id4; 4221 __le32 queue_id4_min_bw; 4222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4237 __le32 queue_id4_max_bw; 4238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4253 u8 queue_id4_tsa_assign; 4254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4258 u8 queue_id4_pri_lvl; 4259 u8 queue_id4_bw_weight; 4260 u8 queue_id5; 4261 __le32 queue_id5_min_bw; 4262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4277 __le32 queue_id5_max_bw; 4278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4293 u8 queue_id5_tsa_assign; 4294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4298 u8 queue_id5_pri_lvl; 4299 u8 queue_id5_bw_weight; 4300 u8 queue_id6; 4301 __le32 queue_id6_min_bw; 4302 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4317 __le32 queue_id6_max_bw; 4318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4333 u8 queue_id6_tsa_assign; 4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4338 u8 queue_id6_pri_lvl; 4339 u8 queue_id6_bw_weight; 4340 u8 queue_id7; 4341 __le32 queue_id7_min_bw; 4342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4357 __le32 queue_id7_max_bw; 4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4373 u8 queue_id7_tsa_assign; 4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4378 u8 queue_id7_pri_lvl; 4379 u8 queue_id7_bw_weight; 4380 u8 unused_1[5]; 4381}; 4382 4383/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4384struct hwrm_queue_cos2bw_cfg_output { 4385 __le16 error_code; 4386 __le16 req_type; 4387 __le16 seq_id; 4388 __le16 resp_len; 4389 u8 unused_0[7]; 4390 u8 valid; 4391}; 4392 4393/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4394struct hwrm_queue_dscp_qcaps_input { 4395 __le16 req_type; 4396 __le16 cmpl_ring; 4397 __le16 seq_id; 4398 __le16 target_id; 4399 __le64 resp_addr; 4400 u8 port_id; 4401 u8 unused_0[7]; 4402}; 4403 4404/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4405struct hwrm_queue_dscp_qcaps_output { 4406 __le16 error_code; 4407 __le16 req_type; 4408 __le16 seq_id; 4409 __le16 resp_len; 4410 u8 num_dscp_bits; 4411 u8 unused_0; 4412 __le16 max_entries; 4413 u8 unused_1[3]; 4414 u8 valid; 4415}; 4416 4417/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4418struct hwrm_queue_dscp2pri_qcfg_input { 4419 __le16 req_type; 4420 __le16 cmpl_ring; 4421 __le16 seq_id; 4422 __le16 target_id; 4423 __le64 resp_addr; 4424 __le64 dest_data_addr; 4425 u8 port_id; 4426 u8 unused_0; 4427 __le16 dest_data_buffer_size; 4428 u8 unused_1[4]; 4429}; 4430 4431/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4432struct hwrm_queue_dscp2pri_qcfg_output { 4433 __le16 error_code; 4434 __le16 req_type; 4435 __le16 seq_id; 4436 __le16 resp_len; 4437 __le16 entry_cnt; 4438 u8 default_pri; 4439 u8 unused_0[4]; 4440 u8 valid; 4441}; 4442 4443/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4444struct hwrm_queue_dscp2pri_cfg_input { 4445 __le16 req_type; 4446 __le16 cmpl_ring; 4447 __le16 seq_id; 4448 __le16 target_id; 4449 __le64 resp_addr; 4450 __le64 src_data_addr; 4451 __le32 flags; 4452 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4453 __le32 enables; 4454 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4455 u8 port_id; 4456 u8 default_pri; 4457 __le16 entry_cnt; 4458 u8 unused_0[4]; 4459}; 4460 4461/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4462struct hwrm_queue_dscp2pri_cfg_output { 4463 __le16 error_code; 4464 __le16 req_type; 4465 __le16 seq_id; 4466 __le16 resp_len; 4467 u8 unused_0[7]; 4468 u8 valid; 4469}; 4470 4471/* hwrm_vnic_alloc_input (size:192b/24B) */ 4472struct hwrm_vnic_alloc_input { 4473 __le16 req_type; 4474 __le16 cmpl_ring; 4475 __le16 seq_id; 4476 __le16 target_id; 4477 __le64 resp_addr; 4478 __le32 flags; 4479 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4480 u8 unused_0[4]; 4481}; 4482 4483/* hwrm_vnic_alloc_output (size:128b/16B) */ 4484struct hwrm_vnic_alloc_output { 4485 __le16 error_code; 4486 __le16 req_type; 4487 __le16 seq_id; 4488 __le16 resp_len; 4489 __le32 vnic_id; 4490 u8 unused_0[3]; 4491 u8 valid; 4492}; 4493 4494/* hwrm_vnic_free_input (size:192b/24B) */ 4495struct hwrm_vnic_free_input { 4496 __le16 req_type; 4497 __le16 cmpl_ring; 4498 __le16 seq_id; 4499 __le16 target_id; 4500 __le64 resp_addr; 4501 __le32 vnic_id; 4502 u8 unused_0[4]; 4503}; 4504 4505/* hwrm_vnic_free_output (size:128b/16B) */ 4506struct hwrm_vnic_free_output { 4507 __le16 error_code; 4508 __le16 req_type; 4509 __le16 seq_id; 4510 __le16 resp_len; 4511 u8 unused_0[7]; 4512 u8 valid; 4513}; 4514 4515/* hwrm_vnic_cfg_input (size:320b/40B) */ 4516struct hwrm_vnic_cfg_input { 4517 __le16 req_type; 4518 __le16 cmpl_ring; 4519 __le16 seq_id; 4520 __le16 target_id; 4521 __le64 resp_addr; 4522 __le32 flags; 4523 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4524 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4525 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4526 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4527 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4528 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4529 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4530 __le32 enables; 4531 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4532 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4533 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4534 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4535 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4536 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4537 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4538 __le16 vnic_id; 4539 __le16 dflt_ring_grp; 4540 __le16 rss_rule; 4541 __le16 cos_rule; 4542 __le16 lb_rule; 4543 __le16 mru; 4544 __le16 default_rx_ring_id; 4545 __le16 default_cmpl_ring_id; 4546}; 4547 4548/* hwrm_vnic_cfg_output (size:128b/16B) */ 4549struct hwrm_vnic_cfg_output { 4550 __le16 error_code; 4551 __le16 req_type; 4552 __le16 seq_id; 4553 __le16 resp_len; 4554 u8 unused_0[7]; 4555 u8 valid; 4556}; 4557 4558/* hwrm_vnic_qcaps_input (size:192b/24B) */ 4559struct hwrm_vnic_qcaps_input { 4560 __le16 req_type; 4561 __le16 cmpl_ring; 4562 __le16 seq_id; 4563 __le16 target_id; 4564 __le64 resp_addr; 4565 __le32 enables; 4566 u8 unused_0[4]; 4567}; 4568 4569/* hwrm_vnic_qcaps_output (size:192b/24B) */ 4570struct hwrm_vnic_qcaps_output { 4571 __le16 error_code; 4572 __le16 req_type; 4573 __le16 seq_id; 4574 __le16 resp_len; 4575 __le16 mru; 4576 u8 unused_0[2]; 4577 __le32 flags; 4578 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4579 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4580 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4581 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4582 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4583 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4584 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4585 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4586 u8 unused_1[7]; 4587 u8 valid; 4588}; 4589 4590/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4591struct hwrm_vnic_tpa_cfg_input { 4592 __le16 req_type; 4593 __le16 cmpl_ring; 4594 __le16 seq_id; 4595 __le16 target_id; 4596 __le64 resp_addr; 4597 __le32 flags; 4598 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 4599 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 4600 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 4601 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 4602 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 4603 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4604 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 4605 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 4606 __le32 enables; 4607 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 4608 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 4609 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 4610 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 4611 __le16 vnic_id; 4612 __le16 max_agg_segs; 4613 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 4614 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 4615 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 4616 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 4617 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 4618 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 4619 __le16 max_aggs; 4620 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 4621 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 4622 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 4623 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 4624 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 4625 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 4626 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 4627 u8 unused_0[2]; 4628 __le32 max_agg_timer; 4629 __le32 min_agg_len; 4630}; 4631 4632/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 4633struct hwrm_vnic_tpa_cfg_output { 4634 __le16 error_code; 4635 __le16 req_type; 4636 __le16 seq_id; 4637 __le16 resp_len; 4638 u8 unused_0[7]; 4639 u8 valid; 4640}; 4641 4642/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 4643struct hwrm_vnic_tpa_qcfg_input { 4644 __le16 req_type; 4645 __le16 cmpl_ring; 4646 __le16 seq_id; 4647 __le16 target_id; 4648 __le64 resp_addr; 4649 __le16 vnic_id; 4650 u8 unused_0[6]; 4651}; 4652 4653/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 4654struct hwrm_vnic_tpa_qcfg_output { 4655 __le16 error_code; 4656 __le16 req_type; 4657 __le16 seq_id; 4658 __le16 resp_len; 4659 __le32 flags; 4660 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 4661 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 4662 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 4663 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 4664 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 4665 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4666 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 4667 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 4668 __le16 max_agg_segs; 4669 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 4670 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 4671 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 4672 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 4673 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 4674 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 4675 __le16 max_aggs; 4676 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 4677 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 4678 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 4679 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 4680 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 4681 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 4682 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 4683 __le32 max_agg_timer; 4684 __le32 min_agg_len; 4685 u8 unused_0[7]; 4686 u8 valid; 4687}; 4688 4689/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 4690struct hwrm_vnic_rss_cfg_input { 4691 __le16 req_type; 4692 __le16 cmpl_ring; 4693 __le16 seq_id; 4694 __le16 target_id; 4695 __le64 resp_addr; 4696 __le32 hash_type; 4697 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 4698 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 4699 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 4700 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4701 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4702 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4703 __le16 vnic_id; 4704 u8 ring_table_pair_index; 4705 u8 hash_mode_flags; 4706 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 4707 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 4708 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 4709 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 4710 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 4711 __le64 ring_grp_tbl_addr; 4712 __le64 hash_key_tbl_addr; 4713 __le16 rss_ctx_idx; 4714 u8 unused_1[6]; 4715}; 4716 4717/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 4718struct hwrm_vnic_rss_cfg_output { 4719 __le16 error_code; 4720 __le16 req_type; 4721 __le16 seq_id; 4722 __le16 resp_len; 4723 u8 unused_0[7]; 4724 u8 valid; 4725}; 4726 4727/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 4728struct hwrm_vnic_plcmodes_cfg_input { 4729 __le16 req_type; 4730 __le16 cmpl_ring; 4731 __le16 seq_id; 4732 __le16 target_id; 4733 __le64 resp_addr; 4734 __le32 flags; 4735 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 4736 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 4737 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 4738 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 4739 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 4740 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 4741 __le32 enables; 4742 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 4743 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 4744 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 4745 __le32 vnic_id; 4746 __le16 jumbo_thresh; 4747 __le16 hds_offset; 4748 __le16 hds_threshold; 4749 u8 unused_0[6]; 4750}; 4751 4752/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 4753struct hwrm_vnic_plcmodes_cfg_output { 4754 __le16 error_code; 4755 __le16 req_type; 4756 __le16 seq_id; 4757 __le16 resp_len; 4758 u8 unused_0[7]; 4759 u8 valid; 4760}; 4761 4762/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 4763struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 4764 __le16 req_type; 4765 __le16 cmpl_ring; 4766 __le16 seq_id; 4767 __le16 target_id; 4768 __le64 resp_addr; 4769}; 4770 4771/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 4772struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 4773 __le16 error_code; 4774 __le16 req_type; 4775 __le16 seq_id; 4776 __le16 resp_len; 4777 __le16 rss_cos_lb_ctx_id; 4778 u8 unused_0[5]; 4779 u8 valid; 4780}; 4781 4782/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 4783struct hwrm_vnic_rss_cos_lb_ctx_free_input { 4784 __le16 req_type; 4785 __le16 cmpl_ring; 4786 __le16 seq_id; 4787 __le16 target_id; 4788 __le64 resp_addr; 4789 __le16 rss_cos_lb_ctx_id; 4790 u8 unused_0[6]; 4791}; 4792 4793/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 4794struct hwrm_vnic_rss_cos_lb_ctx_free_output { 4795 __le16 error_code; 4796 __le16 req_type; 4797 __le16 seq_id; 4798 __le16 resp_len; 4799 u8 unused_0[7]; 4800 u8 valid; 4801}; 4802 4803/* hwrm_ring_alloc_input (size:704b/88B) */ 4804struct hwrm_ring_alloc_input { 4805 __le16 req_type; 4806 __le16 cmpl_ring; 4807 __le16 seq_id; 4808 __le16 target_id; 4809 __le64 resp_addr; 4810 __le32 enables; 4811 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 4812 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 4813 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 4814 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 4815 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 4816 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 4817 u8 ring_type; 4818 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 4819 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 4820 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 4821 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4822 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 4823 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 4824 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 4825 u8 unused_0; 4826 __le16 flags; 4827 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 4828 __le64 page_tbl_addr; 4829 __le32 fbo; 4830 u8 page_size; 4831 u8 page_tbl_depth; 4832 u8 unused_1[2]; 4833 __le32 length; 4834 __le16 logical_id; 4835 __le16 cmpl_ring_id; 4836 __le16 queue_id; 4837 __le16 rx_buf_size; 4838 __le16 rx_ring_id; 4839 __le16 nq_ring_id; 4840 __le16 ring_arb_cfg; 4841 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 4842 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 4843 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 4844 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 4845 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 4846 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 4847 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 4848 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 4849 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 4850 __le16 unused_3; 4851 __le32 reserved3; 4852 __le32 stat_ctx_id; 4853 __le32 reserved4; 4854 __le32 max_bw; 4855 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4856 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 4857 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 4858 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 4859 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 4860 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 4861 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4862 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 4863 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4864 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4865 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4866 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4867 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4868 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4869 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 4870 u8 int_mode; 4871 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 4872 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 4873 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 4874 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 4875 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 4876 u8 unused_4[3]; 4877 __le64 cq_handle; 4878}; 4879 4880/* hwrm_ring_alloc_output (size:128b/16B) */ 4881struct hwrm_ring_alloc_output { 4882 __le16 error_code; 4883 __le16 req_type; 4884 __le16 seq_id; 4885 __le16 resp_len; 4886 __le16 ring_id; 4887 __le16 logical_ring_id; 4888 u8 unused_0[3]; 4889 u8 valid; 4890}; 4891 4892/* hwrm_ring_free_input (size:192b/24B) */ 4893struct hwrm_ring_free_input { 4894 __le16 req_type; 4895 __le16 cmpl_ring; 4896 __le16 seq_id; 4897 __le16 target_id; 4898 __le64 resp_addr; 4899 u8 ring_type; 4900 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 4901 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 4902 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 4903 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4904 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 4905 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 4906 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 4907 u8 unused_0; 4908 __le16 ring_id; 4909 u8 unused_1[4]; 4910}; 4911 4912/* hwrm_ring_free_output (size:128b/16B) */ 4913struct hwrm_ring_free_output { 4914 __le16 error_code; 4915 __le16 req_type; 4916 __le16 seq_id; 4917 __le16 resp_len; 4918 u8 unused_0[7]; 4919 u8 valid; 4920}; 4921 4922/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 4923struct hwrm_ring_aggint_qcaps_input { 4924 __le16 req_type; 4925 __le16 cmpl_ring; 4926 __le16 seq_id; 4927 __le16 target_id; 4928 __le64 resp_addr; 4929}; 4930 4931/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 4932struct hwrm_ring_aggint_qcaps_output { 4933 __le16 error_code; 4934 __le16 req_type; 4935 __le16 seq_id; 4936 __le16 resp_len; 4937 __le32 cmpl_params; 4938 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 4939 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 4940 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 4941 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 4942 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 4943 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 4944 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 4945 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 4946 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 4947 __le32 nq_params; 4948 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 4949 __le16 num_cmpl_dma_aggr_min; 4950 __le16 num_cmpl_dma_aggr_max; 4951 __le16 num_cmpl_dma_aggr_during_int_min; 4952 __le16 num_cmpl_dma_aggr_during_int_max; 4953 __le16 cmpl_aggr_dma_tmr_min; 4954 __le16 cmpl_aggr_dma_tmr_max; 4955 __le16 cmpl_aggr_dma_tmr_during_int_min; 4956 __le16 cmpl_aggr_dma_tmr_during_int_max; 4957 __le16 int_lat_tmr_min_min; 4958 __le16 int_lat_tmr_min_max; 4959 __le16 int_lat_tmr_max_min; 4960 __le16 int_lat_tmr_max_max; 4961 __le16 num_cmpl_aggr_int_min; 4962 __le16 num_cmpl_aggr_int_max; 4963 __le16 timer_units; 4964 u8 unused_0[1]; 4965 u8 valid; 4966}; 4967 4968/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 4969struct hwrm_ring_cmpl_ring_qaggint_params_input { 4970 __le16 req_type; 4971 __le16 cmpl_ring; 4972 __le16 seq_id; 4973 __le16 target_id; 4974 __le64 resp_addr; 4975 __le16 ring_id; 4976 u8 unused_0[6]; 4977}; 4978 4979/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 4980struct hwrm_ring_cmpl_ring_qaggint_params_output { 4981 __le16 error_code; 4982 __le16 req_type; 4983 __le16 seq_id; 4984 __le16 resp_len; 4985 __le16 flags; 4986 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 4987 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 4988 __le16 num_cmpl_dma_aggr; 4989 __le16 num_cmpl_dma_aggr_during_int; 4990 __le16 cmpl_aggr_dma_tmr; 4991 __le16 cmpl_aggr_dma_tmr_during_int; 4992 __le16 int_lat_tmr_min; 4993 __le16 int_lat_tmr_max; 4994 __le16 num_cmpl_aggr_int; 4995 u8 unused_0[7]; 4996 u8 valid; 4997}; 4998 4999/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5000struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
5001 __le16 req_type; 5002 __le16 cmpl_ring; 5003 __le16 seq_id; 5004 __le16 target_id; 5005 __le64 resp_addr; 5006 __le16 ring_id; 5007 __le16 flags; 5008 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5009 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5010 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5011 __le16 num_cmpl_dma_aggr; 5012 __le16 num_cmpl_dma_aggr_during_int; 5013 __le16 cmpl_aggr_dma_tmr; 5014 __le16 cmpl_aggr_dma_tmr_during_int; 5015 __le16 int_lat_tmr_min; 5016 __le16 int_lat_tmr_max; 5017 __le16 num_cmpl_aggr_int; 5018 __le16 enables; 5019 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5020 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5021 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5022 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5023 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5024 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5025 u8 unused_0[4]; 5026}; 5027 5028/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5029struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5030 __le16 error_code; 5031 __le16 req_type; 5032 __le16 seq_id; 5033 __le16 resp_len; 5034 u8 unused_0[7]; 5035 u8 valid; 5036}; 5037 5038/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5039struct hwrm_ring_grp_alloc_input { 5040 __le16 req_type; 5041 __le16 cmpl_ring; 5042 __le16 seq_id; 5043 __le16 target_id; 5044 __le64 resp_addr; 5045 __le16 cr; 5046 __le16 rr; 5047 __le16 ar; 5048 __le16 sc; 5049}; 5050 5051/* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5052struct hwrm_ring_grp_alloc_output { 5053 __le16 error_code; 5054 __le16 req_type; 5055 __le16 seq_id; 5056 __le16 resp_len; 5057 __le32 ring_group_id; 5058 u8 unused_0[3]; 5059 u8 valid; 5060}; 5061 5062/* hwrm_ring_grp_free_input (size:192b/24B) */ 5063struct hwrm_ring_grp_free_input { 5064 __le16 req_type; 5065 __le16 cmpl_ring; 5066 __le16 seq_id; 5067 __le16 target_id; 5068 __le64 resp_addr; 5069 __le32 ring_group_id; 5070 u8 unused_0[4]; 5071}; 5072 5073/* hwrm_ring_grp_free_output (size:128b/16B) */ 5074struct hwrm_ring_grp_free_output { 5075 __le16 error_code; 5076 __le16 req_type; 5077 __le16 seq_id; 5078 __le16 resp_len; 5079 u8 unused_0[7]; 5080 u8 valid; 5081}; 5082#define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5083#define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5084#define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5085#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5086 5087/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5088struct hwrm_cfa_l2_filter_alloc_input { 5089 __le16 req_type; 5090 __le16 cmpl_ring; 5091 __le16 seq_id; 5092 __le16 target_id; 5093 __le64 resp_addr; 5094 __le32 flags; 5095 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5096 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5097 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5098 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5099 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5100 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5101 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5102 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5103 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5104 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5105 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5106 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5107 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5108 __le32 enables; 5109 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5110 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5111 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5112 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5113 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5114 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5115 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5116 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5117 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5118 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5119 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5120 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5121 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5122 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5123 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5124 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5125 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5126 u8 l2_addr[6]; 5127 u8 unused_0[2]; 5128 u8 l2_addr_mask[6]; 5129 __le16 l2_ovlan; 5130 __le16 l2_ovlan_mask; 5131 __le16 l2_ivlan; 5132 __le16 l2_ivlan_mask; 5133 u8 unused_1[2]; 5134 u8 t_l2_addr[6]; 5135 u8 unused_2[2]; 5136 u8 t_l2_addr_mask[6]; 5137 __le16 t_l2_ovlan; 5138 __le16 t_l2_ovlan_mask; 5139 __le16 t_l2_ivlan; 5140 __le16 t_l2_ivlan_mask; 5141 u8 src_type; 5142 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5143 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5144 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5145 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5146 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5147 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5148 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5149 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5150 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5151 u8 unused_3; 5152 __le32 src_id; 5153 u8 tunnel_type; 5154 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5155 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5156 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5157 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5158 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5159 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5160 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5161 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5162 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5163 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5164 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5165 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5166 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5167 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5168 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5169 u8 unused_4; 5170 __le16 dst_id; 5171 __le16 mirror_vnic_id; 5172 u8 pri_hint; 5173 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5174 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5175 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5176 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5177 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5178 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5179 u8 unused_5; 5180 __le32 unused_6; 5181 __le64 l2_filter_id_hint; 5182}; 5183 5184/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5185struct hwrm_cfa_l2_filter_alloc_output { 5186 __le16 error_code; 5187 __le16 req_type; 5188 __le16 seq_id; 5189 __le16 resp_len; 5190 __le64 l2_filter_id; 5191 __le32 flow_id; 5192 u8 unused_0[3]; 5193 u8 valid; 5194}; 5195 5196/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5197struct hwrm_cfa_l2_filter_free_input { 5198 __le16 req_type; 5199 __le16 cmpl_ring; 5200 __le16 seq_id; 5201 __le16 target_id; 5202 __le64 resp_addr; 5203 __le64 l2_filter_id; 5204}; 5205 5206/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5207struct hwrm_cfa_l2_filter_free_output { 5208 __le16 error_code; 5209 __le16 req_type; 5210 __le16 seq_id; 5211 __le16 resp_len; 5212 u8 unused_0[7]; 5213 u8 valid; 5214}; 5215 5216/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5217struct hwrm_cfa_l2_filter_cfg_input { 5218 __le16 req_type; 5219 __le16 cmpl_ring; 5220 __le16 seq_id; 5221 __le16 target_id; 5222 __le64 resp_addr; 5223 __le32 flags; 5224 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5225 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5226 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5227 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5228 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5229 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5230 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5231 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5232 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5233 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5234 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5235 __le32 enables; 5236 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5237 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5238 __le64 l2_filter_id; 5239 __le32 dst_id; 5240 __le32 new_mirror_vnic_id; 5241}; 5242 5243/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5244struct hwrm_cfa_l2_filter_cfg_output { 5245 __le16 error_code; 5246 __le16 req_type; 5247 __le16 seq_id; 5248 __le16 resp_len; 5249 u8 unused_0[7]; 5250 u8 valid; 5251}; 5252 5253/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5254struct hwrm_cfa_l2_set_rx_mask_input { 5255 __le16 req_type; 5256 __le16 cmpl_ring; 5257 __le16 seq_id; 5258 __le16 target_id; 5259 __le64 resp_addr; 5260 __le32 vnic_id; 5261 __le32 mask; 5262 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5263 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5264 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5265 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5266 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5267 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5268 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5269 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5270 __le64 mc_tbl_addr; 5271 __le32 num_mc_entries; 5272 u8 unused_0[4]; 5273 __le64 vlan_tag_tbl_addr; 5274 __le32 num_vlan_tags; 5275 u8 unused_1[4]; 5276}; 5277 5278/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5279struct hwrm_cfa_l2_set_rx_mask_output { 5280 __le16 error_code; 5281 __le16 req_type; 5282 __le16 seq_id; 5283 __le16 resp_len; 5284 u8 unused_0[7]; 5285 u8 valid; 5286}; 5287 5288/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5289struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5290 u8 code; 5291 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5292 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5293 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5294 u8 unused_0[7]; 5295}; 5296 5297/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5298struct hwrm_cfa_tunnel_filter_alloc_input { 5299 __le16 req_type; 5300 __le16 cmpl_ring; 5301 __le16 seq_id; 5302 __le16 target_id; 5303 __le64 resp_addr; 5304 __le32 flags; 5305 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5306 __le32 enables; 5307 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5308 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5309 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5310 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5311 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5312 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5313 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5314 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5315 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5316 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5317 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5318 __le64 l2_filter_id; 5319 u8 l2_addr[6]; 5320 __le16 l2_ivlan; 5321 __le32 l3_addr[4]; 5322 __le32 t_l3_addr[4]; 5323 u8 l3_addr_type; 5324 u8 t_l3_addr_type; 5325 u8 tunnel_type; 5326 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5327 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5328 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5329 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5330 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5331 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5332 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5333 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5334 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5335 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5336 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5337 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5338 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5339 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5340 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5341 u8 tunnel_flags; 5342 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5343 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5344 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5345 __le32 vni; 5346 __le32 dst_vnic_id; 5347 __le32 mirror_vnic_id; 5348}; 5349 5350/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5351struct hwrm_cfa_tunnel_filter_alloc_output { 5352 __le16 error_code; 5353 __le16 req_type; 5354 __le16 seq_id; 5355 __le16 resp_len; 5356 __le64 tunnel_filter_id; 5357 __le32 flow_id; 5358 u8 unused_0[3]; 5359 u8 valid; 5360}; 5361 5362/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5363struct hwrm_cfa_tunnel_filter_free_input { 5364 __le16 req_type; 5365 __le16 cmpl_ring; 5366 __le16 seq_id; 5367 __le16 target_id; 5368 __le64 resp_addr; 5369 __le64 tunnel_filter_id; 5370}; 5371 5372/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5373struct hwrm_cfa_tunnel_filter_free_output { 5374 __le16 error_code; 5375 __le16 req_type; 5376 __le16 seq_id; 5377 __le16 resp_len; 5378 u8 unused_0[7]; 5379 u8 valid; 5380}; 5381 5382/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5383struct hwrm_vxlan_ipv4_hdr { 5384 u8 ver_hlen; 5385 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5386 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5387 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5388 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5389 u8 tos; 5390 __be16 ip_id; 5391 __be16 flags_frag_offset; 5392 u8 ttl; 5393 u8 protocol; 5394 __be32 src_ip_addr; 5395 __be32 dest_ip_addr; 5396}; 5397 5398/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5399struct hwrm_vxlan_ipv6_hdr { 5400 __be32 ver_tc_flow_label; 5401 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5402 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5403 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5404 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5405 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5406 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5407 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5408 __be16 payload_len; 5409 u8 next_hdr; 5410 u8 ttl; 5411 __be32 src_ip_addr[4]; 5412 __be32 dest_ip_addr[4]; 5413}; 5414 5415/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5416struct hwrm_cfa_encap_data_vxlan { 5417 u8 src_mac_addr[6]; 5418 __le16 unused_0; 5419 u8 dst_mac_addr[6]; 5420 u8 num_vlan_tags; 5421 u8 unused_1; 5422 __be16 ovlan_tpid; 5423 __be16 ovlan_tci; 5424 __be16 ivlan_tpid; 5425 __be16 ivlan_tci; 5426 __le32 l3[10]; 5427 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5428 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5429 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5430 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5431 __be16 src_port; 5432 __be16 dst_port; 5433 __be32 vni; 5434 u8 hdr_rsvd0[3]; 5435 u8 hdr_rsvd1; 5436 u8 hdr_flags; 5437 u8 unused[3]; 5438}; 5439 5440/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5441struct hwrm_cfa_encap_record_alloc_input { 5442 __le16 req_type; 5443 __le16 cmpl_ring; 5444 __le16 seq_id; 5445 __le16 target_id; 5446 __le64 resp_addr; 5447 __le32 flags; 5448 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5449 u8 encap_type; 5450 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5451 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5452 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5453 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5454 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5455 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5456 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5457 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5458 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5459 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5460 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5461 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 5462 u8 unused_0[3]; 5463 __le32 encap_data[20]; 5464}; 5465 5466/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5467struct hwrm_cfa_encap_record_alloc_output { 5468 __le16 error_code; 5469 __le16 req_type; 5470 __le16 seq_id; 5471 __le16 resp_len; 5472 __le32 encap_record_id; 5473 u8 unused_0[3]; 5474 u8 valid; 5475}; 5476 5477/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5478struct hwrm_cfa_encap_record_free_input { 5479 __le16 req_type; 5480 __le16 cmpl_ring; 5481 __le16 seq_id; 5482 __le16 target_id; 5483 __le64 resp_addr; 5484 __le32 encap_record_id; 5485 u8 unused_0[4]; 5486}; 5487 5488/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5489struct hwrm_cfa_encap_record_free_output { 5490 __le16 error_code; 5491 __le16 req_type; 5492 __le16 seq_id; 5493 __le16 resp_len; 5494 u8 unused_0[7]; 5495 u8 valid; 5496}; 5497 5498/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 5499struct hwrm_cfa_ntuple_filter_alloc_input { 5500 __le16 req_type; 5501 __le16 cmpl_ring; 5502 __le16 seq_id; 5503 __le16 target_id; 5504 __le64 resp_addr; 5505 __le32 flags; 5506 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5507 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5508 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5509 __le32 enables; 5510 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5511 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5512 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5513 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5514 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5515 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5516 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5517 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5518 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5519 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 5520 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 5521 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 5522 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 5523 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 5524 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 5525 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 5526 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 5527 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 5528 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 5529 __le64 l2_filter_id; 5530 u8 src_macaddr[6]; 5531 __be16 ethertype; 5532 u8 ip_addr_type; 5533 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5536 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5537 u8 ip_protocol; 5538 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5541 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5542 __le16 dst_id; 5543 __le16 mirror_vnic_id; 5544 u8 tunnel_type; 5545 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5557 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5558 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5559 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5560 u8 pri_hint; 5561 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5562 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5563 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 5564 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 5565 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 5566 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 5567 __be32 src_ipaddr[4]; 5568 __be32 src_ipaddr_mask[4]; 5569 __be32 dst_ipaddr[4]; 5570 __be32 dst_ipaddr_mask[4]; 5571 __be16 src_port; 5572 __be16 src_port_mask; 5573 __be16 dst_port; 5574 __be16 dst_port_mask; 5575 __le64 ntuple_filter_id_hint; 5576}; 5577 5578/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 5579struct hwrm_cfa_ntuple_filter_alloc_output { 5580 __le16 error_code; 5581 __le16 req_type; 5582 __le16 seq_id; 5583 __le16 resp_len; 5584 __le64 ntuple_filter_id; 5585 __le32 flow_id; 5586 u8 unused_0[3]; 5587 u8 valid; 5588}; 5589 5590/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 5591struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 5592 u8 code; 5593 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 5594 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 5595 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 5596 u8 unused_0[7]; 5597}; 5598 5599/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 5600struct hwrm_cfa_ntuple_filter_free_input { 5601 __le16 req_type; 5602 __le16 cmpl_ring; 5603 __le16 seq_id; 5604 __le16 target_id; 5605 __le64 resp_addr; 5606 __le64 ntuple_filter_id; 5607}; 5608 5609/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 5610struct hwrm_cfa_ntuple_filter_free_output { 5611 __le16 error_code; 5612 __le16 req_type; 5613 __le16 seq_id; 5614 __le16 resp_len; 5615 u8 unused_0[7]; 5616 u8 valid; 5617}; 5618 5619/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 5620struct hwrm_cfa_ntuple_filter_cfg_input { 5621 __le16 req_type; 5622 __le16 cmpl_ring; 5623 __le16 seq_id; 5624 __le16 target_id; 5625 __le64 resp_addr; 5626 __le32 enables; 5627 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 5628 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5629 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 5630 u8 unused_0[4]; 5631 __le64 ntuple_filter_id; 5632 __le32 new_dst_id; 5633 __le32 new_mirror_vnic_id; 5634 __le16 new_meter_instance_id; 5635 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 5636 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 5637 u8 unused_1[6]; 5638}; 5639 5640/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 5641struct hwrm_cfa_ntuple_filter_cfg_output { 5642 __le16 error_code; 5643 __le16 req_type; 5644 __le16 seq_id; 5645 __le16 resp_len; 5646 u8 unused_0[7]; 5647 u8 valid; 5648}; 5649 5650/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 5651struct hwrm_cfa_decap_filter_alloc_input { 5652 __le16 req_type; 5653 __le16 cmpl_ring; 5654 __le16 seq_id; 5655 __le16 target_id; 5656 __le64 resp_addr; 5657 __le32 flags; 5658 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 5659 __le32 enables; 5660 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 5661 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 5662 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 5663 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 5664 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 5665 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 5666 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 5667 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 5668 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 5669 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 5670 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 5671 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 5672 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 5673 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 5674 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 5675 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5676 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5677 __be32 tunnel_id; 5678 u8 tunnel_type; 5679 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5680 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5681 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5682 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5683 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5684 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5685 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5686 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5687 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5688 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5689 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5690 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5691 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5692 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5693 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5694 u8 unused_0; 5695 __le16 unused_1; 5696 u8 src_macaddr[6]; 5697 u8 unused_2[2]; 5698 u8 dst_macaddr[6]; 5699 __be16 ovlan_vid; 5700 __be16 ivlan_vid; 5701 __be16 t_ovlan_vid; 5702 __be16 t_ivlan_vid; 5703 __be16 ethertype; 5704 u8 ip_addr_type; 5705 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5706 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5707 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5708 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5709 u8 ip_protocol; 5710 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5711 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5712 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5713 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5714 __le16 unused_3; 5715 __le32 unused_4; 5716 __be32 src_ipaddr[4]; 5717 __be32 dst_ipaddr[4]; 5718 __be16 src_port; 5719 __be16 dst_port; 5720 __le16 dst_id; 5721 __le16 l2_ctxt_ref_id; 5722}; 5723 5724/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 5725struct hwrm_cfa_decap_filter_alloc_output { 5726 __le16 error_code; 5727 __le16 req_type; 5728 __le16 seq_id; 5729 __le16 resp_len; 5730 __le32 decap_filter_id; 5731 u8 unused_0[3]; 5732 u8 valid; 5733}; 5734 5735/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 5736struct hwrm_cfa_decap_filter_free_input { 5737 __le16 req_type; 5738 __le16 cmpl_ring; 5739 __le16 seq_id; 5740 __le16 target_id; 5741 __le64 resp_addr; 5742 __le32 decap_filter_id; 5743 u8 unused_0[4]; 5744}; 5745 5746/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 5747struct hwrm_cfa_decap_filter_free_output { 5748 __le16 error_code; 5749 __le16 req_type; 5750 __le16 seq_id; 5751 __le16 resp_len; 5752 u8 unused_0[7]; 5753 u8 valid; 5754}; 5755 5756/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 5757struct hwrm_cfa_flow_alloc_input { 5758 __le16 req_type; 5759 __le16 cmpl_ring; 5760 __le16 seq_id; 5761 __le16 target_id; 5762 __le64 resp_addr; 5763 __le16 flags; 5764 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 5765 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 5766 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 5767 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 5768 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 5769 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 5770 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 5771 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 5772 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 5773 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 5774 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 5775 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 5776 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 5777 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 5778 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 5779 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 5780 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 5781 __le16 src_fid; 5782 __le32 tunnel_handle; 5783 __le16 action_flags; 5784 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 5785 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 5786 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 5787 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 5788 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 5789 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 5790 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 5791 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 5792 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 5793 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 5794 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 5795 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 5796 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 5797 __le16 dst_fid; 5798 __be16 l2_rewrite_vlan_tpid; 5799 __be16 l2_rewrite_vlan_tci; 5800 __le16 act_meter_id; 5801 __le16 ref_flow_handle; 5802 __be16 ethertype; 5803 __be16 outer_vlan_tci; 5804 __be16 dmac[3]; 5805 __be16 inner_vlan_tci; 5806 __be16 smac[3]; 5807 u8 ip_dst_mask_len; 5808 u8 ip_src_mask_len; 5809 __be32 ip_dst[4]; 5810 __be32 ip_src[4]; 5811 __be16 l4_src_port; 5812 __be16 l4_src_port_mask; 5813 __be16 l4_dst_port; 5814 __be16 l4_dst_port_mask; 5815 __be32 nat_ip_address[4]; 5816 __be16 l2_rewrite_dmac[3]; 5817 __be16 nat_port; 5818 __be16 l2_rewrite_smac[3]; 5819 u8 ip_proto; 5820 u8 tunnel_type; 5821 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5822 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5823 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5824 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5825 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5826 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5827 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5828 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5829 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5830 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5831 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5832 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5833 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5834 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5835 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5836}; 5837 5838/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 5839struct hwrm_cfa_flow_alloc_output { 5840 __le16 error_code; 5841 __le16 req_type; 5842 __le16 seq_id; 5843 __le16 resp_len; 5844 __le16 flow_handle; 5845 u8 unused_0[2]; 5846 __le32 flow_id; 5847 __le64 ext_flow_handle; 5848 __le32 flow_counter_id; 5849 u8 unused_1[3]; 5850 u8 valid; 5851}; 5852 5853/* hwrm_cfa_flow_free_input (size:256b/32B) */ 5854struct hwrm_cfa_flow_free_input { 5855 __le16 req_type; 5856 __le16 cmpl_ring; 5857 __le16 seq_id; 5858 __le16 target_id; 5859 __le64 resp_addr; 5860 __le16 flow_handle; 5861 u8 unused_0[6]; 5862 __le64 ext_flow_handle; 5863}; 5864 5865/* hwrm_cfa_flow_free_output (size:256b/32B) */ 5866struct hwrm_cfa_flow_free_output { 5867 __le16 error_code; 5868 __le16 req_type; 5869 __le16 seq_id; 5870 __le16 resp_len; 5871 __le64 packet; 5872 __le64 byte; 5873 u8 unused_0[7]; 5874 u8 valid; 5875}; 5876 5877/* hwrm_cfa_flow_info_input (size:256b/32B) */ 5878struct hwrm_cfa_flow_info_input { 5879 __le16 req_type; 5880 __le16 cmpl_ring; 5881 __le16 seq_id; 5882 __le16 target_id; 5883 __le64 resp_addr; 5884 __le16 flow_handle; 5885 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 5886 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 5887 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 5888 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 5889 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 5890 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 5891 u8 unused_0[6]; 5892 __le64 ext_flow_handle; 5893}; 5894 5895/* hwrm_cfa_flow_info_output (size:448b/56B) */ 5896struct hwrm_cfa_flow_info_output { 5897 __le16 error_code; 5898 __le16 req_type; 5899 __le16 seq_id; 5900 __le16 resp_len; 5901 u8 flags; 5902 u8 profile; 5903 __le16 src_fid; 5904 __le16 dst_fid; 5905 __le16 l2_ctxt_id; 5906 __le64 em_info; 5907 __le64 tcam_info; 5908 __le64 vfp_tcam_info; 5909 __le16 ar_id; 5910 __le16 flow_handle; 5911 __le32 tunnel_handle; 5912 __le16 flow_timer; 5913 u8 unused_0[5]; 5914 u8 valid; 5915}; 5916 5917/* hwrm_cfa_flow_stats_input (size:640b/80B) */ 5918struct hwrm_cfa_flow_stats_input { 5919 __le16 req_type; 5920 __le16 cmpl_ring; 5921 __le16 seq_id; 5922 __le16 target_id; 5923 __le64 resp_addr; 5924 __le16 num_flows; 5925 __le16 flow_handle_0; 5926 __le16 flow_handle_1; 5927 __le16 flow_handle_2; 5928 __le16 flow_handle_3; 5929 __le16 flow_handle_4; 5930 __le16 flow_handle_5; 5931 __le16 flow_handle_6; 5932 __le16 flow_handle_7; 5933 __le16 flow_handle_8; 5934 __le16 flow_handle_9; 5935 u8 unused_0[2]; 5936 __le32 flow_id_0; 5937 __le32 flow_id_1; 5938 __le32 flow_id_2; 5939 __le32 flow_id_3; 5940 __le32 flow_id_4; 5941 __le32 flow_id_5; 5942 __le32 flow_id_6; 5943 __le32 flow_id_7; 5944 __le32 flow_id_8; 5945 __le32 flow_id_9; 5946}; 5947 5948/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 5949struct hwrm_cfa_flow_stats_output { 5950 __le16 error_code; 5951 __le16 req_type; 5952 __le16 seq_id; 5953 __le16 resp_len; 5954 __le64 packet_0; 5955 __le64 packet_1; 5956 __le64 packet_2; 5957 __le64 packet_3; 5958 __le64 packet_4; 5959 __le64 packet_5; 5960 __le64 packet_6; 5961 __le64 packet_7; 5962 __le64 packet_8; 5963 __le64 packet_9; 5964 __le64 byte_0; 5965 __le64 byte_1; 5966 __le64 byte_2; 5967 __le64 byte_3; 5968 __le64 byte_4; 5969 __le64 byte_5; 5970 __le64 byte_6; 5971 __le64 byte_7; 5972 __le64 byte_8; 5973 __le64 byte_9; 5974 u8 unused_0[7]; 5975 u8 valid; 5976}; 5977 5978/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 5979struct hwrm_cfa_vfr_alloc_input { 5980 __le16 req_type; 5981 __le16 cmpl_ring; 5982 __le16 seq_id; 5983 __le16 target_id; 5984 __le64 resp_addr; 5985 __le16 vf_id; 5986 __le16 reserved; 5987 u8 unused_0[4]; 5988 char vfr_name[32]; 5989}; 5990 5991/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 5992struct hwrm_cfa_vfr_alloc_output { 5993 __le16 error_code; 5994 __le16 req_type; 5995 __le16 seq_id; 5996 __le16 resp_len; 5997 __le16 rx_cfa_code; 5998 __le16 tx_cfa_action; 5999 u8 unused_0[3]; 6000 u8 valid;
6001}; 6002 6003/* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6004struct hwrm_cfa_vfr_free_input { 6005 __le16 req_type; 6006 __le16 cmpl_ring; 6007 __le16 seq_id; 6008 __le16 target_id; 6009 __le64 resp_addr; 6010 char vfr_name[32]; 6011}; 6012 6013/* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6014struct hwrm_cfa_vfr_free_output { 6015 __le16 error_code; 6016 __le16 req_type; 6017 __le16 seq_id; 6018 __le16 resp_len; 6019 u8 unused_0[7]; 6020 u8 valid; 6021}; 6022 6023/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6024struct hwrm_cfa_eem_qcaps_input { 6025 __le16 req_type; 6026 __le16 cmpl_ring; 6027 __le16 seq_id; 6028 __le16 target_id; 6029 __le64 resp_addr; 6030 __le32 flags; 6031 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6032 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6033 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6034 __le32 unused_0; 6035}; 6036 6037/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */ 6038struct hwrm_cfa_eem_qcaps_output { 6039 __le16 error_code; 6040 __le16 req_type; 6041 __le16 seq_id; 6042 __le16 resp_len; 6043 __le32 flags; 6044 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6045 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6046 __le32 unused_0; 6047 __le32 supported; 6048 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6049 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6050 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6051 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6052 __le32 max_entries_supported; 6053 __le16 key_entry_size; 6054 __le16 record_entry_size; 6055 __le16 efc_entry_size; 6056 u8 unused_1; 6057 u8 valid; 6058}; 6059 6060/* hwrm_cfa_eem_cfg_input (size:320b/40B) */ 6061struct hwrm_cfa_eem_cfg_input { 6062 __le16 req_type; 6063 __le16 cmpl_ring; 6064 __le16 seq_id; 6065 __le16 target_id; 6066 __le64 resp_addr; 6067 __le32 flags; 6068 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6069 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6070 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6071 __le32 unused_0; 6072 __le32 num_entries; 6073 __le32 unused_1; 6074 __le16 key0_ctx_id; 6075 __le16 key1_ctx_id; 6076 __le16 record_ctx_id; 6077 __le16 efc_ctx_id; 6078}; 6079 6080/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6081struct hwrm_cfa_eem_cfg_output { 6082 __le16 error_code; 6083 __le16 req_type; 6084 __le16 seq_id; 6085 __le16 resp_len; 6086 u8 unused_0[7]; 6087 u8 valid; 6088}; 6089 6090/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6091struct hwrm_cfa_eem_qcfg_input { 6092 __le16 req_type; 6093 __le16 cmpl_ring; 6094 __le16 seq_id; 6095 __le16 target_id; 6096 __le64 resp_addr; 6097 __le32 flags; 6098 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6099 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6100 __le32 unused_0; 6101}; 6102 6103/* hwrm_cfa_eem_qcfg_output (size:128b/16B) */ 6104struct hwrm_cfa_eem_qcfg_output { 6105 __le16 error_code; 6106 __le16 req_type; 6107 __le16 seq_id; 6108 __le16 resp_len; 6109 __le32 flags; 6110 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6111 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6112 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6113 __le32 num_entries; 6114}; 6115 6116/* hwrm_cfa_eem_op_input (size:192b/24B) */ 6117struct hwrm_cfa_eem_op_input { 6118 __le16 req_type; 6119 __le16 cmpl_ring; 6120 __le16 seq_id; 6121 __le16 target_id; 6122 __le64 resp_addr; 6123 __le32 flags; 6124 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6125 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6126 __le16 unused_0; 6127 __le16 op; 6128 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6129 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6130 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6131 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6132 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6133}; 6134 6135/* hwrm_cfa_eem_op_output (size:128b/16B) */ 6136struct hwrm_cfa_eem_op_output { 6137 __le16 error_code; 6138 __le16 req_type; 6139 __le16 seq_id; 6140 __le16 resp_len; 6141 u8 unused_0[7]; 6142 u8 valid; 6143}; 6144 6145/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6146struct hwrm_tunnel_dst_port_query_input { 6147 __le16 req_type; 6148 __le16 cmpl_ring; 6149 __le16 seq_id; 6150 __le16 target_id; 6151 __le64 resp_addr; 6152 u8 tunnel_type; 6153 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6154 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6155 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6156 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6157 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6158 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6159 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6160 u8 unused_0[7]; 6161}; 6162 6163/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6164struct hwrm_tunnel_dst_port_query_output { 6165 __le16 error_code; 6166 __le16 req_type; 6167 __le16 seq_id; 6168 __le16 resp_len; 6169 __le16 tunnel_dst_port_id; 6170 __be16 tunnel_dst_port_val; 6171 u8 unused_0[3]; 6172 u8 valid; 6173}; 6174 6175/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6176struct hwrm_tunnel_dst_port_alloc_input { 6177 __le16 req_type; 6178 __le16 cmpl_ring; 6179 __le16 seq_id; 6180 __le16 target_id; 6181 __le64 resp_addr; 6182 u8 tunnel_type; 6183 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6184 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6185 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6186 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6187 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6188 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6189 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6190 u8 unused_0; 6191 __be16 tunnel_dst_port_val; 6192 u8 unused_1[4]; 6193}; 6194 6195/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6196struct hwrm_tunnel_dst_port_alloc_output { 6197 __le16 error_code; 6198 __le16 req_type; 6199 __le16 seq_id; 6200 __le16 resp_len; 6201 __le16 tunnel_dst_port_id; 6202 u8 unused_0[5]; 6203 u8 valid; 6204}; 6205 6206/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6207struct hwrm_tunnel_dst_port_free_input { 6208 __le16 req_type; 6209 __le16 cmpl_ring; 6210 __le16 seq_id; 6211 __le16 target_id; 6212 __le64 resp_addr; 6213 u8 tunnel_type; 6214 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6215 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6216 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6217 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6218 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6219 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6220 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6221 u8 unused_0; 6222 __le16 tunnel_dst_port_id; 6223 u8 unused_1[4]; 6224}; 6225 6226/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6227struct hwrm_tunnel_dst_port_free_output { 6228 __le16 error_code; 6229 __le16 req_type; 6230 __le16 seq_id; 6231 __le16 resp_len; 6232 u8 unused_1[7]; 6233 u8 valid; 6234}; 6235 6236/* ctx_hw_stats (size:1280b/160B) */ 6237struct ctx_hw_stats { 6238 __le64 rx_ucast_pkts; 6239 __le64 rx_mcast_pkts; 6240 __le64 rx_bcast_pkts; 6241 __le64 rx_discard_pkts; 6242 __le64 rx_drop_pkts; 6243 __le64 rx_ucast_bytes; 6244 __le64 rx_mcast_bytes; 6245 __le64 rx_bcast_bytes; 6246 __le64 tx_ucast_pkts; 6247 __le64 tx_mcast_pkts; 6248 __le64 tx_bcast_pkts; 6249 __le64 tx_discard_pkts; 6250 __le64 tx_drop_pkts; 6251 __le64 tx_ucast_bytes; 6252 __le64 tx_mcast_bytes; 6253 __le64 tx_bcast_bytes; 6254 __le64 tpa_pkts; 6255 __le64 tpa_bytes; 6256 __le64 tpa_events; 6257 __le64 tpa_aborts; 6258}; 6259 6260/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6261struct hwrm_stat_ctx_alloc_input { 6262 __le16 req_type; 6263 __le16 cmpl_ring; 6264 __le16 seq_id; 6265 __le16 target_id; 6266 __le64 resp_addr; 6267 __le64 stats_dma_addr; 6268 __le32 update_period_ms; 6269 u8 stat_ctx_flags; 6270 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 6271 u8 unused_0[3]; 6272}; 6273 6274/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 6275struct hwrm_stat_ctx_alloc_output { 6276 __le16 error_code; 6277 __le16 req_type; 6278 __le16 seq_id; 6279 __le16 resp_len; 6280 __le32 stat_ctx_id; 6281 u8 unused_0[3]; 6282 u8 valid; 6283}; 6284 6285/* hwrm_stat_ctx_free_input (size:192b/24B) */ 6286struct hwrm_stat_ctx_free_input { 6287 __le16 req_type; 6288 __le16 cmpl_ring; 6289 __le16 seq_id; 6290 __le16 target_id; 6291 __le64 resp_addr; 6292 __le32 stat_ctx_id; 6293 u8 unused_0[4]; 6294}; 6295 6296/* hwrm_stat_ctx_free_output (size:128b/16B) */ 6297struct hwrm_stat_ctx_free_output { 6298 __le16 error_code; 6299 __le16 req_type; 6300 __le16 seq_id; 6301 __le16 resp_len; 6302 __le32 stat_ctx_id; 6303 u8 unused_0[3]; 6304 u8 valid; 6305}; 6306 6307/* hwrm_stat_ctx_query_input (size:192b/24B) */ 6308struct hwrm_stat_ctx_query_input { 6309 __le16 req_type; 6310 __le16 cmpl_ring; 6311 __le16 seq_id; 6312 __le16 target_id; 6313 __le64 resp_addr; 6314 __le32 stat_ctx_id; 6315 u8 unused_0[4]; 6316}; 6317 6318/* hwrm_stat_ctx_query_output (size:1408b/176B) */ 6319struct hwrm_stat_ctx_query_output { 6320 __le16 error_code; 6321 __le16 req_type; 6322 __le16 seq_id; 6323 __le16 resp_len; 6324 __le64 tx_ucast_pkts; 6325 __le64 tx_mcast_pkts; 6326 __le64 tx_bcast_pkts; 6327 __le64 tx_err_pkts; 6328 __le64 tx_drop_pkts; 6329 __le64 tx_ucast_bytes; 6330 __le64 tx_mcast_bytes; 6331 __le64 tx_bcast_bytes; 6332 __le64 rx_ucast_pkts; 6333 __le64 rx_mcast_pkts; 6334 __le64 rx_bcast_pkts; 6335 __le64 rx_err_pkts; 6336 __le64 rx_drop_pkts; 6337 __le64 rx_ucast_bytes; 6338 __le64 rx_mcast_bytes; 6339 __le64 rx_bcast_bytes; 6340 __le64 rx_agg_pkts; 6341 __le64 rx_agg_bytes; 6342 __le64 rx_agg_events; 6343 __le64 rx_agg_aborts; 6344 u8 unused_0[7]; 6345 u8 valid; 6346}; 6347 6348/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 6349struct hwrm_stat_ctx_clr_stats_input { 6350 __le16 req_type; 6351 __le16 cmpl_ring; 6352 __le16 seq_id; 6353 __le16 target_id; 6354 __le64 resp_addr; 6355 __le32 stat_ctx_id; 6356 u8 unused_0[4]; 6357}; 6358 6359/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 6360struct hwrm_stat_ctx_clr_stats_output { 6361 __le16 error_code; 6362 __le16 req_type; 6363 __le16 seq_id; 6364 __le16 resp_len; 6365 u8 unused_0[7]; 6366 u8 valid; 6367}; 6368 6369/* hwrm_pcie_qstats_input (size:256b/32B) */ 6370struct hwrm_pcie_qstats_input { 6371 __le16 req_type; 6372 __le16 cmpl_ring; 6373 __le16 seq_id; 6374 __le16 target_id; 6375 __le64 resp_addr; 6376 __le16 pcie_stat_size; 6377 u8 unused_0[6]; 6378 __le64 pcie_stat_host_addr; 6379}; 6380 6381/* hwrm_pcie_qstats_output (size:128b/16B) */ 6382struct hwrm_pcie_qstats_output { 6383 __le16 error_code; 6384 __le16 req_type; 6385 __le16 seq_id; 6386 __le16 resp_len; 6387 __le16 pcie_stat_size; 6388 u8 unused_0[5]; 6389 u8 valid; 6390}; 6391 6392/* pcie_ctx_hw_stats (size:768b/96B) */ 6393struct pcie_ctx_hw_stats { 6394 __le64 pcie_pl_signal_integrity; 6395 __le64 pcie_dl_signal_integrity; 6396 __le64 pcie_tl_signal_integrity; 6397 __le64 pcie_link_integrity; 6398 __le64 pcie_tx_traffic_rate; 6399 __le64 pcie_rx_traffic_rate; 6400 __le64 pcie_tx_dllp_statistics; 6401 __le64 pcie_rx_dllp_statistics; 6402 __le64 pcie_equalization_time; 6403 __le32 pcie_ltssm_histogram[4]; 6404 __le64 pcie_recovery_histogram; 6405}; 6406 6407/* hwrm_fw_reset_input (size:192b/24B) */ 6408struct hwrm_fw_reset_input { 6409 __le16 req_type; 6410 __le16 cmpl_ring; 6411 __le16 seq_id; 6412 __le16 target_id; 6413 __le64 resp_addr; 6414 u8 embedded_proc_type; 6415 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6416 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6417 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6418 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6419 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6420 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6421 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6422 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 6423 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 6424 u8 selfrst_status; 6425 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 6426 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 6427 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6428 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6429 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6430 u8 host_idx; 6431 u8 flags; 6432 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 6433 u8 unused_0[4]; 6434}; 6435 6436/* hwrm_fw_reset_output (size:128b/16B) */ 6437struct hwrm_fw_reset_output { 6438 __le16 error_code; 6439 __le16 req_type; 6440 __le16 seq_id; 6441 __le16 resp_len; 6442 u8 selfrst_status; 6443 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6444 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6445 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6446 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6447 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 6448 u8 unused_0[6]; 6449 u8 valid; 6450}; 6451 6452/* hwrm_fw_qstatus_input (size:192b/24B) */ 6453struct hwrm_fw_qstatus_input { 6454 __le16 req_type; 6455 __le16 cmpl_ring; 6456 __le16 seq_id; 6457 __le16 target_id; 6458 __le64 resp_addr; 6459 u8 embedded_proc_type; 6460 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6461 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6462 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6463 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6464 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6465 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6466 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6467 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 6468 u8 unused_0[7]; 6469}; 6470 6471/* hwrm_fw_qstatus_output (size:128b/16B) */ 6472struct hwrm_fw_qstatus_output { 6473 __le16 error_code; 6474 __le16 req_type; 6475 __le16 seq_id; 6476 __le16 resp_len; 6477 u8 selfrst_status; 6478 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6479 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6480 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6481 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 6482 u8 unused_0[6]; 6483 u8 valid; 6484}; 6485 6486/* hwrm_fw_set_time_input (size:256b/32B) */ 6487struct hwrm_fw_set_time_input { 6488 __le16 req_type; 6489 __le16 cmpl_ring; 6490 __le16 seq_id; 6491 __le16 target_id; 6492 __le64 resp_addr; 6493 __le16 year; 6494 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 6495 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 6496 u8 month; 6497 u8 day; 6498 u8 hour; 6499 u8 minute; 6500 u8 second; 6501 u8 unused_0; 6502 __le16 millisecond; 6503 __le16 zone; 6504 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 6505 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 6506 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 6507 u8 unused_1[4]; 6508}; 6509 6510/* hwrm_fw_set_time_output (size:128b/16B) */ 6511struct hwrm_fw_set_time_output { 6512 __le16 error_code; 6513 __le16 req_type; 6514 __le16 seq_id; 6515 __le16 resp_len; 6516 u8 unused_0[7]; 6517 u8 valid; 6518}; 6519 6520/* hwrm_struct_hdr (size:128b/16B) */ 6521struct hwrm_struct_hdr { 6522 __le16 struct_id; 6523 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6524 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6525 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6526 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6527 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6528 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6529 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6530 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 6531 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6532 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6533 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6534 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 6535 __le16 len; 6536 u8 version; 6537 u8 count; 6538 __le16 subtype; 6539 __le16 next_offset; 6540 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6541 u8 unused_0[6]; 6542}; 6543 6544/* hwrm_struct_data_dcbx_app (size:64b/8B) */ 6545struct hwrm_struct_data_dcbx_app { 6546 __be16 protocol_id; 6547 u8 protocol_selector; 6548 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6549 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6550 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6551 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6552 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 6553 u8 priority; 6554 u8 valid; 6555 u8 unused_0[3]; 6556}; 6557 6558/* hwrm_fw_set_structured_data_input (size:256b/32B) */ 6559struct hwrm_fw_set_structured_data_input { 6560 __le16 req_type; 6561 __le16 cmpl_ring; 6562 __le16 seq_id; 6563 __le16 target_id; 6564 __le64 resp_addr; 6565 __le64 src_data_addr; 6566 __le16 data_len; 6567 u8 hdr_cnt; 6568 u8 unused_0[5]; 6569}; 6570 6571/* hwrm_fw_set_structured_data_output (size:128b/16B) */ 6572struct hwrm_fw_set_structured_data_output { 6573 __le16 error_code; 6574 __le16 req_type; 6575 __le16 seq_id; 6576 __le16 resp_len; 6577 u8 unused_0[7]; 6578 u8 valid; 6579}; 6580 6581/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 6582struct hwrm_fw_set_structured_data_cmd_err { 6583 u8 code; 6584 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6585 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 6586 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 6587 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6588 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6589 u8 unused_0[7]; 6590}; 6591 6592/* hwrm_fw_get_structured_data_input (size:256b/32B) */ 6593struct hwrm_fw_get_structured_data_input { 6594 __le16 req_type; 6595 __le16 cmpl_ring; 6596 __le16 seq_id; 6597 __le16 target_id; 6598 __le64 resp_addr; 6599 __le64 dest_data_addr; 6600 __le16 data_len; 6601 __le16 structure_id; 6602 __le16 subtype; 6603 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 6604 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 6605 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 6606 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 6607 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 6608 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 6609 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 6610 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 6611 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 6612 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 6613 u8 count; 6614 u8 unused_0; 6615}; 6616 6617/* hwrm_fw_get_structured_data_output (size:128b/16B) */ 6618struct hwrm_fw_get_structured_data_output { 6619 __le16 error_code; 6620 __le16 req_type; 6621 __le16 seq_id; 6622 __le16 resp_len; 6623 u8 hdr_cnt; 6624 u8 unused_0[6]; 6625 u8 valid; 6626}; 6627 6628/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 6629struct hwrm_fw_get_structured_data_cmd_err { 6630 u8 code; 6631 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6632 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6633 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6634 u8 unused_0[7]; 6635}; 6636 6637/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 6638struct hwrm_exec_fwd_resp_input { 6639 __le16 req_type; 6640 __le16 cmpl_ring; 6641 __le16 seq_id; 6642 __le16 target_id; 6643 __le64 resp_addr; 6644 __le32 encap_request[26]; 6645 __le16 encap_resp_target_id; 6646 u8 unused_0[6]; 6647}; 6648 6649/* hwrm_exec_fwd_resp_output (size:128b/16B) */ 6650struct hwrm_exec_fwd_resp_output { 6651 __le16 error_code; 6652 __le16 req_type; 6653 __le16 seq_id; 6654 __le16 resp_len; 6655 u8 unused_0[7]; 6656 u8 valid; 6657}; 6658 6659/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 6660struct hwrm_reject_fwd_resp_input { 6661 __le16 req_type; 6662 __le16 cmpl_ring; 6663 __le16 seq_id; 6664 __le16 target_id; 6665 __le64 resp_addr; 6666 __le32 encap_request[26]; 6667 __le16 encap_resp_target_id; 6668 u8 unused_0[6]; 6669}; 6670 6671/* hwrm_reject_fwd_resp_output (size:128b/16B) */ 6672struct hwrm_reject_fwd_resp_output { 6673 __le16 error_code; 6674 __le16 req_type; 6675 __le16 seq_id; 6676 __le16 resp_len; 6677 u8 unused_0[7]; 6678 u8 valid; 6679}; 6680 6681/* hwrm_fwd_resp_input (size:1024b/128B) */ 6682struct hwrm_fwd_resp_input { 6683 __le16 req_type; 6684 __le16 cmpl_ring; 6685 __le16 seq_id; 6686 __le16 target_id; 6687 __le64 resp_addr; 6688 __le16 encap_resp_target_id; 6689 __le16 encap_resp_cmpl_ring; 6690 __le16 encap_resp_len; 6691 u8 unused_0; 6692 u8 unused_1; 6693 __le64 encap_resp_addr; 6694 __le32 encap_resp[24]; 6695}; 6696 6697/* hwrm_fwd_resp_output (size:128b/16B) */ 6698struct hwrm_fwd_resp_output { 6699 __le16 error_code; 6700 __le16 req_type; 6701 __le16 seq_id; 6702 __le16 resp_len; 6703 u8 unused_0[7]; 6704 u8 valid; 6705}; 6706 6707/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 6708struct hwrm_fwd_async_event_cmpl_input { 6709 __le16 req_type; 6710 __le16 cmpl_ring; 6711 __le16 seq_id; 6712 __le16 target_id; 6713 __le64 resp_addr; 6714 __le16 encap_async_event_target_id; 6715 u8 unused_0[6]; 6716 __le32 encap_async_event_cmpl[4]; 6717}; 6718 6719/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 6720struct hwrm_fwd_async_event_cmpl_output { 6721 __le16 error_code; 6722 __le16 req_type; 6723 __le16 seq_id; 6724 __le16 resp_len; 6725 u8 unused_0[7]; 6726 u8 valid; 6727}; 6728 6729/* hwrm_temp_monitor_query_input (size:128b/16B) */ 6730struct hwrm_temp_monitor_query_input { 6731 __le16 req_type; 6732 __le16 cmpl_ring; 6733 __le16 seq_id; 6734 __le16 target_id; 6735 __le64 resp_addr; 6736}; 6737 6738/* hwrm_temp_monitor_query_output (size:128b/16B) */ 6739struct hwrm_temp_monitor_query_output { 6740 __le16 error_code; 6741 __le16 req_type; 6742 __le16 seq_id; 6743 __le16 resp_len; 6744 u8 temp; 6745 u8 unused_0[6]; 6746 u8 valid; 6747}; 6748 6749/* hwrm_wol_filter_alloc_input (size:512b/64B) */ 6750struct hwrm_wol_filter_alloc_input { 6751 __le16 req_type; 6752 __le16 cmpl_ring; 6753 __le16 seq_id; 6754 __le16 target_id; 6755 __le64 resp_addr; 6756 __le32 flags; 6757 __le32 enables; 6758 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 6759 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 6760 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 6761 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 6762 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 6763 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 6764 __le16 port_id; 6765 u8 wol_type; 6766 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 6767 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 6768 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 6769 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 6770 u8 unused_0[5]; 6771 u8 mac_address[6]; 6772 __le16 pattern_offset; 6773 __le16 pattern_buf_size; 6774 __le16 pattern_mask_size; 6775 u8 unused_1[4]; 6776 __le64 pattern_buf_addr; 6777 __le64 pattern_mask_addr; 6778}; 6779 6780/* hwrm_wol_filter_alloc_output (size:128b/16B) */ 6781struct hwrm_wol_filter_alloc_output { 6782 __le16 error_code; 6783 __le16 req_type; 6784 __le16 seq_id; 6785 __le16 resp_len; 6786 u8 wol_filter_id; 6787 u8 unused_0[6]; 6788 u8 valid; 6789}; 6790 6791/* hwrm_wol_filter_free_input (size:256b/32B) */ 6792struct hwrm_wol_filter_free_input { 6793 __le16 req_type; 6794 __le16 cmpl_ring; 6795 __le16 seq_id; 6796 __le16 target_id; 6797 __le64 resp_addr; 6798 __le32 flags; 6799 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 6800 __le32 enables; 6801 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 6802 __le16 port_id; 6803 u8 wol_filter_id; 6804 u8 unused_0[5]; 6805}; 6806 6807/* hwrm_wol_filter_free_output (size:128b/16B) */ 6808struct hwrm_wol_filter_free_output { 6809 __le16 error_code; 6810 __le16 req_type; 6811 __le16 seq_id; 6812 __le16 resp_len; 6813 u8 unused_0[7]; 6814 u8 valid; 6815}; 6816 6817/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 6818struct hwrm_wol_filter_qcfg_input { 6819 __le16 req_type; 6820 __le16 cmpl_ring; 6821 __le16 seq_id; 6822 __le16 target_id; 6823 __le64 resp_addr; 6824 __le16 port_id; 6825 __le16 handle; 6826 u8 unused_0[4]; 6827 __le64 pattern_buf_addr; 6828 __le16 pattern_buf_size; 6829 u8 unused_1[6]; 6830 __le64 pattern_mask_addr; 6831 __le16 pattern_mask_size; 6832 u8 unused_2[6]; 6833}; 6834 6835/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 6836struct hwrm_wol_filter_qcfg_output { 6837 __le16 error_code; 6838 __le16 req_type; 6839 __le16 seq_id; 6840 __le16 resp_len; 6841 __le16 next_handle; 6842 u8 wol_filter_id; 6843 u8 wol_type; 6844 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 6845 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 6846 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 6847 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 6848 __le32 unused_0; 6849 u8 mac_address[6]; 6850 __le16 pattern_offset; 6851 __le16 pattern_size; 6852 __le16 pattern_mask_size; 6853 u8 unused_1[3]; 6854 u8 valid; 6855}; 6856 6857/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 6858struct hwrm_wol_reason_qcfg_input { 6859 __le16 req_type; 6860 __le16 cmpl_ring; 6861 __le16 seq_id; 6862 __le16 target_id; 6863 __le64 resp_addr; 6864 __le16 port_id; 6865 u8 unused_0[6]; 6866 __le64 wol_pkt_buf_addr; 6867 __le16 wol_pkt_buf_size; 6868 u8 unused_1[6]; 6869}; 6870 6871/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 6872struct hwrm_wol_reason_qcfg_output { 6873 __le16 error_code; 6874 __le16 req_type; 6875 __le16 seq_id; 6876 __le16 resp_len; 6877 u8 wol_filter_id; 6878 u8 wol_reason; 6879 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 6880 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 6881 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 6882 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 6883 u8 wol_pkt_len; 6884 u8 unused_0[4]; 6885 u8 valid; 6886}; 6887 6888/* coredump_segment_record (size:128b/16B) */ 6889struct coredump_segment_record { 6890 __le16 component_id; 6891 __le16 segment_id; 6892 __le16 max_instances; 6893 u8 version_hi; 6894 u8 version_low; 6895 u8 seg_flags; 6896 u8 unused_0[7]; 6897}; 6898 6899/* hwrm_dbg_coredump_list_input (size:256b/32B) */ 6900struct hwrm_dbg_coredump_list_input { 6901 __le16 req_type; 6902 __le16 cmpl_ring; 6903 __le16 seq_id; 6904 __le16 target_id; 6905 __le64 resp_addr; 6906 __le64 host_dest_addr; 6907 __le32 host_buf_len; 6908 __le16 seq_no; 6909 u8 unused_0[2]; 6910}; 6911 6912/* hwrm_dbg_coredump_list_output (size:128b/16B) */ 6913struct hwrm_dbg_coredump_list_output { 6914 __le16 error_code; 6915 __le16 req_type; 6916 __le16 seq_id; 6917 __le16 resp_len; 6918 u8 flags; 6919 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 6920 u8 unused_0; 6921 __le16 total_segments; 6922 __le16 data_len; 6923 u8 unused_1; 6924 u8 valid; 6925}; 6926 6927/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 6928struct hwrm_dbg_coredump_initiate_input { 6929 __le16 req_type; 6930 __le16 cmpl_ring; 6931 __le16 seq_id; 6932 __le16 target_id; 6933 __le64 resp_addr; 6934 __le16 component_id; 6935 __le16 segment_id; 6936 __le16 instance; 6937 __le16 unused_0; 6938 u8 seg_flags; 6939 u8 unused_1[7]; 6940}; 6941 6942/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 6943struct hwrm_dbg_coredump_initiate_output { 6944 __le16 error_code; 6945 __le16 req_type; 6946 __le16 seq_id; 6947 __le16 resp_len; 6948 u8 unused_0[7]; 6949 u8 valid; 6950}; 6951 6952/* coredump_data_hdr (size:128b/16B) */ 6953struct coredump_data_hdr { 6954 __le32 address; 6955 __le32 flags_length; 6956 __le32 instance; 6957 __le32 next_offset; 6958}; 6959 6960/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 6961struct hwrm_dbg_coredump_retrieve_input { 6962 __le16 req_type; 6963 __le16 cmpl_ring; 6964 __le16 seq_id; 6965 __le16 target_id; 6966 __le64 resp_addr; 6967 __le64 host_dest_addr; 6968 __le32 host_buf_len; 6969 __le32 unused_0; 6970 __le16 component_id; 6971 __le16 segment_id; 6972 __le16 instance; 6973 __le16 unused_1; 6974 u8 seg_flags; 6975 u8 unused_2; 6976 __le16 unused_3; 6977 __le32 unused_4; 6978 __le32 seq_no; 6979 __le32 unused_5; 6980}; 6981 6982/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 6983struct hwrm_dbg_coredump_retrieve_output { 6984 __le16 error_code; 6985 __le16 req_type; 6986 __le16 seq_id; 6987 __le16 resp_len; 6988 u8 flags; 6989 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 6990 u8 unused_0; 6991 __le16 data_len; 6992 u8 unused_1[3]; 6993 u8 valid; 6994}; 6995 6996/* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 6997struct hwrm_dbg_ring_info_get_input { 6998 __le16 req_type; 6999 __le16 cmpl_ring; 7000 __le16 seq_id;
7001 __le16 target_id; 7002 __le64 resp_addr; 7003 u8 ring_type; 7004 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7005 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7006 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7007 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 7008 u8 unused_0[3]; 7009 __le32 fw_ring_id; 7010}; 7011 7012/* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7013struct hwrm_dbg_ring_info_get_output { 7014 __le16 error_code; 7015 __le16 req_type; 7016 __le16 seq_id; 7017 __le16 resp_len; 7018 __le32 producer_index; 7019 __le32 consumer_index; 7020 u8 unused_0[7]; 7021 u8 valid; 7022}; 7023 7024/* hwrm_nvm_read_input (size:320b/40B) */ 7025struct hwrm_nvm_read_input { 7026 __le16 req_type; 7027 __le16 cmpl_ring; 7028 __le16 seq_id; 7029 __le16 target_id; 7030 __le64 resp_addr; 7031 __le64 host_dest_addr; 7032 __le16 dir_idx; 7033 u8 unused_0[2]; 7034 __le32 offset; 7035 __le32 len; 7036 u8 unused_1[4]; 7037}; 7038 7039/* hwrm_nvm_read_output (size:128b/16B) */ 7040struct hwrm_nvm_read_output { 7041 __le16 error_code; 7042 __le16 req_type; 7043 __le16 seq_id; 7044 __le16 resp_len; 7045 u8 unused_0[7]; 7046 u8 valid; 7047}; 7048 7049/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7050struct hwrm_nvm_get_dir_entries_input { 7051 __le16 req_type; 7052 __le16 cmpl_ring; 7053 __le16 seq_id; 7054 __le16 target_id; 7055 __le64 resp_addr; 7056 __le64 host_dest_addr; 7057}; 7058 7059/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7060struct hwrm_nvm_get_dir_entries_output { 7061 __le16 error_code; 7062 __le16 req_type; 7063 __le16 seq_id; 7064 __le16 resp_len; 7065 u8 unused_0[7]; 7066 u8 valid; 7067}; 7068 7069/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7070struct hwrm_nvm_get_dir_info_input { 7071 __le16 req_type; 7072 __le16 cmpl_ring; 7073 __le16 seq_id; 7074 __le16 target_id; 7075 __le64 resp_addr; 7076}; 7077 7078/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7079struct hwrm_nvm_get_dir_info_output { 7080 __le16 error_code; 7081 __le16 req_type; 7082 __le16 seq_id; 7083 __le16 resp_len; 7084 __le32 entries; 7085 __le32 entry_length; 7086 u8 unused_0[7]; 7087 u8 valid; 7088}; 7089 7090/* hwrm_nvm_write_input (size:384b/48B) */ 7091struct hwrm_nvm_write_input { 7092 __le16 req_type; 7093 __le16 cmpl_ring; 7094 __le16 seq_id; 7095 __le16 target_id; 7096 __le64 resp_addr; 7097 __le64 host_src_addr; 7098 __le16 dir_type; 7099 __le16 dir_ordinal; 7100 __le16 dir_ext; 7101 __le16 dir_attr; 7102 __le32 dir_data_length; 7103 __le16 option; 7104 __le16 flags; 7105 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7106 __le32 dir_item_length; 7107 __le32 unused_0; 7108}; 7109 7110/* hwrm_nvm_write_output (size:128b/16B) */ 7111struct hwrm_nvm_write_output { 7112 __le16 error_code; 7113 __le16 req_type; 7114 __le16 seq_id; 7115 __le16 resp_len; 7116 __le32 dir_item_length; 7117 __le16 dir_idx; 7118 u8 unused_0; 7119 u8 valid; 7120}; 7121 7122/* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7123struct hwrm_nvm_write_cmd_err { 7124 u8 code; 7125 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7126 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7127 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7128 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7129 u8 unused_0[7]; 7130}; 7131 7132/* hwrm_nvm_modify_input (size:320b/40B) */ 7133struct hwrm_nvm_modify_input { 7134 __le16 req_type; 7135 __le16 cmpl_ring; 7136 __le16 seq_id; 7137 __le16 target_id; 7138 __le64 resp_addr; 7139 __le64 host_src_addr; 7140 __le16 dir_idx; 7141 u8 unused_0[2]; 7142 __le32 offset; 7143 __le32 len; 7144 u8 unused_1[4]; 7145}; 7146 7147/* hwrm_nvm_modify_output (size:128b/16B) */ 7148struct hwrm_nvm_modify_output { 7149 __le16 error_code; 7150 __le16 req_type; 7151 __le16 seq_id; 7152 __le16 resp_len; 7153 u8 unused_0[7]; 7154 u8 valid; 7155}; 7156 7157/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7158struct hwrm_nvm_find_dir_entry_input { 7159 __le16 req_type; 7160 __le16 cmpl_ring; 7161 __le16 seq_id; 7162 __le16 target_id; 7163 __le64 resp_addr; 7164 __le32 enables; 7165 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7166 __le16 dir_idx; 7167 __le16 dir_type; 7168 __le16 dir_ordinal; 7169 __le16 dir_ext; 7170 u8 opt_ordinal; 7171 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7172 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7173 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 7174 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 7175 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 7176 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 7177 u8 unused_0[3]; 7178}; 7179 7180/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 7181struct hwrm_nvm_find_dir_entry_output { 7182 __le16 error_code; 7183 __le16 req_type; 7184 __le16 seq_id; 7185 __le16 resp_len; 7186 __le32 dir_item_length; 7187 __le32 dir_data_length; 7188 __le32 fw_ver; 7189 __le16 dir_ordinal; 7190 __le16 dir_idx; 7191 u8 unused_0[7]; 7192 u8 valid; 7193}; 7194 7195/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 7196struct hwrm_nvm_erase_dir_entry_input { 7197 __le16 req_type; 7198 __le16 cmpl_ring; 7199 __le16 seq_id; 7200 __le16 target_id; 7201 __le64 resp_addr; 7202 __le16 dir_idx; 7203 u8 unused_0[6]; 7204}; 7205 7206/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 7207struct hwrm_nvm_erase_dir_entry_output { 7208 __le16 error_code; 7209 __le16 req_type; 7210 __le16 seq_id; 7211 __le16 resp_len; 7212 u8 unused_0[7]; 7213 u8 valid; 7214}; 7215 7216/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 7217struct hwrm_nvm_get_dev_info_input { 7218 __le16 req_type; 7219 __le16 cmpl_ring; 7220 __le16 seq_id; 7221 __le16 target_id; 7222 __le64 resp_addr; 7223}; 7224 7225/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 7226struct hwrm_nvm_get_dev_info_output { 7227 __le16 error_code; 7228 __le16 req_type; 7229 __le16 seq_id; 7230 __le16 resp_len; 7231 __le16 manufacturer_id; 7232 __le16 device_id; 7233 __le32 sector_size; 7234 __le32 nvram_size; 7235 __le32 reserved_size; 7236 __le32 available_size; 7237 u8 unused_0[3]; 7238 u8 valid; 7239}; 7240 7241/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 7242struct hwrm_nvm_mod_dir_entry_input { 7243 __le16 req_type; 7244 __le16 cmpl_ring; 7245 __le16 seq_id; 7246 __le16 target_id; 7247 __le64 resp_addr; 7248 __le32 enables; 7249 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 7250 __le16 dir_idx; 7251 __le16 dir_ordinal; 7252 __le16 dir_ext; 7253 __le16 dir_attr; 7254 __le32 checksum; 7255}; 7256 7257/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 7258struct hwrm_nvm_mod_dir_entry_output { 7259 __le16 error_code; 7260 __le16 req_type; 7261 __le16 seq_id; 7262 __le16 resp_len; 7263 u8 unused_0[7]; 7264 u8 valid; 7265}; 7266 7267/* hwrm_nvm_verify_update_input (size:192b/24B) */ 7268struct hwrm_nvm_verify_update_input { 7269 __le16 req_type; 7270 __le16 cmpl_ring; 7271 __le16 seq_id; 7272 __le16 target_id; 7273 __le64 resp_addr; 7274 __le16 dir_type; 7275 __le16 dir_ordinal; 7276 __le16 dir_ext; 7277 u8 unused_0[2]; 7278}; 7279 7280/* hwrm_nvm_verify_update_output (size:128b/16B) */ 7281struct hwrm_nvm_verify_update_output { 7282 __le16 error_code; 7283 __le16 req_type; 7284 __le16 seq_id; 7285 __le16 resp_len; 7286 u8 unused_0[7]; 7287 u8 valid; 7288}; 7289 7290/* hwrm_nvm_install_update_input (size:192b/24B) */ 7291struct hwrm_nvm_install_update_input { 7292 __le16 req_type; 7293 __le16 cmpl_ring; 7294 __le16 seq_id; 7295 __le16 target_id; 7296 __le64 resp_addr; 7297 __le32 install_type; 7298 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 7299 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 7300 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 7301 __le16 flags; 7302 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 7303 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 7304 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 7305 u8 unused_0[2]; 7306}; 7307 7308/* hwrm_nvm_install_update_output (size:192b/24B) */ 7309struct hwrm_nvm_install_update_output { 7310 __le16 error_code; 7311 __le16 req_type; 7312 __le16 seq_id; 7313 __le16 resp_len; 7314 __le64 installed_items; 7315 u8 result; 7316 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 7317 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 7318 u8 problem_item; 7319 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 7320 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 7321 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 7322 u8 reset_required; 7323 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 7324 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 7325 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 7326 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 7327 u8 unused_0[4]; 7328 u8 valid; 7329}; 7330 7331/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 7332struct hwrm_nvm_install_update_cmd_err { 7333 u8 code; 7334 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 7335 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7336 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 7337 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 7338 u8 unused_0[7]; 7339}; 7340 7341/* hwrm_nvm_get_variable_input (size:320b/40B) */ 7342struct hwrm_nvm_get_variable_input { 7343 __le16 req_type; 7344 __le16 cmpl_ring; 7345 __le16 seq_id; 7346 __le16 target_id; 7347 __le64 resp_addr; 7348 __le64 dest_data_addr; 7349 __le16 data_len; 7350 __le16 option_num; 7351 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7352 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7353 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7354 __le16 dimensions; 7355 __le16 index_0; 7356 __le16 index_1; 7357 __le16 index_2; 7358 __le16 index_3; 7359 u8 flags; 7360 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 7361 u8 unused_0; 7362}; 7363 7364/* hwrm_nvm_get_variable_output (size:128b/16B) */ 7365struct hwrm_nvm_get_variable_output { 7366 __le16 error_code; 7367 __le16 req_type; 7368 __le16 seq_id; 7369 __le16 resp_len; 7370 __le16 data_len; 7371 __le16 option_num; 7372 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 7373 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 7374 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 7375 u8 unused_0[3]; 7376 u8 valid; 7377}; 7378 7379/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 7380struct hwrm_nvm_get_variable_cmd_err { 7381 u8 code; 7382 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7383 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7384 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7385 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 7386 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 7387 u8 unused_0[7]; 7388}; 7389 7390/* hwrm_nvm_set_variable_input (size:320b/40B) */ 7391struct hwrm_nvm_set_variable_input { 7392 __le16 req_type; 7393 __le16 cmpl_ring; 7394 __le16 seq_id; 7395 __le16 target_id; 7396 __le64 resp_addr; 7397 __le64 src_data_addr; 7398 __le16 data_len; 7399 __le16 option_num; 7400 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7401 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7402 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7403 __le16 dimensions; 7404 __le16 index_0; 7405 __le16 index_1; 7406 __le16 index_2; 7407 __le16 index_3; 7408 u8 flags; 7409 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 7410 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 7411 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 7412 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 7413 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 7414 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 7415 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 7416 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 7417 u8 unused_0; 7418}; 7419 7420/* hwrm_nvm_set_variable_output (size:128b/16B) */ 7421struct hwrm_nvm_set_variable_output { 7422 __le16 error_code; 7423 __le16 req_type; 7424 __le16 seq_id; 7425 __le16 resp_len; 7426 u8 unused_0[7]; 7427 u8 valid; 7428}; 7429 7430/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 7431struct hwrm_nvm_set_variable_cmd_err { 7432 u8 code; 7433 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7434 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7435 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7436 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 7437 u8 unused_0[7]; 7438}; 7439 7440/* hwrm_selftest_qlist_input (size:128b/16B) */ 7441struct hwrm_selftest_qlist_input { 7442 __le16 req_type; 7443 __le16 cmpl_ring; 7444 __le16 seq_id; 7445 __le16 target_id; 7446 __le64 resp_addr; 7447}; 7448 7449/* hwrm_selftest_qlist_output (size:2240b/280B) */ 7450struct hwrm_selftest_qlist_output { 7451 __le16 error_code; 7452 __le16 req_type; 7453 __le16 seq_id; 7454 __le16 resp_len; 7455 u8 num_tests; 7456 u8 available_tests; 7457 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 7458 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 7459 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 7460 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 7461 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 7462 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7463 u8 offline_tests; 7464 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 7465 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 7466 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 7467 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 7468 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 7469 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7470 u8 unused_0; 7471 __le16 test_timeout; 7472 u8 unused_1[2]; 7473 char test0_name[32]; 7474 char test1_name[32]; 7475 char test2_name[32]; 7476 char test3_name[32]; 7477 char test4_name[32]; 7478 char test5_name[32]; 7479 char test6_name[32]; 7480 char test7_name[32]; 7481 u8 unused_2[7]; 7482 u8 valid; 7483}; 7484 7485/* hwrm_selftest_exec_input (size:192b/24B) */ 7486struct hwrm_selftest_exec_input { 7487 __le16 req_type; 7488 __le16 cmpl_ring; 7489 __le16 seq_id; 7490 __le16 target_id; 7491 __le64 resp_addr; 7492 u8 flags; 7493 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 7494 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 7495 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 7496 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 7497 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 7498 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 7499 u8 unused_0[7]; 7500}; 7501 7502/* hwrm_selftest_exec_output (size:128b/16B) */ 7503struct hwrm_selftest_exec_output { 7504 __le16 error_code; 7505 __le16 req_type; 7506 __le16 seq_id; 7507 __le16 resp_len; 7508 u8 requested_tests; 7509 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 7510 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 7511 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 7512 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 7513 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 7514 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 7515 u8 test_success; 7516 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 7517 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 7518 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 7519 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 7520 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 7521 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 7522 u8 unused_0[5]; 7523 u8 valid; 7524}; 7525 7526/* hwrm_selftest_irq_input (size:128b/16B) */ 7527struct hwrm_selftest_irq_input { 7528 __le16 req_type; 7529 __le16 cmpl_ring; 7530 __le16 seq_id; 7531 __le16 target_id; 7532 __le64 resp_addr; 7533}; 7534 7535/* hwrm_selftest_irq_output (size:128b/16B) */ 7536struct hwrm_selftest_irq_output { 7537 __le16 error_code; 7538 __le16 req_type; 7539 __le16 seq_id; 7540 __le16 resp_len; 7541 u8 unused_0[7]; 7542 u8 valid; 7543}; 7544 7545#endif /* _BNXT_HSI_H_ */ 7546