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22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
32#include <linux/of.h>
33#include <linux/phy.h>
34#include <linux/platform_device.h>
35#include <linux/property.h>
36#include <linux/crc32.h>
37#include <linux/if_vlan.h>
38#include <linux/of_net.h>
39#include <net/ip.h>
40#include <net/ncsi.h>
41
42#include "ftgmac100.h"
43
44#define DRV_NAME "ftgmac100"
45#define DRV_VERSION "0.7"
46
47
48#define MAX_RX_QUEUE_ENTRIES 1024
49#define MAX_TX_QUEUE_ENTRIES 1024
50#define MIN_RX_QUEUE_ENTRIES 32
51#define MIN_TX_QUEUE_ENTRIES 32
52
53
54#define DEF_RX_QUEUE_ENTRIES 128
55#define DEF_TX_QUEUE_ENTRIES 128
56
57#define MAX_PKT_SIZE 1536
58#define RX_BUF_SIZE MAX_PKT_SIZE
59
60
61#define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
62
63#define FTGMAC_100MHZ 100000000
64#define FTGMAC_25MHZ 25000000
65
66struct ftgmac100 {
67
68 struct resource *res;
69 void __iomem *base;
70
71
72 unsigned int rx_q_entries;
73 struct ftgmac100_rxdes *rxdes;
74 dma_addr_t rxdes_dma;
75 struct sk_buff **rx_skbs;
76 unsigned int rx_pointer;
77 u32 rxdes0_edorr_mask;
78
79
80 unsigned int tx_q_entries;
81 struct ftgmac100_txdes *txdes;
82 dma_addr_t txdes_dma;
83 struct sk_buff **tx_skbs;
84 unsigned int tx_clean_pointer;
85 unsigned int tx_pointer;
86 u32 txdes0_edotr_mask;
87
88
89 unsigned int new_rx_q_entries;
90 unsigned int new_tx_q_entries;
91
92
93 void *rx_scratch;
94 dma_addr_t rx_scratch_dma;
95
96
97 struct net_device *netdev;
98 struct device *dev;
99 struct ncsi_dev *ndev;
100 struct napi_struct napi;
101 struct work_struct reset_task;
102 struct mii_bus *mii_bus;
103 struct clk *clk;
104
105
106 int cur_speed;
107 int cur_duplex;
108 bool use_ncsi;
109
110
111 u32 maht0;
112 u32 maht1;
113
114
115 bool tx_pause;
116 bool rx_pause;
117 bool aneg_pause;
118
119
120 bool need_mac_restart;
121 bool is_aspeed;
122};
123
124static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
125{
126 struct net_device *netdev = priv->netdev;
127 int i;
128
129
130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
131 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
132 priv->base + FTGMAC100_OFFSET_MACCR);
133 for (i = 0; i < 200; i++) {
134 unsigned int maccr;
135
136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
137 if (!(maccr & FTGMAC100_MACCR_SW_RST))
138 return 0;
139
140 udelay(1);
141 }
142
143 netdev_err(netdev, "Hardware reset failed\n");
144 return -EIO;
145}
146
147static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
148{
149 u32 maccr = 0;
150
151 switch (priv->cur_speed) {
152 case SPEED_10:
153 case 0:
154 break;
155
156 case SPEED_100:
157 maccr |= FTGMAC100_MACCR_FAST_MODE;
158 break;
159
160 case SPEED_1000:
161 maccr |= FTGMAC100_MACCR_GIGA_MODE;
162 break;
163 default:
164 netdev_err(priv->netdev, "Unknown speed %d !\n",
165 priv->cur_speed);
166 break;
167 }
168
169
170 priv->rx_pointer = 0;
171 priv->tx_clean_pointer = 0;
172 priv->tx_pointer = 0;
173
174
175 if (ftgmac100_reset_mac(priv, maccr))
176 return -EIO;
177 usleep_range(10, 1000);
178 return ftgmac100_reset_mac(priv, maccr);
179}
180
181static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
182{
183 unsigned int maddr = mac[0] << 8 | mac[1];
184 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
185
186 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
187 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
188}
189
190static void ftgmac100_initial_mac(struct ftgmac100 *priv)
191{
192 u8 mac[ETH_ALEN];
193 unsigned int m;
194 unsigned int l;
195 void *addr;
196
197 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
198 if (addr) {
199 ether_addr_copy(priv->netdev->dev_addr, mac);
200 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
201 mac);
202 return;
203 }
204
205 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
206 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
207
208 mac[0] = (m >> 8) & 0xff;
209 mac[1] = m & 0xff;
210 mac[2] = (l >> 24) & 0xff;
211 mac[3] = (l >> 16) & 0xff;
212 mac[4] = (l >> 8) & 0xff;
213 mac[5] = l & 0xff;
214
215 if (is_valid_ether_addr(mac)) {
216 ether_addr_copy(priv->netdev->dev_addr, mac);
217 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
218 } else {
219 eth_hw_addr_random(priv->netdev);
220 dev_info(priv->dev, "Generated random MAC address %pM\n",
221 priv->netdev->dev_addr);
222 }
223}
224
225static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
226{
227 int ret;
228
229 ret = eth_prepare_mac_addr_change(dev, p);
230 if (ret < 0)
231 return ret;
232
233 eth_commit_mac_addr_change(dev, p);
234 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
235
236 return 0;
237}
238
239static void ftgmac100_config_pause(struct ftgmac100 *priv)
240{
241 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
242
243
244 if (priv->rx_pause)
245 fcr |= FTGMAC100_FCR_FC_EN;
246
247
248
249
250 if (priv->tx_pause)
251 fcr |= FTGMAC100_FCR_FCTHR_EN;
252
253 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
254}
255
256static void ftgmac100_init_hw(struct ftgmac100 *priv)
257{
258 u32 reg, rfifo_sz, tfifo_sz;
259
260
261 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
262 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
263
264
265 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
266
267
268 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
269
270
271 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
272 priv->base + FTGMAC100_OFFSET_RBSR);
273
274
275 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
276 priv->base + FTGMAC100_OFFSET_APTC);
277
278
279 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
280
281
282 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
283 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
284
285
286
287
288
289
290 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) |
291 FTGMAC100_DBLAC_TXDES_SIZE(2) |
292 FTGMAC100_DBLAC_RXBURST_SIZE(3) |
293 FTGMAC100_DBLAC_TXBURST_SIZE(3) |
294 FTGMAC100_DBLAC_RX_THR_EN |
295 FTGMAC100_DBLAC_RXFIFO_HTHR(6) |
296 FTGMAC100_DBLAC_RXFIFO_LTHR(2),
297 priv->base + FTGMAC100_OFFSET_DBLAC);
298
299
300
301
302
303 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
304 FTGMAC100_ITC_TXINT_THR(1),
305 priv->base + FTGMAC100_OFFSET_ITC);
306
307
308 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
309 rfifo_sz = reg & 0x00000007;
310 tfifo_sz = (reg >> 3) & 0x00000007;
311 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
312 reg &= ~0x3f000000;
313 reg |= (tfifo_sz << 27);
314 reg |= (rfifo_sz << 24);
315 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
316}
317
318static void ftgmac100_start_hw(struct ftgmac100 *priv)
319{
320 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
321
322
323 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
324
325
326 maccr |= FTGMAC100_MACCR_TXDMA_EN |
327 FTGMAC100_MACCR_RXDMA_EN |
328 FTGMAC100_MACCR_TXMAC_EN |
329 FTGMAC100_MACCR_RXMAC_EN |
330 FTGMAC100_MACCR_CRC_APD |
331 FTGMAC100_MACCR_PHY_LINK_LEVEL |
332 FTGMAC100_MACCR_RX_RUNT |
333 FTGMAC100_MACCR_RX_BROADPKT;
334
335
336 if (priv->cur_duplex == DUPLEX_FULL)
337 maccr |= FTGMAC100_MACCR_FULLDUP;
338 if (priv->netdev->flags & IFF_PROMISC)
339 maccr |= FTGMAC100_MACCR_RX_ALL;
340 if (priv->netdev->flags & IFF_ALLMULTI)
341 maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
342 else if (netdev_mc_count(priv->netdev))
343 maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
344
345
346 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
347 maccr |= FTGMAC100_MACCR_RM_VLAN;
348
349
350 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
351}
352
353static void ftgmac100_stop_hw(struct ftgmac100 *priv)
354{
355 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
356}
357
358static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
359{
360 struct netdev_hw_addr *ha;
361
362 priv->maht1 = 0;
363 priv->maht0 = 0;
364 netdev_for_each_mc_addr(ha, priv->netdev) {
365 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
366
367 crc_val = (~(crc_val >> 2)) & 0x3f;
368 if (crc_val >= 32)
369 priv->maht1 |= 1ul << (crc_val - 32);
370 else
371 priv->maht0 |= 1ul << (crc_val);
372 }
373}
374
375static void ftgmac100_set_rx_mode(struct net_device *netdev)
376{
377 struct ftgmac100 *priv = netdev_priv(netdev);
378
379
380 ftgmac100_calc_mc_hash(priv);
381
382
383 if (!netif_running(netdev))
384 return;
385
386
387 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
388 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
389
390
391 ftgmac100_start_hw(priv);
392}
393
394static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
395 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
396{
397 struct net_device *netdev = priv->netdev;
398 struct sk_buff *skb;
399 dma_addr_t map;
400 int err = 0;
401
402 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
403 if (unlikely(!skb)) {
404 if (net_ratelimit())
405 netdev_warn(netdev, "failed to allocate rx skb\n");
406 err = -ENOMEM;
407 map = priv->rx_scratch_dma;
408 } else {
409 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
410 DMA_FROM_DEVICE);
411 if (unlikely(dma_mapping_error(priv->dev, map))) {
412 if (net_ratelimit())
413 netdev_err(netdev, "failed to map rx page\n");
414 dev_kfree_skb_any(skb);
415 map = priv->rx_scratch_dma;
416 skb = NULL;
417 err = -ENOMEM;
418 }
419 }
420
421
422 priv->rx_skbs[entry] = skb;
423
424
425 rxdes->rxdes3 = cpu_to_le32(map);
426
427
428 dma_wmb();
429
430
431 if (entry == (priv->rx_q_entries - 1))
432 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
433 else
434 rxdes->rxdes0 = 0;
435
436 return err;
437}
438
439static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
440 unsigned int pointer)
441{
442 return (pointer + 1) & (priv->rx_q_entries - 1);
443}
444
445static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
446{
447 struct net_device *netdev = priv->netdev;
448
449 if (status & FTGMAC100_RXDES0_RX_ERR)
450 netdev->stats.rx_errors++;
451
452 if (status & FTGMAC100_RXDES0_CRC_ERR)
453 netdev->stats.rx_crc_errors++;
454
455 if (status & (FTGMAC100_RXDES0_FTL |
456 FTGMAC100_RXDES0_RUNT |
457 FTGMAC100_RXDES0_RX_ODD_NB))
458 netdev->stats.rx_length_errors++;
459}
460
461static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
462{
463 struct net_device *netdev = priv->netdev;
464 struct ftgmac100_rxdes *rxdes;
465 struct sk_buff *skb;
466 unsigned int pointer, size;
467 u32 status, csum_vlan;
468 dma_addr_t map;
469
470
471 pointer = priv->rx_pointer;
472 rxdes = &priv->rxdes[pointer];
473
474
475 status = le32_to_cpu(rxdes->rxdes0);
476
477
478 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
479 return false;
480
481
482 dma_rmb();
483
484
485 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
486 !(status & FTGMAC100_RXDES0_LRS)))
487 goto drop;
488
489
490 size = status & FTGMAC100_RXDES0_VDBC;
491 csum_vlan = le32_to_cpu(rxdes->rxdes1);
492
493
494 if (unlikely(status & RXDES0_ANY_ERROR)) {
495
496
497
498
499
500 if ((status & FTGMAC100_RXDES0_RUNT) &&
501 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
502 (size >= 60))
503 status &= ~FTGMAC100_RXDES0_RUNT;
504
505
506 if (status & RXDES0_ANY_ERROR) {
507 ftgmac100_rx_packet_error(priv, status);
508 goto drop;
509 }
510 }
511
512
513
514
515 skb = priv->rx_skbs[pointer];
516 if (!unlikely(skb)) {
517 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
518 goto drop;
519 }
520
521 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
522 netdev->stats.multicast++;
523
524
525
526
527
528
529
530 if (netdev->features & NETIF_F_RXCSUM) {
531 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
532 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
533 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
534 if ((csum_vlan & err_bits) ||
535 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
536 skb->ip_summed = CHECKSUM_NONE;
537 else
538 skb->ip_summed = CHECKSUM_UNNECESSARY;
539 }
540
541
542 skb_put(skb, size);
543
544
545 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
546 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
547 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
548 csum_vlan & 0xffff);
549
550
551 map = le32_to_cpu(rxdes->rxdes3);
552
553#if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
554
555
556
557
558 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
559#else
560 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
561#endif
562
563
564
565 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
566 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
567
568 skb->protocol = eth_type_trans(skb, netdev);
569
570 netdev->stats.rx_packets++;
571 netdev->stats.rx_bytes += size;
572
573
574 if (skb->ip_summed == CHECKSUM_NONE)
575 netif_receive_skb(skb);
576 else
577 napi_gro_receive(&priv->napi, skb);
578
579 (*processed)++;
580 return true;
581
582 drop:
583
584 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
585 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
586 netdev->stats.rx_dropped++;
587 return true;
588}
589
590static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
591 unsigned int index)
592{
593 if (index == (priv->tx_q_entries - 1))
594 return priv->txdes0_edotr_mask;
595 else
596 return 0;
597}
598
599static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
600 unsigned int pointer)
601{
602 return (pointer + 1) & (priv->tx_q_entries - 1);
603}
604
605static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
606{
607
608
609
610
611
612
613 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
614 (priv->tx_q_entries - 1);
615}
616
617static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
618{
619 return priv->tx_pointer != priv->tx_clean_pointer;
620}
621
622static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
623 unsigned int pointer,
624 struct sk_buff *skb,
625 struct ftgmac100_txdes *txdes,
626 u32 ctl_stat)
627{
628 dma_addr_t map = le32_to_cpu(txdes->txdes3);
629 size_t len;
630
631 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
632 len = skb_headlen(skb);
633 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
634 } else {
635 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
636 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
637 }
638
639
640 if (ctl_stat & FTGMAC100_TXDES0_LTS)
641 dev_kfree_skb(skb);
642 priv->tx_skbs[pointer] = NULL;
643}
644
645static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
646{
647 struct net_device *netdev = priv->netdev;
648 struct ftgmac100_txdes *txdes;
649 struct sk_buff *skb;
650 unsigned int pointer;
651 u32 ctl_stat;
652
653 pointer = priv->tx_clean_pointer;
654 txdes = &priv->txdes[pointer];
655
656 ctl_stat = le32_to_cpu(txdes->txdes0);
657 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
658 return false;
659
660 skb = priv->tx_skbs[pointer];
661 netdev->stats.tx_packets++;
662 netdev->stats.tx_bytes += skb->len;
663 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
664 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
665
666 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
667
668 return true;
669}
670
671static void ftgmac100_tx_complete(struct ftgmac100 *priv)
672{
673 struct net_device *netdev = priv->netdev;
674
675
676 while (ftgmac100_tx_buf_cleanable(priv) &&
677 ftgmac100_tx_complete_packet(priv))
678 ;
679
680
681 smp_mb();
682 if (unlikely(netif_queue_stopped(netdev) &&
683 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
684 struct netdev_queue *txq;
685
686 txq = netdev_get_tx_queue(netdev, 0);
687 __netif_tx_lock(txq, smp_processor_id());
688 if (netif_queue_stopped(netdev) &&
689 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
690 netif_wake_queue(netdev);
691 __netif_tx_unlock(txq);
692 }
693}
694
695static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
696{
697 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
698 u8 ip_proto = ip_hdr(skb)->protocol;
699
700 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
701 switch(ip_proto) {
702 case IPPROTO_TCP:
703 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
704 return true;
705 case IPPROTO_UDP:
706 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
707 return true;
708 case IPPROTO_IP:
709 return true;
710 }
711 }
712 return skb_checksum_help(skb) == 0;
713}
714
715static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
716 struct net_device *netdev)
717{
718 struct ftgmac100 *priv = netdev_priv(netdev);
719 struct ftgmac100_txdes *txdes, *first;
720 unsigned int pointer, nfrags, len, i, j;
721 u32 f_ctl_stat, ctl_stat, csum_vlan;
722 dma_addr_t map;
723
724
725 if (eth_skb_pad(skb)) {
726 netdev->stats.tx_dropped++;
727 return NETDEV_TX_OK;
728 }
729
730
731 if (unlikely(skb->len > MAX_PKT_SIZE)) {
732 if (net_ratelimit())
733 netdev_dbg(netdev, "tx packet too big\n");
734 goto drop;
735 }
736
737
738
739
740 nfrags = skb_shinfo(skb)->nr_frags;
741
742
743 len = skb_headlen(skb);
744
745
746 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
747 if (dma_mapping_error(priv->dev, map)) {
748 if (net_ratelimit())
749 netdev_err(netdev, "map tx packet head failed\n");
750 goto drop;
751 }
752
753
754 pointer = priv->tx_pointer;
755 txdes = first = &priv->txdes[pointer];
756
757
758
759
760 priv->tx_skbs[pointer] = skb;
761 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
762 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
763 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
764 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
765 if (nfrags == 0)
766 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
767 txdes->txdes3 = cpu_to_le32(map);
768
769
770 csum_vlan = 0;
771 if (skb->ip_summed == CHECKSUM_PARTIAL &&
772 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
773 goto drop;
774
775
776 if (skb_vlan_tag_present(skb)) {
777 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
778 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
779 }
780
781 txdes->txdes1 = cpu_to_le32(csum_vlan);
782
783
784 pointer = ftgmac100_next_tx_pointer(priv, pointer);
785
786
787 for (i = 0; i < nfrags; i++) {
788 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
789
790 len = frag->size;
791
792
793 map = skb_frag_dma_map(priv->dev, frag, 0, len,
794 DMA_TO_DEVICE);
795 if (dma_mapping_error(priv->dev, map))
796 goto dma_err;
797
798
799 priv->tx_skbs[pointer] = skb;
800 txdes = &priv->txdes[pointer];
801 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
802 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
803 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
804 if (i == (nfrags - 1))
805 ctl_stat |= FTGMAC100_TXDES0_LTS;
806 txdes->txdes0 = cpu_to_le32(ctl_stat);
807 txdes->txdes1 = 0;
808 txdes->txdes3 = cpu_to_le32(map);
809
810
811 pointer = ftgmac100_next_tx_pointer(priv, pointer);
812 }
813
814
815
816
817 dma_wmb();
818 first->txdes0 = cpu_to_le32(f_ctl_stat);
819
820
821 priv->tx_pointer = pointer;
822
823
824
825
826
827 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
828 netif_stop_queue(netdev);
829
830 smp_mb();
831 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
832 netif_wake_queue(netdev);
833 }
834
835
836 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
837
838 return NETDEV_TX_OK;
839
840 dma_err:
841 if (net_ratelimit())
842 netdev_err(netdev, "map tx fragment failed\n");
843
844
845 pointer = priv->tx_pointer;
846 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
847 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
848
849
850 for (j = 0; j < i; j++) {
851 pointer = ftgmac100_next_tx_pointer(priv, pointer);
852 txdes = &priv->txdes[pointer];
853 ctl_stat = le32_to_cpu(txdes->txdes0);
854 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
855 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
856 }
857
858
859
860
861
862 drop:
863
864 dev_kfree_skb_any(skb);
865 netdev->stats.tx_dropped++;
866
867 return NETDEV_TX_OK;
868}
869
870static void ftgmac100_free_buffers(struct ftgmac100 *priv)
871{
872 int i;
873
874
875 for (i = 0; i < priv->rx_q_entries; i++) {
876 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
877 struct sk_buff *skb = priv->rx_skbs[i];
878 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
879
880 if (!skb)
881 continue;
882
883 priv->rx_skbs[i] = NULL;
884 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
885 dev_kfree_skb_any(skb);
886 }
887
888
889 for (i = 0; i < priv->tx_q_entries; i++) {
890 struct ftgmac100_txdes *txdes = &priv->txdes[i];
891 struct sk_buff *skb = priv->tx_skbs[i];
892
893 if (!skb)
894 continue;
895 ftgmac100_free_tx_packet(priv, i, skb, txdes,
896 le32_to_cpu(txdes->txdes0));
897 }
898}
899
900static void ftgmac100_free_rings(struct ftgmac100 *priv)
901{
902
903 kfree(priv->rx_skbs);
904 kfree(priv->tx_skbs);
905
906
907 if (priv->rxdes)
908 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
909 sizeof(struct ftgmac100_rxdes),
910 priv->rxdes, priv->rxdes_dma);
911 priv->rxdes = NULL;
912
913 if (priv->txdes)
914 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
915 sizeof(struct ftgmac100_txdes),
916 priv->txdes, priv->txdes_dma);
917 priv->txdes = NULL;
918
919
920 if (priv->rx_scratch)
921 dma_free_coherent(priv->dev, RX_BUF_SIZE,
922 priv->rx_scratch, priv->rx_scratch_dma);
923}
924
925static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
926{
927
928 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
929 GFP_KERNEL);
930 if (!priv->rx_skbs)
931 return -ENOMEM;
932 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
933 GFP_KERNEL);
934 if (!priv->tx_skbs)
935 return -ENOMEM;
936
937
938 priv->rxdes = dma_alloc_coherent(priv->dev,
939 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
940 &priv->rxdes_dma, GFP_KERNEL);
941 if (!priv->rxdes)
942 return -ENOMEM;
943 priv->txdes = dma_alloc_coherent(priv->dev,
944 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
945 &priv->txdes_dma, GFP_KERNEL);
946 if (!priv->txdes)
947 return -ENOMEM;
948
949
950 priv->rx_scratch = dma_alloc_coherent(priv->dev,
951 RX_BUF_SIZE,
952 &priv->rx_scratch_dma,
953 GFP_KERNEL);
954 if (!priv->rx_scratch)
955 return -ENOMEM;
956
957 return 0;
958}
959
960static void ftgmac100_init_rings(struct ftgmac100 *priv)
961{
962 struct ftgmac100_rxdes *rxdes = NULL;
963 struct ftgmac100_txdes *txdes = NULL;
964 int i;
965
966
967 priv->rx_q_entries = priv->new_rx_q_entries;
968 priv->tx_q_entries = priv->new_tx_q_entries;
969
970 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
971 return;
972
973
974 for (i = 0; i < priv->rx_q_entries; i++) {
975 rxdes = &priv->rxdes[i];
976 rxdes->rxdes0 = 0;
977 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
978 }
979
980 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
981
982 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
983 return;
984
985
986 for (i = 0; i < priv->tx_q_entries; i++) {
987 txdes = &priv->txdes[i];
988 txdes->txdes0 = 0;
989 }
990 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
991}
992
993static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
994{
995 int i;
996
997 for (i = 0; i < priv->rx_q_entries; i++) {
998 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
999
1000 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
1001 return -ENOMEM;
1002 }
1003 return 0;
1004}
1005
1006static void ftgmac100_adjust_link(struct net_device *netdev)
1007{
1008 struct ftgmac100 *priv = netdev_priv(netdev);
1009 struct phy_device *phydev = netdev->phydev;
1010 bool tx_pause, rx_pause;
1011 int new_speed;
1012
1013
1014 if (!phydev->link)
1015 new_speed = 0;
1016 else
1017 new_speed = phydev->speed;
1018
1019
1020 if (priv->aneg_pause) {
1021 rx_pause = tx_pause = phydev->pause;
1022 if (phydev->asym_pause)
1023 tx_pause = !rx_pause;
1024 } else {
1025 rx_pause = priv->rx_pause;
1026 tx_pause = priv->tx_pause;
1027 }
1028
1029
1030 if (phydev->speed == priv->cur_speed &&
1031 phydev->duplex == priv->cur_duplex &&
1032 rx_pause == priv->rx_pause &&
1033 tx_pause == priv->tx_pause)
1034 return;
1035
1036
1037
1038
1039 if (new_speed || priv->cur_speed)
1040 phy_print_status(phydev);
1041
1042 priv->cur_speed = new_speed;
1043 priv->cur_duplex = phydev->duplex;
1044 priv->rx_pause = rx_pause;
1045 priv->tx_pause = tx_pause;
1046
1047
1048 if (!new_speed)
1049 return;
1050
1051
1052 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1053
1054
1055 schedule_work(&priv->reset_task);
1056}
1057
1058static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf)
1059{
1060 struct net_device *netdev = priv->netdev;
1061 struct phy_device *phydev;
1062
1063 phydev = phy_find_first(priv->mii_bus);
1064 if (!phydev) {
1065 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1066 return -ENODEV;
1067 }
1068
1069 phydev = phy_connect(netdev, phydev_name(phydev),
1070 &ftgmac100_adjust_link, intf);
1071
1072 if (IS_ERR(phydev)) {
1073 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1074 return PTR_ERR(phydev);
1075 }
1076
1077
1078
1079
1080 phy_support_asym_pause(phydev);
1081
1082
1083 phy_attached_info(phydev);
1084
1085 return 0;
1086}
1087
1088static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1089{
1090 struct net_device *netdev = bus->priv;
1091 struct ftgmac100 *priv = netdev_priv(netdev);
1092 unsigned int phycr;
1093 int i;
1094
1095 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1096
1097
1098 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1099
1100 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1101 FTGMAC100_PHYCR_REGAD(regnum) |
1102 FTGMAC100_PHYCR_MIIRD;
1103
1104 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1105
1106 for (i = 0; i < 10; i++) {
1107 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1108
1109 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1110 int data;
1111
1112 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1113 return FTGMAC100_PHYDATA_MIIRDATA(data);
1114 }
1115
1116 udelay(100);
1117 }
1118
1119 netdev_err(netdev, "mdio read timed out\n");
1120 return -EIO;
1121}
1122
1123static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1124 int regnum, u16 value)
1125{
1126 struct net_device *netdev = bus->priv;
1127 struct ftgmac100 *priv = netdev_priv(netdev);
1128 unsigned int phycr;
1129 int data;
1130 int i;
1131
1132 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1133
1134
1135 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1136
1137 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1138 FTGMAC100_PHYCR_REGAD(regnum) |
1139 FTGMAC100_PHYCR_MIIWR;
1140
1141 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1142
1143 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1144 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1145
1146 for (i = 0; i < 10; i++) {
1147 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1148
1149 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1150 return 0;
1151
1152 udelay(100);
1153 }
1154
1155 netdev_err(netdev, "mdio write timed out\n");
1156 return -EIO;
1157}
1158
1159static void ftgmac100_get_drvinfo(struct net_device *netdev,
1160 struct ethtool_drvinfo *info)
1161{
1162 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1163 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1164 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1165}
1166
1167static void ftgmac100_get_ringparam(struct net_device *netdev,
1168 struct ethtool_ringparam *ering)
1169{
1170 struct ftgmac100 *priv = netdev_priv(netdev);
1171
1172 memset(ering, 0, sizeof(*ering));
1173 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1174 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1175 ering->rx_pending = priv->rx_q_entries;
1176 ering->tx_pending = priv->tx_q_entries;
1177}
1178
1179static int ftgmac100_set_ringparam(struct net_device *netdev,
1180 struct ethtool_ringparam *ering)
1181{
1182 struct ftgmac100 *priv = netdev_priv(netdev);
1183
1184 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1185 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1186 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1187 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1188 !is_power_of_2(ering->rx_pending) ||
1189 !is_power_of_2(ering->tx_pending))
1190 return -EINVAL;
1191
1192 priv->new_rx_q_entries = ering->rx_pending;
1193 priv->new_tx_q_entries = ering->tx_pending;
1194 if (netif_running(netdev))
1195 schedule_work(&priv->reset_task);
1196
1197 return 0;
1198}
1199
1200static void ftgmac100_get_pauseparam(struct net_device *netdev,
1201 struct ethtool_pauseparam *pause)
1202{
1203 struct ftgmac100 *priv = netdev_priv(netdev);
1204
1205 pause->autoneg = priv->aneg_pause;
1206 pause->tx_pause = priv->tx_pause;
1207 pause->rx_pause = priv->rx_pause;
1208}
1209
1210static int ftgmac100_set_pauseparam(struct net_device *netdev,
1211 struct ethtool_pauseparam *pause)
1212{
1213 struct ftgmac100 *priv = netdev_priv(netdev);
1214 struct phy_device *phydev = netdev->phydev;
1215
1216 priv->aneg_pause = pause->autoneg;
1217 priv->tx_pause = pause->tx_pause;
1218 priv->rx_pause = pause->rx_pause;
1219
1220 if (phydev)
1221 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1222
1223 if (netif_running(netdev)) {
1224 if (!(phydev && priv->aneg_pause))
1225 ftgmac100_config_pause(priv);
1226 }
1227
1228 return 0;
1229}
1230
1231static const struct ethtool_ops ftgmac100_ethtool_ops = {
1232 .get_drvinfo = ftgmac100_get_drvinfo,
1233 .get_link = ethtool_op_get_link,
1234 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1235 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1236 .nway_reset = phy_ethtool_nway_reset,
1237 .get_ringparam = ftgmac100_get_ringparam,
1238 .set_ringparam = ftgmac100_set_ringparam,
1239 .get_pauseparam = ftgmac100_get_pauseparam,
1240 .set_pauseparam = ftgmac100_set_pauseparam,
1241};
1242
1243static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1244{
1245 struct net_device *netdev = dev_id;
1246 struct ftgmac100 *priv = netdev_priv(netdev);
1247 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1248
1249
1250 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1251 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1252 if (unlikely(status & FTGMAC100_INT_BAD)) {
1253
1254
1255 if (status & FTGMAC100_INT_NO_RXBUF)
1256 netdev->stats.rx_over_errors++;
1257
1258
1259 if (status & FTGMAC100_INT_RPKT_LOST)
1260 netdev->stats.rx_fifo_errors++;
1261
1262
1263 if (status & FTGMAC100_INT_XPKT_LOST)
1264 netdev->stats.tx_fifo_errors++;
1265
1266
1267 if (status & FTGMAC100_INT_AHB_ERR) {
1268 if (net_ratelimit())
1269 netdev_warn(netdev,
1270 "AHB bus error ! Resetting chip.\n");
1271 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1272 schedule_work(&priv->reset_task);
1273 return IRQ_HANDLED;
1274 }
1275
1276
1277
1278
1279 priv->need_mac_restart = true;
1280
1281
1282 new_mask &= ~status;
1283 }
1284
1285
1286 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1287
1288
1289 napi_schedule_irqoff(&priv->napi);
1290
1291 return IRQ_HANDLED;
1292}
1293
1294static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1295{
1296 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1297
1298
1299 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1300}
1301
1302static int ftgmac100_poll(struct napi_struct *napi, int budget)
1303{
1304 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1305 int work_done = 0;
1306 bool more;
1307
1308
1309 if (ftgmac100_tx_buf_cleanable(priv))
1310 ftgmac100_tx_complete(priv);
1311
1312
1313 do {
1314 more = ftgmac100_rx_packet(priv, &work_done);
1315 } while (more && work_done < budget);
1316
1317
1318
1319
1320
1321 if (unlikely(priv->need_mac_restart)) {
1322 ftgmac100_start_hw(priv);
1323
1324
1325 iowrite32(FTGMAC100_INT_BAD,
1326 priv->base + FTGMAC100_OFFSET_IER);
1327 }
1328
1329
1330
1331
1332 if (ftgmac100_tx_buf_cleanable(priv))
1333 work_done = budget;
1334
1335 if (work_done < budget) {
1336
1337
1338
1339
1340
1341 iowrite32(FTGMAC100_INT_RXTX,
1342 priv->base + FTGMAC100_OFFSET_ISR);
1343
1344
1345
1346
1347 ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1348
1349
1350 if (ftgmac100_check_rx(priv) ||
1351 ftgmac100_tx_buf_cleanable(priv))
1352 return budget;
1353
1354
1355 napi_complete(napi);
1356
1357
1358 iowrite32(FTGMAC100_INT_ALL,
1359 priv->base + FTGMAC100_OFFSET_IER);
1360 }
1361
1362 return work_done;
1363}
1364
1365static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1366{
1367 int err = 0;
1368
1369
1370 ftgmac100_init_rings(priv);
1371
1372
1373 err = ftgmac100_alloc_rx_buffers(priv);
1374 if (err && !ignore_alloc_err)
1375 return err;
1376
1377
1378 ftgmac100_init_hw(priv);
1379 ftgmac100_config_pause(priv);
1380 ftgmac100_start_hw(priv);
1381
1382
1383 napi_enable(&priv->napi);
1384 netif_start_queue(priv->netdev);
1385
1386
1387 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1388
1389 return err;
1390}
1391
1392static void ftgmac100_reset_task(struct work_struct *work)
1393{
1394 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1395 reset_task);
1396 struct net_device *netdev = priv->netdev;
1397 int err;
1398
1399 netdev_dbg(netdev, "Resetting NIC...\n");
1400
1401
1402 rtnl_lock();
1403 if (netdev->phydev)
1404 mutex_lock(&netdev->phydev->lock);
1405 if (priv->mii_bus)
1406 mutex_lock(&priv->mii_bus->mdio_lock);
1407
1408
1409
1410 if (!netif_running(netdev))
1411 goto bail;
1412
1413
1414 netif_trans_update(netdev);
1415 napi_disable(&priv->napi);
1416 netif_tx_disable(netdev);
1417
1418
1419 ftgmac100_stop_hw(priv);
1420 err = ftgmac100_reset_and_config_mac(priv);
1421 if (err) {
1422
1423 netdev_err(netdev, "attempting to continue...\n");
1424 }
1425
1426
1427 ftgmac100_free_buffers(priv);
1428
1429
1430 ftgmac100_init_all(priv, true);
1431
1432 netdev_dbg(netdev, "Reset done !\n");
1433 bail:
1434 if (priv->mii_bus)
1435 mutex_unlock(&priv->mii_bus->mdio_lock);
1436 if (netdev->phydev)
1437 mutex_unlock(&netdev->phydev->lock);
1438 rtnl_unlock();
1439}
1440
1441static int ftgmac100_open(struct net_device *netdev)
1442{
1443 struct ftgmac100 *priv = netdev_priv(netdev);
1444 int err;
1445
1446
1447 err = ftgmac100_alloc_rings(priv);
1448 if (err) {
1449 netdev_err(netdev, "Failed to allocate descriptors\n");
1450 return err;
1451 }
1452
1453
1454
1455
1456
1457
1458
1459 if (priv->use_ncsi) {
1460 priv->cur_duplex = DUPLEX_FULL;
1461 priv->cur_speed = SPEED_100;
1462 } else {
1463 priv->cur_duplex = 0;
1464 priv->cur_speed = 0;
1465 }
1466
1467
1468 err = ftgmac100_reset_and_config_mac(priv);
1469 if (err)
1470 goto err_hw;
1471
1472
1473 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1474
1475
1476 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1477 if (err) {
1478 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1479 goto err_irq;
1480 }
1481
1482
1483 err = ftgmac100_init_all(priv, false);
1484 if (err) {
1485 netdev_err(netdev, "Failed to allocate packet buffers\n");
1486 goto err_alloc;
1487 }
1488
1489 if (netdev->phydev) {
1490
1491 phy_start(netdev->phydev);
1492 } else if (priv->use_ncsi) {
1493
1494 netif_carrier_on(netdev);
1495
1496
1497 err = ncsi_start_dev(priv->ndev);
1498 if (err)
1499 goto err_ncsi;
1500 }
1501
1502 return 0;
1503
1504 err_ncsi:
1505 napi_disable(&priv->napi);
1506 netif_stop_queue(netdev);
1507 err_alloc:
1508 ftgmac100_free_buffers(priv);
1509 free_irq(netdev->irq, netdev);
1510 err_irq:
1511 netif_napi_del(&priv->napi);
1512 err_hw:
1513 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1514 ftgmac100_free_rings(priv);
1515 return err;
1516}
1517
1518static int ftgmac100_stop(struct net_device *netdev)
1519{
1520 struct ftgmac100 *priv = netdev_priv(netdev);
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1532
1533 netif_stop_queue(netdev);
1534 napi_disable(&priv->napi);
1535 netif_napi_del(&priv->napi);
1536 if (netdev->phydev)
1537 phy_stop(netdev->phydev);
1538 else if (priv->use_ncsi)
1539 ncsi_stop_dev(priv->ndev);
1540
1541 ftgmac100_stop_hw(priv);
1542 free_irq(netdev->irq, netdev);
1543 ftgmac100_free_buffers(priv);
1544 ftgmac100_free_rings(priv);
1545
1546 return 0;
1547}
1548
1549
1550static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1551{
1552 if (!netdev->phydev)
1553 return -ENXIO;
1554
1555 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1556}
1557
1558static void ftgmac100_tx_timeout(struct net_device *netdev)
1559{
1560 struct ftgmac100 *priv = netdev_priv(netdev);
1561
1562
1563 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1564
1565
1566 schedule_work(&priv->reset_task);
1567}
1568
1569static int ftgmac100_set_features(struct net_device *netdev,
1570 netdev_features_t features)
1571{
1572 struct ftgmac100 *priv = netdev_priv(netdev);
1573 netdev_features_t changed = netdev->features ^ features;
1574
1575 if (!netif_running(netdev))
1576 return 0;
1577
1578
1579 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1580 u32 maccr;
1581
1582 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1583 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1584 maccr |= FTGMAC100_MACCR_RM_VLAN;
1585 else
1586 maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1587 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1588 }
1589
1590 return 0;
1591}
1592
1593#ifdef CONFIG_NET_POLL_CONTROLLER
1594static void ftgmac100_poll_controller(struct net_device *netdev)
1595{
1596 unsigned long flags;
1597
1598 local_irq_save(flags);
1599 ftgmac100_interrupt(netdev->irq, netdev);
1600 local_irq_restore(flags);
1601}
1602#endif
1603
1604static const struct net_device_ops ftgmac100_netdev_ops = {
1605 .ndo_open = ftgmac100_open,
1606 .ndo_stop = ftgmac100_stop,
1607 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1608 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1609 .ndo_validate_addr = eth_validate_addr,
1610 .ndo_do_ioctl = ftgmac100_do_ioctl,
1611 .ndo_tx_timeout = ftgmac100_tx_timeout,
1612 .ndo_set_rx_mode = ftgmac100_set_rx_mode,
1613 .ndo_set_features = ftgmac100_set_features,
1614#ifdef CONFIG_NET_POLL_CONTROLLER
1615 .ndo_poll_controller = ftgmac100_poll_controller,
1616#endif
1617 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid,
1618 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid,
1619};
1620
1621static int ftgmac100_setup_mdio(struct net_device *netdev)
1622{
1623 struct ftgmac100 *priv = netdev_priv(netdev);
1624 struct platform_device *pdev = to_platform_device(priv->dev);
1625 int phy_intf = PHY_INTERFACE_MODE_RGMII;
1626 struct device_node *np = pdev->dev.of_node;
1627 int i, err = 0;
1628 u32 reg;
1629
1630
1631 priv->mii_bus = mdiobus_alloc();
1632 if (!priv->mii_bus)
1633 return -EIO;
1634
1635 if (priv->is_aspeed) {
1636
1637 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1638 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1639 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1640 };
1641
1642
1643 if (np) {
1644
1645 phy_intf = of_get_phy_mode(np);
1646 if (phy_intf < 0)
1647 phy_intf = PHY_INTERFACE_MODE_RGMII;
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663 if (priv->is_aspeed &&
1664 phy_intf != PHY_INTERFACE_MODE_RMII &&
1665 phy_intf != PHY_INTERFACE_MODE_RGMII &&
1666 phy_intf != PHY_INTERFACE_MODE_RGMII_ID &&
1667 phy_intf != PHY_INTERFACE_MODE_RGMII_RXID &&
1668 phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) {
1669 netdev_warn(netdev,
1670 "Unsupported PHY mode %s !\n",
1671 phy_modes(phy_intf));
1672 }
1673 }
1674
1675 priv->mii_bus->name = "ftgmac100_mdio";
1676 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1677 pdev->name, pdev->id);
1678 priv->mii_bus->parent = priv->dev;
1679 priv->mii_bus->priv = priv->netdev;
1680 priv->mii_bus->read = ftgmac100_mdiobus_read;
1681 priv->mii_bus->write = ftgmac100_mdiobus_write;
1682
1683 for (i = 0; i < PHY_MAX_ADDR; i++)
1684 priv->mii_bus->irq[i] = PHY_POLL;
1685
1686 err = mdiobus_register(priv->mii_bus);
1687 if (err) {
1688 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1689 goto err_register_mdiobus;
1690 }
1691
1692 err = ftgmac100_mii_probe(priv, phy_intf);
1693 if (err) {
1694 dev_err(priv->dev, "MII Probe failed!\n");
1695 goto err_mii_probe;
1696 }
1697
1698 return 0;
1699
1700err_mii_probe:
1701 mdiobus_unregister(priv->mii_bus);
1702err_register_mdiobus:
1703 mdiobus_free(priv->mii_bus);
1704 return err;
1705}
1706
1707static void ftgmac100_destroy_mdio(struct net_device *netdev)
1708{
1709 struct ftgmac100 *priv = netdev_priv(netdev);
1710
1711 if (!netdev->phydev)
1712 return;
1713
1714 phy_disconnect(netdev->phydev);
1715 mdiobus_unregister(priv->mii_bus);
1716 mdiobus_free(priv->mii_bus);
1717}
1718
1719static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1720{
1721 if (unlikely(nd->state != ncsi_dev_state_functional))
1722 return;
1723
1724 netdev_dbg(nd->dev, "NCSI interface %s\n",
1725 nd->link_up ? "up" : "down");
1726}
1727
1728static void ftgmac100_setup_clk(struct ftgmac100 *priv)
1729{
1730 priv->clk = devm_clk_get(priv->dev, NULL);
1731 if (IS_ERR(priv->clk))
1732 return;
1733
1734 clk_prepare_enable(priv->clk);
1735
1736
1737
1738
1739
1740 clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1741 FTGMAC_100MHZ);
1742}
1743
1744static int ftgmac100_probe(struct platform_device *pdev)
1745{
1746 struct resource *res;
1747 int irq;
1748 struct net_device *netdev;
1749 struct ftgmac100 *priv;
1750 struct device_node *np;
1751 int err = 0;
1752
1753 if (!pdev)
1754 return -ENODEV;
1755
1756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1757 if (!res)
1758 return -ENXIO;
1759
1760 irq = platform_get_irq(pdev, 0);
1761 if (irq < 0)
1762 return irq;
1763
1764
1765 netdev = alloc_etherdev(sizeof(*priv));
1766 if (!netdev) {
1767 err = -ENOMEM;
1768 goto err_alloc_etherdev;
1769 }
1770
1771 SET_NETDEV_DEV(netdev, &pdev->dev);
1772
1773 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1774 netdev->netdev_ops = &ftgmac100_netdev_ops;
1775 netdev->watchdog_timeo = 5 * HZ;
1776
1777 platform_set_drvdata(pdev, netdev);
1778
1779
1780 priv = netdev_priv(netdev);
1781 priv->netdev = netdev;
1782 priv->dev = &pdev->dev;
1783 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1784
1785
1786 priv->res = request_mem_region(res->start, resource_size(res),
1787 dev_name(&pdev->dev));
1788 if (!priv->res) {
1789 dev_err(&pdev->dev, "Could not reserve memory region\n");
1790 err = -ENOMEM;
1791 goto err_req_mem;
1792 }
1793
1794 priv->base = ioremap(res->start, resource_size(res));
1795 if (!priv->base) {
1796 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1797 err = -EIO;
1798 goto err_ioremap;
1799 }
1800
1801 netdev->irq = irq;
1802
1803
1804 priv->tx_pause = true;
1805 priv->rx_pause = true;
1806 priv->aneg_pause = true;
1807
1808
1809 ftgmac100_initial_mac(priv);
1810
1811 np = pdev->dev.of_node;
1812 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1813 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1814 priv->rxdes0_edorr_mask = BIT(30);
1815 priv->txdes0_edotr_mask = BIT(30);
1816 priv->is_aspeed = true;
1817 } else {
1818 priv->rxdes0_edorr_mask = BIT(15);
1819 priv->txdes0_edotr_mask = BIT(15);
1820 }
1821
1822 if (np && of_get_property(np, "use-ncsi", NULL)) {
1823 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1824 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1825 goto err_ncsi_dev;
1826 }
1827
1828 dev_info(&pdev->dev, "Using NCSI interface\n");
1829 priv->use_ncsi = true;
1830 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1831 if (!priv->ndev)
1832 goto err_ncsi_dev;
1833 } else {
1834 priv->use_ncsi = false;
1835 err = ftgmac100_setup_mdio(netdev);
1836 if (err)
1837 goto err_setup_mdio;
1838 }
1839
1840 if (priv->is_aspeed)
1841 ftgmac100_setup_clk(priv);
1842
1843
1844 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1845 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1846
1847
1848 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1849 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1850 NETIF_F_HW_VLAN_CTAG_TX;
1851
1852 if (priv->use_ncsi)
1853 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1854
1855
1856 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1857 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1858 if (np && of_get_property(np, "no-hw-checksum", NULL))
1859 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1860 netdev->features |= netdev->hw_features;
1861
1862
1863 err = register_netdev(netdev);
1864 if (err) {
1865 dev_err(&pdev->dev, "Failed to register netdev\n");
1866 goto err_register_netdev;
1867 }
1868
1869 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1870
1871 return 0;
1872
1873err_ncsi_dev:
1874err_register_netdev:
1875 ftgmac100_destroy_mdio(netdev);
1876err_setup_mdio:
1877 iounmap(priv->base);
1878err_ioremap:
1879 release_resource(priv->res);
1880err_req_mem:
1881 free_netdev(netdev);
1882err_alloc_etherdev:
1883 return err;
1884}
1885
1886static int ftgmac100_remove(struct platform_device *pdev)
1887{
1888 struct net_device *netdev;
1889 struct ftgmac100 *priv;
1890
1891 netdev = platform_get_drvdata(pdev);
1892 priv = netdev_priv(netdev);
1893
1894 unregister_netdev(netdev);
1895
1896 clk_disable_unprepare(priv->clk);
1897
1898
1899
1900
1901 cancel_work_sync(&priv->reset_task);
1902
1903 ftgmac100_destroy_mdio(netdev);
1904
1905 iounmap(priv->base);
1906 release_resource(priv->res);
1907
1908 netif_napi_del(&priv->napi);
1909 free_netdev(netdev);
1910 return 0;
1911}
1912
1913static const struct of_device_id ftgmac100_of_match[] = {
1914 { .compatible = "faraday,ftgmac100" },
1915 { }
1916};
1917MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1918
1919static struct platform_driver ftgmac100_driver = {
1920 .probe = ftgmac100_probe,
1921 .remove = ftgmac100_remove,
1922 .driver = {
1923 .name = DRV_NAME,
1924 .of_match_table = ftgmac100_of_match,
1925 },
1926};
1927module_platform_driver(ftgmac100_driver);
1928
1929MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1930MODULE_DESCRIPTION("FTGMAC100 driver");
1931MODULE_LICENSE("GPL");
1932