1
2
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/types.h>
7#include <linux/pci.h>
8#include <linux/netdevice.h>
9#include <linux/etherdevice.h>
10#include <linux/slab.h>
11#include <linux/device.h>
12#include <linux/skbuff.h>
13#include <linux/if_vlan.h>
14#include <net/switchdev.h>
15
16#include "pci.h"
17#include "core.h"
18#include "reg.h"
19#include "port.h"
20#include "trap.h"
21#include "txheader.h"
22#include "ib.h"
23
24static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
25static const char mlxsw_sx_driver_version[] = "1.0";
26
27struct mlxsw_sx_port;
28
29struct mlxsw_sx {
30 struct mlxsw_sx_port **ports;
31 struct mlxsw_core *core;
32 const struct mlxsw_bus_info *bus_info;
33 u8 hw_id[ETH_ALEN];
34};
35
36struct mlxsw_sx_port_pcpu_stats {
37 u64 rx_packets;
38 u64 rx_bytes;
39 u64 tx_packets;
40 u64 tx_bytes;
41 struct u64_stats_sync syncp;
42 u32 tx_dropped;
43};
44
45struct mlxsw_sx_port {
46 struct net_device *dev;
47 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
48 struct mlxsw_sx *mlxsw_sx;
49 u8 local_port;
50 struct {
51 u8 module;
52 } mapping;
53};
54
55
56
57
58
59MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
60
61
62
63
64
65
66MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
67
68
69
70
71MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
72
73
74
75
76
77
78MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
79
80
81
82
83MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
84
85
86
87
88
89
90
91
92
93MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
94
95
96
97
98MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
99
100
101
102
103
104MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
105
106
107
108
109MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
110
111
112
113
114MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
115
116
117
118
119MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
120
121
122
123
124MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
125
126
127
128
129
130MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
131
132static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
133 const struct mlxsw_tx_info *tx_info)
134{
135 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
136 bool is_emad = tx_info->is_emad;
137
138 memset(txhdr, 0, MLXSW_TXHDR_LEN);
139
140
141 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
142 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
143 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
144 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
145 MLXSW_TXHDR_ETCLASS_5);
146 mlxsw_tx_hdr_swid_set(txhdr, 0);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
149 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
150 MLXSW_TXHDR_RDQ_OTHER);
151 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
152 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
153 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
154 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
155 MLXSW_TXHDR_NOT_EMAD);
156 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
157}
158
159static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
160 bool is_up)
161{
162 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
163 char paos_pl[MLXSW_REG_PAOS_LEN];
164
165 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
166 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
167 MLXSW_PORT_ADMIN_STATUS_DOWN);
168 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
169}
170
171static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
172 bool *p_is_up)
173{
174 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
175 char paos_pl[MLXSW_REG_PAOS_LEN];
176 u8 oper_status;
177 int err;
178
179 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
180 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
181 if (err)
182 return err;
183 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
184 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
185 return 0;
186}
187
188static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
189 u16 mtu)
190{
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char pmtu_pl[MLXSW_REG_PMTU_LEN];
193 int max_mtu;
194 int err;
195
196 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
197 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
198 if (err)
199 return err;
200 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
201
202 if (mtu > max_mtu)
203 return -EINVAL;
204
205 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
206 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
207}
208
209static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
210 u16 mtu)
211{
212 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
213 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
214}
215
216static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
217 u16 mtu)
218{
219 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
220}
221
222static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
223 u8 ib_port)
224{
225 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
226 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
227 int err;
228
229 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
230 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
231 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
232 return err;
233}
234
235static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
236{
237 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
238 char pspa_pl[MLXSW_REG_PSPA_LEN];
239
240 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
241 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
242}
243
244static int
245mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
246{
247 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
248 char sspr_pl[MLXSW_REG_SSPR_LEN];
249
250 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
251 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
252}
253
254static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
255 u8 local_port, u8 *p_module,
256 u8 *p_width)
257{
258 char pmlp_pl[MLXSW_REG_PMLP_LEN];
259 int err;
260
261 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
262 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
263 if (err)
264 return err;
265 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
266 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
267 return 0;
268}
269
270static int mlxsw_sx_port_open(struct net_device *dev)
271{
272 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
273 int err;
274
275 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
276 if (err)
277 return err;
278 netif_start_queue(dev);
279 return 0;
280}
281
282static int mlxsw_sx_port_stop(struct net_device *dev)
283{
284 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
285
286 netif_stop_queue(dev);
287 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
288}
289
290static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
291 struct net_device *dev)
292{
293 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
294 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
295 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
296 const struct mlxsw_tx_info tx_info = {
297 .local_port = mlxsw_sx_port->local_port,
298 .is_emad = false,
299 };
300 u64 len;
301 int err;
302
303 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
304 return NETDEV_TX_BUSY;
305
306 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
307 struct sk_buff *skb_orig = skb;
308
309 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
310 if (!skb) {
311 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
312 dev_kfree_skb_any(skb_orig);
313 return NETDEV_TX_OK;
314 }
315 dev_consume_skb_any(skb_orig);
316 }
317 mlxsw_sx_txhdr_construct(skb, &tx_info);
318
319
320
321 len = skb->len - MLXSW_TXHDR_LEN;
322
323
324
325 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
326
327 if (!err) {
328 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
329 u64_stats_update_begin(&pcpu_stats->syncp);
330 pcpu_stats->tx_packets++;
331 pcpu_stats->tx_bytes += len;
332 u64_stats_update_end(&pcpu_stats->syncp);
333 } else {
334 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
335 dev_kfree_skb_any(skb);
336 }
337 return NETDEV_TX_OK;
338}
339
340static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
341{
342 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
343 int err;
344
345 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
346 if (err)
347 return err;
348 dev->mtu = mtu;
349 return 0;
350}
351
352static void
353mlxsw_sx_port_get_stats64(struct net_device *dev,
354 struct rtnl_link_stats64 *stats)
355{
356 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
357 struct mlxsw_sx_port_pcpu_stats *p;
358 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
359 u32 tx_dropped = 0;
360 unsigned int start;
361 int i;
362
363 for_each_possible_cpu(i) {
364 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
365 do {
366 start = u64_stats_fetch_begin_irq(&p->syncp);
367 rx_packets = p->rx_packets;
368 rx_bytes = p->rx_bytes;
369 tx_packets = p->tx_packets;
370 tx_bytes = p->tx_bytes;
371 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
372
373 stats->rx_packets += rx_packets;
374 stats->rx_bytes += rx_bytes;
375 stats->tx_packets += tx_packets;
376 stats->tx_bytes += tx_bytes;
377
378 tx_dropped += p->tx_dropped;
379 }
380 stats->tx_dropped = tx_dropped;
381}
382
383static int mlxsw_sx_port_get_phys_port_name(struct net_device *dev, char *name,
384 size_t len)
385{
386 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
387
388 return mlxsw_core_port_get_phys_port_name(mlxsw_sx_port->mlxsw_sx->core,
389 mlxsw_sx_port->local_port,
390 name, len);
391}
392
393static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
394 .ndo_open = mlxsw_sx_port_open,
395 .ndo_stop = mlxsw_sx_port_stop,
396 .ndo_start_xmit = mlxsw_sx_port_xmit,
397 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
398 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
399 .ndo_get_phys_port_name = mlxsw_sx_port_get_phys_port_name,
400};
401
402static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
403 struct ethtool_drvinfo *drvinfo)
404{
405 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
406 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
407
408 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
409 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
410 sizeof(drvinfo->version));
411 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
412 "%d.%d.%d",
413 mlxsw_sx->bus_info->fw_rev.major,
414 mlxsw_sx->bus_info->fw_rev.minor,
415 mlxsw_sx->bus_info->fw_rev.subminor);
416 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
417 sizeof(drvinfo->bus_info));
418}
419
420struct mlxsw_sx_port_hw_stats {
421 char str[ETH_GSTRING_LEN];
422 u64 (*getter)(const char *payload);
423};
424
425static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
426 {
427 .str = "a_frames_transmitted_ok",
428 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
429 },
430 {
431 .str = "a_frames_received_ok",
432 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
433 },
434 {
435 .str = "a_frame_check_sequence_errors",
436 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
437 },
438 {
439 .str = "a_alignment_errors",
440 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
441 },
442 {
443 .str = "a_octets_transmitted_ok",
444 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
445 },
446 {
447 .str = "a_octets_received_ok",
448 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
449 },
450 {
451 .str = "a_multicast_frames_xmitted_ok",
452 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
453 },
454 {
455 .str = "a_broadcast_frames_xmitted_ok",
456 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
457 },
458 {
459 .str = "a_multicast_frames_received_ok",
460 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
461 },
462 {
463 .str = "a_broadcast_frames_received_ok",
464 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
465 },
466 {
467 .str = "a_in_range_length_errors",
468 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
469 },
470 {
471 .str = "a_out_of_range_length_field",
472 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
473 },
474 {
475 .str = "a_frame_too_long_errors",
476 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
477 },
478 {
479 .str = "a_symbol_error_during_carrier",
480 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
481 },
482 {
483 .str = "a_mac_control_frames_transmitted",
484 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
485 },
486 {
487 .str = "a_mac_control_frames_received",
488 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
489 },
490 {
491 .str = "a_unsupported_opcodes_received",
492 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
493 },
494 {
495 .str = "a_pause_mac_ctrl_frames_received",
496 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
497 },
498 {
499 .str = "a_pause_mac_ctrl_frames_xmitted",
500 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
501 },
502};
503
504#define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
505
506static void mlxsw_sx_port_get_strings(struct net_device *dev,
507 u32 stringset, u8 *data)
508{
509 u8 *p = data;
510 int i;
511
512 switch (stringset) {
513 case ETH_SS_STATS:
514 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
515 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
516 ETH_GSTRING_LEN);
517 p += ETH_GSTRING_LEN;
518 }
519 break;
520 }
521}
522
523static void mlxsw_sx_port_get_stats(struct net_device *dev,
524 struct ethtool_stats *stats, u64 *data)
525{
526 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
527 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
528 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
529 int i;
530 int err;
531
532 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
533 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
534 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
535 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
536 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
537}
538
539static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
540{
541 switch (sset) {
542 case ETH_SS_STATS:
543 return MLXSW_SX_PORT_HW_STATS_LEN;
544 default:
545 return -EOPNOTSUPP;
546 }
547}
548
549struct mlxsw_sx_port_link_mode {
550 u32 mask;
551 u32 supported;
552 u32 advertised;
553 u32 speed;
554};
555
556static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
557 {
558 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
559 .supported = SUPPORTED_100baseT_Full,
560 .advertised = ADVERTISED_100baseT_Full,
561 .speed = 100,
562 },
563 {
564 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
565 .speed = 100,
566 },
567 {
568 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
569 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
570 .supported = SUPPORTED_1000baseKX_Full,
571 .advertised = ADVERTISED_1000baseKX_Full,
572 .speed = 1000,
573 },
574 {
575 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
576 .supported = SUPPORTED_10000baseT_Full,
577 .advertised = ADVERTISED_10000baseT_Full,
578 .speed = 10000,
579 },
580 {
581 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
582 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
583 .supported = SUPPORTED_10000baseKX4_Full,
584 .advertised = ADVERTISED_10000baseKX4_Full,
585 .speed = 10000,
586 },
587 {
588 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
589 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
590 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
591 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
592 .supported = SUPPORTED_10000baseKR_Full,
593 .advertised = ADVERTISED_10000baseKR_Full,
594 .speed = 10000,
595 },
596 {
597 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
598 .supported = SUPPORTED_20000baseKR2_Full,
599 .advertised = ADVERTISED_20000baseKR2_Full,
600 .speed = 20000,
601 },
602 {
603 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
604 .supported = SUPPORTED_40000baseCR4_Full,
605 .advertised = ADVERTISED_40000baseCR4_Full,
606 .speed = 40000,
607 },
608 {
609 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
610 .supported = SUPPORTED_40000baseKR4_Full,
611 .advertised = ADVERTISED_40000baseKR4_Full,
612 .speed = 40000,
613 },
614 {
615 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
616 .supported = SUPPORTED_40000baseSR4_Full,
617 .advertised = ADVERTISED_40000baseSR4_Full,
618 .speed = 40000,
619 },
620 {
621 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
622 .supported = SUPPORTED_40000baseLR4_Full,
623 .advertised = ADVERTISED_40000baseLR4_Full,
624 .speed = 40000,
625 },
626 {
627 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
628 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
629 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
630 .speed = 25000,
631 },
632 {
633 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
634 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
635 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
636 .speed = 50000,
637 },
638 {
639 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
640 .supported = SUPPORTED_56000baseKR4_Full,
641 .advertised = ADVERTISED_56000baseKR4_Full,
642 .speed = 56000,
643 },
644 {
645 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
646 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
647 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
648 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
649 .speed = 100000,
650 },
651};
652
653#define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
654#define MLXSW_SX_PORT_BASE_SPEED 10000
655
656static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
657{
658 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
659 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
660 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
661 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
662 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
663 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
664 return SUPPORTED_FIBRE;
665
666 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
667 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
668 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
669 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
670 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
671 return SUPPORTED_Backplane;
672 return 0;
673}
674
675static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
676{
677 u32 modes = 0;
678 int i;
679
680 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
681 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
682 modes |= mlxsw_sx_port_link_mode[i].supported;
683 }
684 return modes;
685}
686
687static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
688{
689 u32 modes = 0;
690 int i;
691
692 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
693 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
694 modes |= mlxsw_sx_port_link_mode[i].advertised;
695 }
696 return modes;
697}
698
699static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
700 struct ethtool_link_ksettings *cmd)
701{
702 u32 speed = SPEED_UNKNOWN;
703 u8 duplex = DUPLEX_UNKNOWN;
704 int i;
705
706 if (!carrier_ok)
707 goto out;
708
709 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
710 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
711 speed = mlxsw_sx_port_link_mode[i].speed;
712 duplex = DUPLEX_FULL;
713 break;
714 }
715 }
716out:
717 cmd->base.speed = speed;
718 cmd->base.duplex = duplex;
719}
720
721static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
722{
723 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
724 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
725 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
726 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
727 return PORT_FIBRE;
728
729 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
730 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
731 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
732 return PORT_DA;
733
734 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
735 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
736 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
737 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
738 return PORT_NONE;
739
740 return PORT_OTHER;
741}
742
743static int
744mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
745 struct ethtool_link_ksettings *cmd)
746{
747 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
748 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
749 char ptys_pl[MLXSW_REG_PTYS_LEN];
750 u32 eth_proto_cap;
751 u32 eth_proto_admin;
752 u32 eth_proto_oper;
753 u32 supported, advertising, lp_advertising;
754 int err;
755
756 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
757 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
758 if (err) {
759 netdev_err(dev, "Failed to get proto");
760 return err;
761 }
762 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
763 ð_proto_admin, ð_proto_oper);
764
765 supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
766 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
767 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
768 advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
769 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
770 eth_proto_oper, cmd);
771
772 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
773 cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
774 lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
775
776 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
777 supported);
778 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
779 advertising);
780 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
781 lp_advertising);
782
783 return 0;
784}
785
786static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
787{
788 u32 ptys_proto = 0;
789 int i;
790
791 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
792 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
793 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
794 }
795 return ptys_proto;
796}
797
798static u32 mlxsw_sx_to_ptys_speed(u32 speed)
799{
800 u32 ptys_proto = 0;
801 int i;
802
803 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
804 if (speed == mlxsw_sx_port_link_mode[i].speed)
805 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
806 }
807 return ptys_proto;
808}
809
810static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
811{
812 u32 ptys_proto = 0;
813 int i;
814
815 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
816 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
817 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
818 }
819 return ptys_proto;
820}
821
822static int
823mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
824 const struct ethtool_link_ksettings *cmd)
825{
826 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
827 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
828 char ptys_pl[MLXSW_REG_PTYS_LEN];
829 u32 speed;
830 u32 eth_proto_new;
831 u32 eth_proto_cap;
832 u32 eth_proto_admin;
833 u32 advertising;
834 bool is_up;
835 int err;
836
837 speed = cmd->base.speed;
838
839 ethtool_convert_link_mode_to_legacy_u32(&advertising,
840 cmd->link_modes.advertising);
841
842 eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
843 mlxsw_sx_to_ptys_advert_link(advertising) :
844 mlxsw_sx_to_ptys_speed(speed);
845
846 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
847 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
848 if (err) {
849 netdev_err(dev, "Failed to get proto");
850 return err;
851 }
852 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
853 NULL);
854
855 eth_proto_new = eth_proto_new & eth_proto_cap;
856 if (!eth_proto_new) {
857 netdev_err(dev, "Not supported proto admin requested");
858 return -EINVAL;
859 }
860 if (eth_proto_new == eth_proto_admin)
861 return 0;
862
863 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
864 eth_proto_new, true);
865 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
866 if (err) {
867 netdev_err(dev, "Failed to set proto admin");
868 return err;
869 }
870
871 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
872 if (err) {
873 netdev_err(dev, "Failed to get oper status");
874 return err;
875 }
876 if (!is_up)
877 return 0;
878
879 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
880 if (err) {
881 netdev_err(dev, "Failed to set admin status");
882 return err;
883 }
884
885 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
886 if (err) {
887 netdev_err(dev, "Failed to set admin status");
888 return err;
889 }
890
891 return 0;
892}
893
894static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
895 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
896 .get_link = ethtool_op_get_link,
897 .get_strings = mlxsw_sx_port_get_strings,
898 .get_ethtool_stats = mlxsw_sx_port_get_stats,
899 .get_sset_count = mlxsw_sx_port_get_sset_count,
900 .get_link_ksettings = mlxsw_sx_port_get_link_ksettings,
901 .set_link_ksettings = mlxsw_sx_port_set_link_ksettings,
902};
903
904static int mlxsw_sx_port_attr_get(struct net_device *dev,
905 struct switchdev_attr *attr)
906{
907 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
908 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
909
910 switch (attr->id) {
911 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
912 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
913 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
914 break;
915 default:
916 return -EOPNOTSUPP;
917 }
918
919 return 0;
920}
921
922static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
923 .switchdev_port_attr_get = mlxsw_sx_port_attr_get,
924};
925
926static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
927{
928 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
929 int err;
930
931 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
932 if (err)
933 return err;
934 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
935 return 0;
936}
937
938static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
939{
940 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
941 struct net_device *dev = mlxsw_sx_port->dev;
942 char ppad_pl[MLXSW_REG_PPAD_LEN];
943 int err;
944
945 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
946 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
947 if (err)
948 return err;
949 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
950
951
952
953
954 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
955 return 0;
956}
957
958static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
959 u16 vid, enum mlxsw_reg_spms_state state)
960{
961 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
962 char *spms_pl;
963 int err;
964
965 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
966 if (!spms_pl)
967 return -ENOMEM;
968 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
969 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
970 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
971 kfree(spms_pl);
972 return err;
973}
974
975static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
976 u16 speed, u16 width)
977{
978 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
979 char ptys_pl[MLXSW_REG_PTYS_LEN];
980
981 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
982 width);
983 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
984}
985
986static int
987mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
988{
989 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
990 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
991 char ptys_pl[MLXSW_REG_PTYS_LEN];
992 u32 eth_proto_admin;
993
994 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
995 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
996 eth_proto_admin, true);
997 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
998}
999
1000static int
1001mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
1002 enum mlxsw_reg_spmlr_learn_mode mode)
1003{
1004 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
1005 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
1006
1007 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
1008 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
1009}
1010
1011static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1012 u8 module, u8 width)
1013{
1014 struct mlxsw_sx_port *mlxsw_sx_port;
1015 struct net_device *dev;
1016 int err;
1017
1018 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
1019 if (!dev)
1020 return -ENOMEM;
1021 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
1022 mlxsw_sx_port = netdev_priv(dev);
1023 mlxsw_sx_port->dev = dev;
1024 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1025 mlxsw_sx_port->local_port = local_port;
1026 mlxsw_sx_port->mapping.module = module;
1027
1028 mlxsw_sx_port->pcpu_stats =
1029 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
1030 if (!mlxsw_sx_port->pcpu_stats) {
1031 err = -ENOMEM;
1032 goto err_alloc_stats;
1033 }
1034
1035 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1036 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1037 dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
1038
1039 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1040 if (err) {
1041 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1042 mlxsw_sx_port->local_port);
1043 goto err_dev_addr_get;
1044 }
1045
1046 netif_carrier_off(dev);
1047
1048 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1049 NETIF_F_VLAN_CHALLENGED;
1050
1051 dev->min_mtu = 0;
1052 dev->max_mtu = ETH_MAX_MTU;
1053
1054
1055
1056
1057 dev->needed_headroom = MLXSW_TXHDR_LEN;
1058
1059 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1060 if (err) {
1061 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1062 mlxsw_sx_port->local_port);
1063 goto err_port_system_port_mapping_set;
1064 }
1065
1066 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1067 if (err) {
1068 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1069 mlxsw_sx_port->local_port);
1070 goto err_port_swid_set;
1071 }
1072
1073 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1074 if (err) {
1075 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1076 mlxsw_sx_port->local_port);
1077 goto err_port_speed_set;
1078 }
1079
1080 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1081 if (err) {
1082 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1083 mlxsw_sx_port->local_port);
1084 goto err_port_mtu_set;
1085 }
1086
1087 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1088 if (err)
1089 goto err_port_admin_status_set;
1090
1091 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1092 MLXSW_PORT_DEFAULT_VID,
1093 MLXSW_REG_SPMS_STATE_FORWARDING);
1094 if (err) {
1095 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1096 mlxsw_sx_port->local_port);
1097 goto err_port_stp_state_set;
1098 }
1099
1100 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1101 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1102 if (err) {
1103 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1104 mlxsw_sx_port->local_port);
1105 goto err_port_mac_learning_mode_set;
1106 }
1107
1108 err = register_netdev(dev);
1109 if (err) {
1110 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1111 mlxsw_sx_port->local_port);
1112 goto err_register_netdev;
1113 }
1114
1115 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1116 mlxsw_sx_port, dev, module + 1, false, 0);
1117 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1118 return 0;
1119
1120err_register_netdev:
1121err_port_mac_learning_mode_set:
1122err_port_stp_state_set:
1123err_port_admin_status_set:
1124err_port_mtu_set:
1125err_port_speed_set:
1126 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1127err_port_swid_set:
1128err_port_system_port_mapping_set:
1129err_dev_addr_get:
1130 free_percpu(mlxsw_sx_port->pcpu_stats);
1131err_alloc_stats:
1132 free_netdev(dev);
1133 return err;
1134}
1135
1136static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1137 u8 module, u8 width)
1138{
1139 int err;
1140
1141 err = mlxsw_core_port_init(mlxsw_sx->core, local_port);
1142 if (err) {
1143 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1144 local_port);
1145 return err;
1146 }
1147 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1148 if (err)
1149 goto err_port_create;
1150
1151 return 0;
1152
1153err_port_create:
1154 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1155 return err;
1156}
1157
1158static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1159{
1160 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1161
1162 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1163 unregister_netdev(mlxsw_sx_port->dev);
1164 mlxsw_sx->ports[local_port] = NULL;
1165 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1166 free_percpu(mlxsw_sx_port->pcpu_stats);
1167 free_netdev(mlxsw_sx_port->dev);
1168}
1169
1170static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1171{
1172 return mlxsw_sx->ports[local_port] != NULL;
1173}
1174
1175static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1176 u8 module, u8 width)
1177{
1178 struct mlxsw_sx_port *mlxsw_sx_port;
1179 int err;
1180
1181 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1182 if (!mlxsw_sx_port)
1183 return -ENOMEM;
1184 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1185 mlxsw_sx_port->local_port = local_port;
1186 mlxsw_sx_port->mapping.module = module;
1187
1188 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1189 if (err) {
1190 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1191 mlxsw_sx_port->local_port);
1192 goto err_port_system_port_mapping_set;
1193 }
1194
1195
1196 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1197 if (err) {
1198 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1199 mlxsw_sx_port->local_port);
1200 goto err_port_swid_set;
1201 }
1202
1203
1204 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1205 if (err) {
1206 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1207 mlxsw_sx_port->local_port);
1208 goto err_port_ib_set;
1209 }
1210
1211
1212
1213
1214 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1215 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1216 BIT(3) - 1);
1217 if (err) {
1218 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1219 mlxsw_sx_port->local_port);
1220 goto err_port_speed_set;
1221 }
1222
1223
1224
1225
1226 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1227 if (err) {
1228 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1229 mlxsw_sx_port->local_port);
1230 goto err_port_mtu_set;
1231 }
1232
1233 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1234 if (err) {
1235 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1236 mlxsw_sx_port->local_port);
1237 goto err_port_admin_set;
1238 }
1239
1240 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1241 mlxsw_sx_port);
1242 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1243 return 0;
1244
1245err_port_admin_set:
1246err_port_mtu_set:
1247err_port_speed_set:
1248err_port_ib_set:
1249 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1250err_port_swid_set:
1251err_port_system_port_mapping_set:
1252 kfree(mlxsw_sx_port);
1253 return err;
1254}
1255
1256static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1257{
1258 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1259
1260 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1261 mlxsw_sx->ports[local_port] = NULL;
1262 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1263 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1264 kfree(mlxsw_sx_port);
1265}
1266
1267static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1268{
1269 enum devlink_port_type port_type =
1270 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1271
1272 if (port_type == DEVLINK_PORT_TYPE_ETH)
1273 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1274 else if (port_type == DEVLINK_PORT_TYPE_IB)
1275 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1276}
1277
1278static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1279{
1280 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1281 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1282}
1283
1284static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1285{
1286 int i;
1287
1288 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1289 if (mlxsw_sx_port_created(mlxsw_sx, i))
1290 mlxsw_sx_port_remove(mlxsw_sx, i);
1291 kfree(mlxsw_sx->ports);
1292}
1293
1294static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1295{
1296 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1297 size_t alloc_size;
1298 u8 module, width;
1299 int i;
1300 int err;
1301
1302 alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1303 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1304 if (!mlxsw_sx->ports)
1305 return -ENOMEM;
1306
1307 for (i = 1; i < max_ports; i++) {
1308 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1309 &width);
1310 if (err)
1311 goto err_port_module_info_get;
1312 if (!width)
1313 continue;
1314 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1315 if (err)
1316 goto err_port_create;
1317 }
1318 return 0;
1319
1320err_port_create:
1321err_port_module_info_get:
1322 for (i--; i >= 1; i--)
1323 if (mlxsw_sx_port_created(mlxsw_sx, i))
1324 mlxsw_sx_port_remove(mlxsw_sx, i);
1325 kfree(mlxsw_sx->ports);
1326 return err;
1327}
1328
1329static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1330 enum mlxsw_reg_pude_oper_status status)
1331{
1332 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1333 netdev_info(mlxsw_sx_port->dev, "link up\n");
1334 netif_carrier_on(mlxsw_sx_port->dev);
1335 } else {
1336 netdev_info(mlxsw_sx_port->dev, "link down\n");
1337 netif_carrier_off(mlxsw_sx_port->dev);
1338 }
1339}
1340
1341static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1342 enum mlxsw_reg_pude_oper_status status)
1343{
1344 if (status == MLXSW_PORT_OPER_STATUS_UP)
1345 pr_info("ib link for port %d - up\n",
1346 mlxsw_sx_port->mapping.module + 1);
1347 else
1348 pr_info("ib link for port %d - down\n",
1349 mlxsw_sx_port->mapping.module + 1);
1350}
1351
1352static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1353 char *pude_pl, void *priv)
1354{
1355 struct mlxsw_sx *mlxsw_sx = priv;
1356 struct mlxsw_sx_port *mlxsw_sx_port;
1357 enum mlxsw_reg_pude_oper_status status;
1358 enum devlink_port_type port_type;
1359 u8 local_port;
1360
1361 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1362 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1363 if (!mlxsw_sx_port) {
1364 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1365 local_port);
1366 return;
1367 }
1368
1369 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1370 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1371 if (port_type == DEVLINK_PORT_TYPE_ETH)
1372 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1373 else if (port_type == DEVLINK_PORT_TYPE_IB)
1374 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1375}
1376
1377static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1378 void *priv)
1379{
1380 struct mlxsw_sx *mlxsw_sx = priv;
1381 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1382 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1383
1384 if (unlikely(!mlxsw_sx_port)) {
1385 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1386 local_port);
1387 return;
1388 }
1389
1390 skb->dev = mlxsw_sx_port->dev;
1391
1392 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1393 u64_stats_update_begin(&pcpu_stats->syncp);
1394 pcpu_stats->rx_packets++;
1395 pcpu_stats->rx_bytes += skb->len;
1396 u64_stats_update_end(&pcpu_stats->syncp);
1397
1398 skb->protocol = eth_type_trans(skb, skb->dev);
1399 netif_receive_skb(skb);
1400}
1401
1402static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1403 enum devlink_port_type new_type)
1404{
1405 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1406 u8 module, width;
1407 int err;
1408
1409 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1410 return -EOPNOTSUPP;
1411
1412 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1413 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1414 &width);
1415 if (err)
1416 goto err_port_module_info_get;
1417
1418 if (new_type == DEVLINK_PORT_TYPE_ETH)
1419 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1420 width);
1421 else if (new_type == DEVLINK_PORT_TYPE_IB)
1422 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1423 width);
1424
1425err_port_module_info_get:
1426 return err;
1427}
1428
1429#define MLXSW_SX_RXL(_trap_id) \
1430 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1431 false, SX2_RX, FORWARD)
1432
1433static const struct mlxsw_listener mlxsw_sx_listener[] = {
1434 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1435 MLXSW_SX_RXL(FDB_MC),
1436 MLXSW_SX_RXL(STP),
1437 MLXSW_SX_RXL(LACP),
1438 MLXSW_SX_RXL(EAPOL),
1439 MLXSW_SX_RXL(LLDP),
1440 MLXSW_SX_RXL(MMRP),
1441 MLXSW_SX_RXL(MVRP),
1442 MLXSW_SX_RXL(RPVST),
1443 MLXSW_SX_RXL(DHCP),
1444 MLXSW_SX_RXL(IGMP_QUERY),
1445 MLXSW_SX_RXL(IGMP_V1_REPORT),
1446 MLXSW_SX_RXL(IGMP_V2_REPORT),
1447 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1448 MLXSW_SX_RXL(IGMP_V3_REPORT),
1449};
1450
1451static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1452{
1453 char htgt_pl[MLXSW_REG_HTGT_LEN];
1454 int i;
1455 int err;
1456
1457 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1458 MLXSW_REG_HTGT_INVALID_POLICER,
1459 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1460 MLXSW_REG_HTGT_DEFAULT_TC);
1461 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1462 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1463
1464 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1465 if (err)
1466 return err;
1467
1468 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1469 MLXSW_REG_HTGT_INVALID_POLICER,
1470 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1471 MLXSW_REG_HTGT_DEFAULT_TC);
1472 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1473 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1474
1475 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1476 if (err)
1477 return err;
1478
1479 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1480 err = mlxsw_core_trap_register(mlxsw_sx->core,
1481 &mlxsw_sx_listener[i],
1482 mlxsw_sx);
1483 if (err)
1484 goto err_listener_register;
1485
1486 }
1487 return 0;
1488
1489err_listener_register:
1490 for (i--; i >= 0; i--) {
1491 mlxsw_core_trap_unregister(mlxsw_sx->core,
1492 &mlxsw_sx_listener[i],
1493 mlxsw_sx);
1494 }
1495 return err;
1496}
1497
1498static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1499{
1500 int i;
1501
1502 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1503 mlxsw_core_trap_unregister(mlxsw_sx->core,
1504 &mlxsw_sx_listener[i],
1505 mlxsw_sx);
1506 }
1507}
1508
1509static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1510{
1511 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1512 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1513 char *sftr_pl;
1514 int err;
1515
1516
1517 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1518 if (!sftr_pl)
1519 return -ENOMEM;
1520 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1521 MLXSW_PORT_CPU_PORT, true);
1522 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1523 kfree(sftr_pl);
1524 if (err)
1525 return err;
1526
1527
1528 mlxsw_reg_sfgc_pack(sfgc_pl,
1529 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1530 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1531 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1532 0);
1533 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1534 if (err)
1535 return err;
1536
1537 mlxsw_reg_sfgc_pack(sfgc_pl,
1538 MLXSW_REG_SFGC_TYPE_BROADCAST,
1539 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1540 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1541 0);
1542 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1543 if (err)
1544 return err;
1545
1546 mlxsw_reg_sfgc_pack(sfgc_pl,
1547 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1548 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1549 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1550 0);
1551 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1552 if (err)
1553 return err;
1554
1555 mlxsw_reg_sfgc_pack(sfgc_pl,
1556 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1557 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1558 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1559 0);
1560 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1561 if (err)
1562 return err;
1563
1564 mlxsw_reg_sfgc_pack(sfgc_pl,
1565 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1566 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1567 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1568 0);
1569 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1570 if (err)
1571 return err;
1572
1573 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1574 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1575}
1576
1577static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1578{
1579 char htgt_pl[MLXSW_REG_HTGT_LEN];
1580
1581 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1582 MLXSW_REG_HTGT_INVALID_POLICER,
1583 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1584 MLXSW_REG_HTGT_DEFAULT_TC);
1585 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1586 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1587 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1588 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1589}
1590
1591static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1592 const struct mlxsw_bus_info *mlxsw_bus_info)
1593{
1594 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1595 int err;
1596
1597 mlxsw_sx->core = mlxsw_core;
1598 mlxsw_sx->bus_info = mlxsw_bus_info;
1599
1600 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1601 if (err) {
1602 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1603 return err;
1604 }
1605
1606 err = mlxsw_sx_ports_create(mlxsw_sx);
1607 if (err) {
1608 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1609 return err;
1610 }
1611
1612 err = mlxsw_sx_traps_init(mlxsw_sx);
1613 if (err) {
1614 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1615 goto err_listener_register;
1616 }
1617
1618 err = mlxsw_sx_flood_init(mlxsw_sx);
1619 if (err) {
1620 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1621 goto err_flood_init;
1622 }
1623
1624 return 0;
1625
1626err_flood_init:
1627 mlxsw_sx_traps_fini(mlxsw_sx);
1628err_listener_register:
1629 mlxsw_sx_ports_remove(mlxsw_sx);
1630 return err;
1631}
1632
1633static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1634{
1635 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1636
1637 mlxsw_sx_traps_fini(mlxsw_sx);
1638 mlxsw_sx_ports_remove(mlxsw_sx);
1639}
1640
1641static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1642 .used_max_vepa_channels = 1,
1643 .max_vepa_channels = 0,
1644 .used_max_mid = 1,
1645 .max_mid = 7000,
1646 .used_max_pgt = 1,
1647 .max_pgt = 0,
1648 .used_max_system_port = 1,
1649 .max_system_port = 48000,
1650 .used_max_vlan_groups = 1,
1651 .max_vlan_groups = 127,
1652 .used_max_regions = 1,
1653 .max_regions = 400,
1654 .used_flood_tables = 1,
1655 .max_flood_tables = 2,
1656 .max_vid_flood_tables = 1,
1657 .used_flood_mode = 1,
1658 .flood_mode = 3,
1659 .used_max_ib_mc = 1,
1660 .max_ib_mc = 6,
1661 .used_max_pkey = 1,
1662 .max_pkey = 0,
1663 .swid_config = {
1664 {
1665 .used_type = 1,
1666 .type = MLXSW_PORT_SWID_TYPE_ETH,
1667 },
1668 {
1669 .used_type = 1,
1670 .type = MLXSW_PORT_SWID_TYPE_IB,
1671 }
1672 },
1673};
1674
1675static struct mlxsw_driver mlxsw_sx_driver = {
1676 .kind = mlxsw_sx_driver_name,
1677 .priv_size = sizeof(struct mlxsw_sx),
1678 .init = mlxsw_sx_init,
1679 .fini = mlxsw_sx_fini,
1680 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1681 .txhdr_construct = mlxsw_sx_txhdr_construct,
1682 .txhdr_len = MLXSW_TXHDR_LEN,
1683 .profile = &mlxsw_sx_config_profile,
1684 .port_type_set = mlxsw_sx_port_type_set,
1685};
1686
1687static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1688 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1689 {0, },
1690};
1691
1692static struct pci_driver mlxsw_sx_pci_driver = {
1693 .name = mlxsw_sx_driver_name,
1694 .id_table = mlxsw_sx_pci_id_table,
1695};
1696
1697static int __init mlxsw_sx_module_init(void)
1698{
1699 int err;
1700
1701 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1702 if (err)
1703 return err;
1704
1705 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1706 if (err)
1707 goto err_pci_driver_register;
1708
1709 return 0;
1710
1711err_pci_driver_register:
1712 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1713 return err;
1714}
1715
1716static void __exit mlxsw_sx_module_exit(void)
1717{
1718 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1719 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1720}
1721
1722module_init(mlxsw_sx_module_init);
1723module_exit(mlxsw_sx_module_exit);
1724
1725MODULE_LICENSE("Dual BSD/GPL");
1726MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1727MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1728MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);
1729
