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26#ifndef __RTL92E_DEF_H__
27#define __RTL92E_DEF_H__
28
29#define RX_DESC_NUM_92E 512
30
31#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
32#define HAL_PRIME_CHNL_OFFSET_LOWER 1
33#define HAL_PRIME_CHNL_OFFSET_UPPER 2
34
35#define RX_MPDU_QUEUE 0
36
37#define IS_HT_RATE(_rate) \
38 (_rate >= DESC92C_RATEMCS0)
39#define IS_CCK_RATE(_rate) \
40 (_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
41#define IS_OFDM_RATE(_rate) \
42 (_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
43
44enum version_8192e {
45 VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
46 VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
47 VERSION_UNKNOWN = 0xFF,
48};
49
50enum rtl_desc_qsel {
51 QSLT_BK = 0x2,
52 QSLT_BE = 0x0,
53 QSLT_VI = 0x5,
54 QSLT_VO = 0x7,
55 QSLT_BEACON = 0x10,
56 QSLT_HIGH = 0x11,
57 QSLT_MGNT = 0x12,
58 QSLT_CMD = 0x13,
59};
60
61enum rtl_desc92c_rate {
62 DESC92C_RATE1M = 0x00,
63 DESC92C_RATE2M = 0x01,
64 DESC92C_RATE5_5M = 0x02,
65 DESC92C_RATE11M = 0x03,
66
67 DESC92C_RATE6M = 0x04,
68 DESC92C_RATE9M = 0x05,
69 DESC92C_RATE12M = 0x06,
70 DESC92C_RATE18M = 0x07,
71 DESC92C_RATE24M = 0x08,
72 DESC92C_RATE36M = 0x09,
73 DESC92C_RATE48M = 0x0a,
74 DESC92C_RATE54M = 0x0b,
75
76 DESC92C_RATEMCS0 = 0x0c,
77 DESC92C_RATEMCS1 = 0x0d,
78 DESC92C_RATEMCS2 = 0x0e,
79 DESC92C_RATEMCS3 = 0x0f,
80 DESC92C_RATEMCS4 = 0x10,
81 DESC92C_RATEMCS5 = 0x11,
82 DESC92C_RATEMCS6 = 0x12,
83 DESC92C_RATEMCS7 = 0x13,
84 DESC92C_RATEMCS8 = 0x14,
85 DESC92C_RATEMCS9 = 0x15,
86 DESC92C_RATEMCS10 = 0x16,
87 DESC92C_RATEMCS11 = 0x17,
88 DESC92C_RATEMCS12 = 0x18,
89 DESC92C_RATEMCS13 = 0x19,
90 DESC92C_RATEMCS14 = 0x1a,
91 DESC92C_RATEMCS15 = 0x1b,
92};
93#endif
94