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12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/acpi.h>
15#include <linux/bitfield.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/uaccess.h>
22
23#include <asm/cpu_device_id.h>
24#include <asm/intel-family.h>
25
26#include "intel_pmc_core.h"
27
28#define ICPU(model, data) \
29 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
30
31static struct pmc_dev pmc;
32
33static const struct pmc_bit_map spt_pll_map[] = {
34 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
35 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
36 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
37 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
38 {},
39};
40
41static const struct pmc_bit_map spt_mphy_map[] = {
42 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
43 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
44 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
45 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
46 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
47 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
48 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
49 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
50 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
51 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
52 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
53 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
54 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
55 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
56 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
57 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
58 {},
59};
60
61static const struct pmc_bit_map spt_pfear_map[] = {
62 {"PMC", SPT_PMC_BIT_PMC},
63 {"OPI-DMI", SPT_PMC_BIT_OPI},
64 {"SPI / eSPI", SPT_PMC_BIT_SPI},
65 {"XHCI", SPT_PMC_BIT_XHCI},
66 {"SPA", SPT_PMC_BIT_SPA},
67 {"SPB", SPT_PMC_BIT_SPB},
68 {"SPC", SPT_PMC_BIT_SPC},
69 {"GBE", SPT_PMC_BIT_GBE},
70 {"SATA", SPT_PMC_BIT_SATA},
71 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
72 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
73 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
74 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
75 {"RSVD", SPT_PMC_BIT_RSVD_0B},
76 {"LPSS", SPT_PMC_BIT_LPSS},
77 {"LPC", SPT_PMC_BIT_LPC},
78 {"SMB", SPT_PMC_BIT_SMB},
79 {"ISH", SPT_PMC_BIT_ISH},
80 {"P2SB", SPT_PMC_BIT_P2SB},
81 {"DFX", SPT_PMC_BIT_DFX},
82 {"SCC", SPT_PMC_BIT_SCC},
83 {"RSVD", SPT_PMC_BIT_RSVD_0C},
84 {"FUSE", SPT_PMC_BIT_FUSE},
85 {"CAMERA", SPT_PMC_BIT_CAMREA},
86 {"RSVD", SPT_PMC_BIT_RSVD_0D},
87 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
88 {"EXI", SPT_PMC_BIT_EXI},
89 {"CSE", SPT_PMC_BIT_CSE},
90 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
91 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
92 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
93 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
94 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
95 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
96 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
97 {"RSVD", SPT_PMC_BIT_RSVD_1A},
98 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
99 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
100 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
101 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
102 {},
103};
104
105static const struct pmc_bit_map spt_ltr_show_map[] = {
106 {"SOUTHPORT_A", SPT_PMC_LTR_SPA},
107 {"SOUTHPORT_B", SPT_PMC_LTR_SPB},
108 {"SATA", SPT_PMC_LTR_SATA},
109 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
110 {"XHCI", SPT_PMC_LTR_XHCI},
111 {"ME", SPT_PMC_LTR_ME},
112
113 {"EVA", SPT_PMC_LTR_EVA},
114 {"SOUTHPORT_C", SPT_PMC_LTR_SPC},
115 {"HD_AUDIO", SPT_PMC_LTR_AZ},
116 {"LPSS", SPT_PMC_LTR_LPSS},
117 {"SOUTHPORT_D", SPT_PMC_LTR_SPD},
118 {"SOUTHPORT_E", SPT_PMC_LTR_SPE},
119 {"CAMERA", SPT_PMC_LTR_CAM},
120 {"ESPI", SPT_PMC_LTR_ESPI},
121 {"SCC", SPT_PMC_LTR_SCC},
122 {"ISH", SPT_PMC_LTR_ISH},
123
124 {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
125 {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
126 {}
127};
128
129static const struct pmc_reg_map spt_reg_map = {
130 .pfear_sts = spt_pfear_map,
131 .mphy_sts = spt_mphy_map,
132 .pll_sts = spt_pll_map,
133 .ltr_show_sts = spt_ltr_show_map,
134 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
135 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
136 .regmap_length = SPT_PMC_MMIO_REG_LEN,
137 .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
138 .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
139 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
140 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
141 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
142};
143
144
145static const struct pmc_bit_map cnp_pfear_map[] = {
146 {"PMC", BIT(0)},
147 {"OPI-DMI", BIT(1)},
148 {"SPI/eSPI", BIT(2)},
149 {"XHCI", BIT(3)},
150 {"SPA", BIT(4)},
151 {"SPB", BIT(5)},
152 {"SPC", BIT(6)},
153 {"GBE", BIT(7)},
154
155 {"SATA", BIT(0)},
156 {"HDA_PGD0", BIT(1)},
157 {"HDA_PGD1", BIT(2)},
158 {"HDA_PGD2", BIT(3)},
159 {"HDA_PGD3", BIT(4)},
160 {"SPD", BIT(5)},
161 {"LPSS", BIT(6)},
162 {"LPC", BIT(7)},
163
164 {"SMB", BIT(0)},
165 {"ISH", BIT(1)},
166 {"P2SB", BIT(2)},
167 {"NPK_VNN", BIT(3)},
168 {"SDX", BIT(4)},
169 {"SPE", BIT(5)},
170 {"Fuse", BIT(6)},
171 {"Res_23", BIT(7)},
172
173 {"CSME_FSC", BIT(0)},
174 {"USB3_OTG", BIT(1)},
175 {"EXI", BIT(2)},
176 {"CSE", BIT(3)},
177 {"csme_kvm", BIT(4)},
178 {"csme_pmt", BIT(5)},
179 {"csme_clink", BIT(6)},
180 {"csme_ptio", BIT(7)},
181
182 {"csme_usbr", BIT(0)},
183 {"csme_susram", BIT(1)},
184 {"csme_smt1", BIT(2)},
185 {"CSME_SMT4", BIT(3)},
186 {"csme_sms2", BIT(4)},
187 {"csme_sms1", BIT(5)},
188 {"csme_rtc", BIT(6)},
189 {"csme_psf", BIT(7)},
190
191 {"SBR0", BIT(0)},
192 {"SBR1", BIT(1)},
193 {"SBR2", BIT(2)},
194 {"SBR3", BIT(3)},
195 {"SBR4", BIT(4)},
196 {"SBR5", BIT(5)},
197 {"CSME_PECI", BIT(6)},
198 {"PSF1", BIT(7)},
199
200 {"PSF2", BIT(0)},
201 {"PSF3", BIT(1)},
202 {"PSF4", BIT(2)},
203 {"CNVI", BIT(3)},
204 {"UFS0", BIT(4)},
205 {"EMMC", BIT(5)},
206 {"Res_6", BIT(6)},
207 {"SBR6", BIT(7)},
208
209 {"SBR7", BIT(0)},
210 {"NPK_AON", BIT(1)},
211 {"HDA_PGD4", BIT(2)},
212 {"HDA_PGD5", BIT(3)},
213 {"HDA_PGD6", BIT(4)},
214 {}
215};
216
217static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
218 {"AUDIO_D3", BIT(0)},
219 {"OTG_D3", BIT(1)},
220 {"XHCI_D3", BIT(2)},
221 {"LPIO_D3", BIT(3)},
222 {"SDX_D3", BIT(4)},
223 {"SATA_D3", BIT(5)},
224 {"UFS0_D3", BIT(6)},
225 {"UFS1_D3", BIT(7)},
226 {"EMMC_D3", BIT(8)},
227 {}
228};
229
230static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
231 {"SDIO_PLL_OFF", BIT(0)},
232 {"USB2_PLL_OFF", BIT(1)},
233 {"AUDIO_PLL_OFF", BIT(2)},
234 {"OC_PLL_OFF", BIT(3)},
235 {"MAIN_PLL_OFF", BIT(4)},
236 {"XOSC_OFF", BIT(5)},
237 {"LPC_CLKS_GATED", BIT(6)},
238 {"PCIE_CLKREQS_IDLE", BIT(7)},
239 {"AUDIO_ROSC_OFF", BIT(8)},
240 {"HPET_XOSC_CLK_REQ", BIT(9)},
241 {"PMC_ROSC_SLOW_CLK", BIT(10)},
242 {"AON2_ROSC_GATED", BIT(11)},
243 {"CLKACKS_DEASSERTED", BIT(12)},
244 {}
245};
246
247static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
248 {"MPHY_CORE_GATED", BIT(0)},
249 {"CSME_GATED", BIT(1)},
250 {"USB2_SUS_GATED", BIT(2)},
251 {"DYN_FLEX_IO_IDLE", BIT(3)},
252 {"GBE_NO_LINK", BIT(4)},
253 {"THERM_SEN_DISABLED", BIT(5)},
254 {"PCIE_LOW_POWER", BIT(6)},
255 {"ISH_VNNAON_REQ_ACT", BIT(7)},
256 {"ISH_VNN_REQ_ACT", BIT(8)},
257 {"CNV_VNNAON_REQ_ACT", BIT(9)},
258 {"CNV_VNN_REQ_ACT", BIT(10)},
259 {"NPK_VNNON_REQ_ACT", BIT(11)},
260 {"PMSYNC_STATE_IDLE", BIT(12)},
261 {"ALST_GT_THRES", BIT(13)},
262 {"PMC_ARC_PG_READY", BIT(14)},
263 {}
264};
265
266static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
267 cnp_slps0_dbg0_map,
268 cnp_slps0_dbg1_map,
269 cnp_slps0_dbg2_map,
270 NULL,
271};
272
273static const struct pmc_bit_map cnp_ltr_show_map[] = {
274 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
275 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
276 {"SATA", CNP_PMC_LTR_SATA},
277 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
278 {"XHCI", CNP_PMC_LTR_XHCI},
279 {"ME", CNP_PMC_LTR_ME},
280
281 {"EVA", CNP_PMC_LTR_EVA},
282 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
283 {"HD_AUDIO", CNP_PMC_LTR_AZ},
284 {"CNV", CNP_PMC_LTR_CNV},
285 {"LPSS", CNP_PMC_LTR_LPSS},
286 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
287 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
288 {"CAMERA", CNP_PMC_LTR_CAM},
289 {"ESPI", CNP_PMC_LTR_ESPI},
290 {"SCC", CNP_PMC_LTR_SCC},
291 {"ISH", CNP_PMC_LTR_ISH},
292 {"UFSX2", CNP_PMC_LTR_UFSX2},
293 {"EMMC", CNP_PMC_LTR_EMMC},
294
295 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
296 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
297 {}
298};
299
300static const struct pmc_reg_map cnp_reg_map = {
301 .pfear_sts = cnp_pfear_map,
302 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
303 .slps0_dbg_maps = cnp_slps0_dbg_maps,
304 .ltr_show_sts = cnp_ltr_show_map,
305 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
306 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
307 .regmap_length = CNP_PMC_MMIO_REG_LEN,
308 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
309 .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
310 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
311 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
312 .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
313};
314
315static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
316{
317 return readb(pmcdev->regbase + offset);
318}
319
320static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
321{
322 return readl(pmcdev->regbase + reg_offset);
323}
324
325static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
326 reg_offset, u32 val)
327{
328 writel(val, pmcdev->regbase + reg_offset);
329}
330
331static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
332{
333 return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
334}
335
336static int pmc_core_dev_state_get(void *data, u64 *val)
337{
338 struct pmc_dev *pmcdev = data;
339 const struct pmc_reg_map *map = pmcdev->map;
340 u32 value;
341
342 value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
343 *val = pmc_core_adjust_slp_s0_step(value);
344
345 return 0;
346}
347
348DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
349
350static int pmc_core_check_read_lock_bit(void)
351{
352 struct pmc_dev *pmcdev = &pmc;
353 u32 value;
354
355 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
356 return value & BIT(pmcdev->map->pm_read_disable_bit);
357}
358
359#if IS_ENABLED(CONFIG_DEBUG_FS)
360static bool slps0_dbg_latch;
361
362static void pmc_core_display_map(struct seq_file *s, int index,
363 u8 pf_reg, const struct pmc_bit_map *pf_map)
364{
365 seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
366 index, pf_map[index].name,
367 pf_map[index].bit_mask & pf_reg ? "Off" : "On");
368}
369
370static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
371{
372 struct pmc_dev *pmcdev = s->private;
373 const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
374 u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
375 int index, iter;
376
377 iter = pmcdev->map->ppfear0_offset;
378
379 for (index = 0; index < pmcdev->map->ppfear_buckets &&
380 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
381 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
382
383 for (index = 0; map[index].name; index++)
384 pmc_core_display_map(s, index, pf_regs[index / 8], map);
385
386 return 0;
387}
388DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
389
390
391static int pmc_core_mtpmc_link_status(void)
392{
393 struct pmc_dev *pmcdev = &pmc;
394 u32 value;
395
396 value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
397 return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
398}
399
400static int pmc_core_send_msg(u32 *addr_xram)
401{
402 struct pmc_dev *pmcdev = &pmc;
403 u32 dest;
404 int timeout;
405
406 for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
407 if (pmc_core_mtpmc_link_status() == 0)
408 break;
409 msleep(5);
410 }
411
412 if (timeout <= 0 && pmc_core_mtpmc_link_status())
413 return -EBUSY;
414
415 dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
416 pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
417 return 0;
418}
419
420static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
421{
422 struct pmc_dev *pmcdev = s->private;
423 const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
424 u32 mphy_core_reg_low, mphy_core_reg_high;
425 u32 val_low, val_high;
426 int index, err = 0;
427
428 if (pmcdev->pmc_xram_read_bit) {
429 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
430 return 0;
431 }
432
433 mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
434 mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
435
436 mutex_lock(&pmcdev->lock);
437
438 if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
439 err = -EBUSY;
440 goto out_unlock;
441 }
442
443 msleep(10);
444 val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
445
446 if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
447 err = -EBUSY;
448 goto out_unlock;
449 }
450
451 msleep(10);
452 val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
453
454 for (index = 0; map[index].name && index < 8; index++) {
455 seq_printf(s, "%-32s\tState: %s\n",
456 map[index].name,
457 map[index].bit_mask & val_low ? "Not power gated" :
458 "Power gated");
459 }
460
461 for (index = 8; map[index].name; index++) {
462 seq_printf(s, "%-32s\tState: %s\n",
463 map[index].name,
464 map[index].bit_mask & val_high ? "Not power gated" :
465 "Power gated");
466 }
467
468out_unlock:
469 mutex_unlock(&pmcdev->lock);
470 return err;
471}
472DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
473
474static int pmc_core_pll_show(struct seq_file *s, void *unused)
475{
476 struct pmc_dev *pmcdev = s->private;
477 const struct pmc_bit_map *map = pmcdev->map->pll_sts;
478 u32 mphy_common_reg, val;
479 int index, err = 0;
480
481 if (pmcdev->pmc_xram_read_bit) {
482 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
483 return 0;
484 }
485
486 mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
487 mutex_lock(&pmcdev->lock);
488
489 if (pmc_core_send_msg(&mphy_common_reg) != 0) {
490 err = -EBUSY;
491 goto out_unlock;
492 }
493
494
495 msleep(10);
496 val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
497
498 for (index = 0; map[index].name ; index++) {
499 seq_printf(s, "%-32s\tState: %s\n",
500 map[index].name,
501 map[index].bit_mask & val ? "Active" : "Idle");
502 }
503
504out_unlock:
505 mutex_unlock(&pmcdev->lock);
506 return err;
507}
508DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
509
510static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
511*userbuf, size_t count, loff_t *ppos)
512{
513 struct pmc_dev *pmcdev = &pmc;
514 const struct pmc_reg_map *map = pmcdev->map;
515 u32 val, buf_size, fd;
516 int err = 0;
517
518 buf_size = count < 64 ? count : 64;
519 mutex_lock(&pmcdev->lock);
520
521 if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
522 err = -EFAULT;
523 goto out_unlock;
524 }
525
526 if (val > map->ltr_ignore_max) {
527 err = -EINVAL;
528 goto out_unlock;
529 }
530
531 fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
532 fd |= (1U << val);
533 pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
534
535out_unlock:
536 mutex_unlock(&pmcdev->lock);
537 return err == 0 ? count : err;
538}
539
540static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
541{
542 return 0;
543}
544
545static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
546{
547 return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
548}
549
550static const struct file_operations pmc_core_ltr_ignore_ops = {
551 .open = pmc_core_ltr_ignore_open,
552 .read = seq_read,
553 .write = pmc_core_ltr_ignore_write,
554 .llseek = seq_lseek,
555 .release = single_release,
556};
557
558static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
559{
560 const struct pmc_reg_map *map = pmcdev->map;
561 u32 fd;
562
563 mutex_lock(&pmcdev->lock);
564
565 if (!reset && !slps0_dbg_latch)
566 goto out_unlock;
567
568 fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
569 if (reset)
570 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
571 else
572 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
573 pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
574
575 slps0_dbg_latch = 0;
576
577out_unlock:
578 mutex_unlock(&pmcdev->lock);
579}
580
581static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
582{
583 struct pmc_dev *pmcdev = s->private;
584 const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
585 const struct pmc_bit_map *map;
586 int offset;
587 u32 data;
588
589 pmc_core_slps0_dbg_latch(pmcdev, false);
590 offset = pmcdev->map->slps0_dbg_offset;
591 while (*maps) {
592 map = *maps;
593 data = pmc_core_reg_read(pmcdev, offset);
594 offset += 4;
595 while (map->name) {
596 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
597 map->name,
598 data & map->bit_mask ?
599 "Yes" : "No");
600 ++map;
601 }
602 ++maps;
603 }
604 pmc_core_slps0_dbg_latch(pmcdev, true);
605 return 0;
606}
607DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
608
609static u32 convert_ltr_scale(u32 val)
610{
611
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632
633
634
635 if (val > 5) {
636 pr_warn("Invalid LTR scale factor.\n");
637 return 0;
638 }
639
640 return 1U << (5 * val);
641}
642
643static int pmc_core_ltr_show(struct seq_file *s, void *unused)
644{
645 struct pmc_dev *pmcdev = s->private;
646 const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
647 u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
648 u32 ltr_raw_data, scale, val;
649 u16 snoop_ltr, nonsnoop_ltr;
650 int index;
651
652 for (index = 0; map[index].name ; index++) {
653 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
654 ltr_raw_data = pmc_core_reg_read(pmcdev,
655 map[index].bit_mask);
656 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
657 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
658
659 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
660 scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
661 val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
662 decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
663 }
664
665 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
666 scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
667 val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
668 decoded_snoop_ltr = val * convert_ltr_scale(scale);
669 }
670
671 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
672 map[index].name, ltr_raw_data,
673 decoded_non_snoop_ltr,
674 decoded_snoop_ltr);
675 }
676 return 0;
677}
678DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
679
680static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
681{
682 debugfs_remove_recursive(pmcdev->dbgfs_dir);
683}
684
685static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
686{
687 struct dentry *dir;
688
689 dir = debugfs_create_dir("pmc_core", NULL);
690 if (!dir)
691 return -ENOMEM;
692
693 pmcdev->dbgfs_dir = dir;
694
695 debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
696 &pmc_core_dev_state);
697
698 debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
699 &pmc_core_ppfear_fops);
700
701 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
702 &pmc_core_ltr_ignore_ops);
703
704 debugfs_create_file("ltr_show", 0644, dir, pmcdev, &pmc_core_ltr_fops);
705
706 if (pmcdev->map->pll_sts)
707 debugfs_create_file("pll_status", 0444, dir, pmcdev,
708 &pmc_core_pll_fops);
709
710 if (pmcdev->map->mphy_sts)
711 debugfs_create_file("mphy_core_lanes_power_gating_status",
712 0444, dir, pmcdev,
713 &pmc_core_mphy_pg_fops);
714
715 if (pmcdev->map->slps0_dbg_maps) {
716 debugfs_create_file("slp_s0_debug_status", 0444,
717 dir, pmcdev,
718 &pmc_core_slps0_dbg_fops);
719
720 debugfs_create_bool("slp_s0_dbg_latch", 0644,
721 dir, &slps0_dbg_latch);
722 }
723
724 return 0;
725}
726#else
727static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
728{
729 return 0;
730}
731
732static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
733{
734}
735#endif
736
737static const struct x86_cpu_id intel_pmc_core_ids[] = {
738 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
739 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
740 ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
741 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
742 ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
743 {}
744};
745
746MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
747
748static const struct pci_device_id pmc_pci_ids[] = {
749 { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
750 { 0, },
751};
752
753static int __init pmc_core_probe(void)
754{
755 struct pmc_dev *pmcdev = &pmc;
756 const struct x86_cpu_id *cpu_id;
757 u64 slp_s0_addr;
758 int err;
759
760 cpu_id = x86_match_cpu(intel_pmc_core_ids);
761 if (!cpu_id)
762 return -ENODEV;
763
764 pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
765
766
767
768
769
770
771 if (!pci_dev_present(pmc_pci_ids))
772 pmcdev->map = &cnp_reg_map;
773
774 if (lpit_read_residency_count_address(&slp_s0_addr))
775 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
776 else
777 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
778
779 pmcdev->regbase = ioremap(pmcdev->base_addr,
780 pmcdev->map->regmap_length);
781 if (!pmcdev->regbase)
782 return -ENOMEM;
783
784 mutex_init(&pmcdev->lock);
785 pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
786
787 err = pmc_core_dbgfs_register(pmcdev);
788 if (err < 0) {
789 pr_warn(" debugfs register failed.\n");
790 iounmap(pmcdev->regbase);
791 return err;
792 }
793
794 pr_info(" initialized\n");
795 return 0;
796}
797module_init(pmc_core_probe)
798
799static void __exit pmc_core_remove(void)
800{
801 struct pmc_dev *pmcdev = &pmc;
802
803 pmc_core_dbgfs_unregister(pmcdev);
804 mutex_destroy(&pmcdev->lock);
805 iounmap(pmcdev->regbase);
806}
807module_exit(pmc_core_remove)
808
809MODULE_LICENSE("GPL v2");
810MODULE_DESCRIPTION("Intel PMC Core Driver");
811
