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27#include "mv_sas.h"
28
29int interrupt_coalescing = 0x80;
30
31static struct scsi_transport_template *mvs_stt;
32static const struct mvs_chip_info mvs_chips[] = {
33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
42};
43
44struct device_attribute *mvst_host_attrs[];
45
46#define SOC_SAS_NUM 2
47
48static struct scsi_host_template mvs_sht = {
49 .module = THIS_MODULE,
50 .name = DRV_NAME,
51 .queuecommand = sas_queuecommand,
52 .target_alloc = sas_target_alloc,
53 .slave_configure = sas_slave_configure,
54 .scan_finished = mvs_scan_finished,
55 .scan_start = mvs_scan_start,
56 .change_queue_depth = sas_change_queue_depth,
57 .bios_param = sas_bios_param,
58 .can_queue = 1,
59 .this_id = -1,
60 .sg_tablesize = SG_ALL,
61 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
62 .eh_device_reset_handler = sas_eh_device_reset_handler,
63 .eh_target_reset_handler = sas_eh_target_reset_handler,
64 .target_destroy = sas_target_destroy,
65 .ioctl = sas_ioctl,
66 .shost_attrs = mvst_host_attrs,
67 .track_queue_depth = 1,
68};
69
70static struct sas_domain_function_template mvs_transport_ops = {
71 .lldd_dev_found = mvs_dev_found,
72 .lldd_dev_gone = mvs_dev_gone,
73 .lldd_execute_task = mvs_queue_command,
74 .lldd_control_phy = mvs_phy_control,
75
76 .lldd_abort_task = mvs_abort_task,
77 .lldd_abort_task_set = mvs_abort_task_set,
78 .lldd_clear_aca = mvs_clear_aca,
79 .lldd_clear_task_set = mvs_clear_task_set,
80 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
81 .lldd_lu_reset = mvs_lu_reset,
82 .lldd_query_task = mvs_query_task,
83 .lldd_port_formed = mvs_port_formed,
84 .lldd_port_deformed = mvs_port_deformed,
85
86 .lldd_write_gpio = mvs_gpio_write,
87
88};
89
90static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
91{
92 struct mvs_phy *phy = &mvi->phy[phy_id];
93 struct asd_sas_phy *sas_phy = &phy->sas_phy;
94
95 phy->mvi = mvi;
96 phy->port = NULL;
97 timer_setup(&phy->timer, NULL, 0);
98 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
99 sas_phy->class = SAS;
100 sas_phy->iproto = SAS_PROTOCOL_ALL;
101 sas_phy->tproto = 0;
102 sas_phy->type = PHY_TYPE_PHYSICAL;
103 sas_phy->role = PHY_ROLE_INITIATOR;
104 sas_phy->oob_mode = OOB_NOT_CONNECTED;
105 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
106
107 sas_phy->id = phy_id;
108 sas_phy->sas_addr = &mvi->sas_addr[0];
109 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
110 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
111 sas_phy->lldd_phy = phy;
112}
113
114static void mvs_free(struct mvs_info *mvi)
115{
116 struct mvs_wq *mwq;
117 int slot_nr;
118
119 if (!mvi)
120 return;
121
122 if (mvi->flags & MVF_FLAG_SOC)
123 slot_nr = MVS_SOC_SLOTS;
124 else
125 slot_nr = MVS_CHIP_SLOT_SZ;
126
127 dma_pool_destroy(mvi->dma_pool);
128
129 if (mvi->tx)
130 dma_free_coherent(mvi->dev,
131 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
132 mvi->tx, mvi->tx_dma);
133 if (mvi->rx_fis)
134 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
135 mvi->rx_fis, mvi->rx_fis_dma);
136 if (mvi->rx)
137 dma_free_coherent(mvi->dev,
138 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
139 mvi->rx, mvi->rx_dma);
140 if (mvi->slot)
141 dma_free_coherent(mvi->dev,
142 sizeof(*mvi->slot) * slot_nr,
143 mvi->slot, mvi->slot_dma);
144
145 if (mvi->bulk_buffer)
146 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
147 mvi->bulk_buffer, mvi->bulk_buffer_dma);
148 if (mvi->bulk_buffer1)
149 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
150 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
151
152 MVS_CHIP_DISP->chip_iounmap(mvi);
153 if (mvi->shost)
154 scsi_host_put(mvi->shost);
155 list_for_each_entry(mwq, &mvi->wq_list, entry)
156 cancel_delayed_work(&mwq->work_q);
157 kfree(mvi->tags);
158 kfree(mvi);
159}
160
161#ifdef CONFIG_SCSI_MVSAS_TASKLET
162static void mvs_tasklet(unsigned long opaque)
163{
164 u32 stat;
165 u16 core_nr, i = 0;
166
167 struct mvs_info *mvi;
168 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
169
170 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
171 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
172
173 if (unlikely(!mvi))
174 BUG_ON(1);
175
176 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
177 if (!stat)
178 goto out;
179
180 for (i = 0; i < core_nr; i++) {
181 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
182 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
183 }
184out:
185 MVS_CHIP_DISP->interrupt_enable(mvi);
186
187}
188#endif
189
190static irqreturn_t mvs_interrupt(int irq, void *opaque)
191{
192 u32 core_nr;
193 u32 stat;
194 struct mvs_info *mvi;
195 struct sas_ha_struct *sha = opaque;
196#ifndef CONFIG_SCSI_MVSAS_TASKLET
197 u32 i;
198#endif
199
200 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
201 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
202
203 if (unlikely(!mvi))
204 return IRQ_NONE;
205#ifdef CONFIG_SCSI_MVSAS_TASKLET
206 MVS_CHIP_DISP->interrupt_disable(mvi);
207#endif
208
209 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
210 if (!stat) {
211 #ifdef CONFIG_SCSI_MVSAS_TASKLET
212 MVS_CHIP_DISP->interrupt_enable(mvi);
213 #endif
214 return IRQ_NONE;
215 }
216
217#ifdef CONFIG_SCSI_MVSAS_TASKLET
218 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
219#else
220 for (i = 0; i < core_nr; i++) {
221 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
222 MVS_CHIP_DISP->isr(mvi, irq, stat);
223 }
224#endif
225 return IRQ_HANDLED;
226}
227
228static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
229{
230 int i = 0, slot_nr;
231 char pool_name[32];
232
233 if (mvi->flags & MVF_FLAG_SOC)
234 slot_nr = MVS_SOC_SLOTS;
235 else
236 slot_nr = MVS_CHIP_SLOT_SZ;
237
238 spin_lock_init(&mvi->lock);
239 for (i = 0; i < mvi->chip->n_phy; i++) {
240 mvs_phy_init(mvi, i);
241 mvi->port[i].wide_port_phymap = 0;
242 mvi->port[i].port_attached = 0;
243 INIT_LIST_HEAD(&mvi->port[i].list);
244 }
245 for (i = 0; i < MVS_MAX_DEVICES; i++) {
246 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
247 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
248 mvi->devices[i].device_id = i;
249 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
250 }
251
252
253
254
255 mvi->tx = dma_alloc_coherent(mvi->dev,
256 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
257 &mvi->tx_dma, GFP_KERNEL);
258 if (!mvi->tx)
259 goto err_out;
260 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
261 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
262 &mvi->rx_fis_dma, GFP_KERNEL);
263 if (!mvi->rx_fis)
264 goto err_out;
265 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
266
267 mvi->rx = dma_alloc_coherent(mvi->dev,
268 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
269 &mvi->rx_dma, GFP_KERNEL);
270 if (!mvi->rx)
271 goto err_out;
272 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
273 mvi->rx[0] = cpu_to_le32(0xfff);
274 mvi->rx_cons = 0xfff;
275
276 mvi->slot = dma_alloc_coherent(mvi->dev,
277 sizeof(*mvi->slot) * slot_nr,
278 &mvi->slot_dma, GFP_KERNEL);
279 if (!mvi->slot)
280 goto err_out;
281 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
282
283 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
284 TRASH_BUCKET_SIZE,
285 &mvi->bulk_buffer_dma, GFP_KERNEL);
286 if (!mvi->bulk_buffer)
287 goto err_out;
288
289 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
290 TRASH_BUCKET_SIZE,
291 &mvi->bulk_buffer_dma1, GFP_KERNEL);
292 if (!mvi->bulk_buffer1)
293 goto err_out;
294
295 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
296 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
297 MVS_SLOT_BUF_SZ, 16, 0);
298 if (!mvi->dma_pool) {
299 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
300 goto err_out;
301 }
302 mvi->tags_num = slot_nr;
303
304
305 mvs_tag_init(mvi);
306 return 0;
307err_out:
308 return 1;
309}
310
311
312int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
313{
314 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
315 struct pci_dev *pdev = mvi->pdev;
316 if (bar_ex != -1) {
317
318
319
320 res_start = pci_resource_start(pdev, bar_ex);
321 res_len = pci_resource_len(pdev, bar_ex);
322 if (!res_start || !res_len)
323 goto err_out;
324
325 res_flag_ex = pci_resource_flags(pdev, bar_ex);
326 if (res_flag_ex & IORESOURCE_MEM)
327 mvi->regs_ex = ioremap(res_start, res_len);
328 else
329 mvi->regs_ex = (void *)res_start;
330 if (!mvi->regs_ex)
331 goto err_out;
332 }
333
334 res_start = pci_resource_start(pdev, bar);
335 res_len = pci_resource_len(pdev, bar);
336 if (!res_start || !res_len) {
337 iounmap(mvi->regs_ex);
338 mvi->regs_ex = NULL;
339 goto err_out;
340 }
341
342 res_flag = pci_resource_flags(pdev, bar);
343 mvi->regs = ioremap(res_start, res_len);
344
345 if (!mvi->regs) {
346 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
347 iounmap(mvi->regs_ex);
348 mvi->regs_ex = NULL;
349 goto err_out;
350 }
351
352 return 0;
353err_out:
354 return -1;
355}
356
357void mvs_iounmap(void __iomem *regs)
358{
359 iounmap(regs);
360}
361
362static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
363 const struct pci_device_id *ent,
364 struct Scsi_Host *shost, unsigned int id)
365{
366 struct mvs_info *mvi = NULL;
367 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
368
369 mvi = kzalloc(sizeof(*mvi) +
370 (1L << mvs_chips[ent->driver_data].slot_width) *
371 sizeof(struct mvs_slot_info), GFP_KERNEL);
372 if (!mvi)
373 return NULL;
374
375 mvi->pdev = pdev;
376 mvi->dev = &pdev->dev;
377 mvi->chip_id = ent->driver_data;
378 mvi->chip = &mvs_chips[mvi->chip_id];
379 INIT_LIST_HEAD(&mvi->wq_list);
380
381 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
382 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
383
384 mvi->id = id;
385 mvi->sas = sha;
386 mvi->shost = shost;
387
388 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
389 if (!mvi->tags)
390 goto err_out;
391
392 if (MVS_CHIP_DISP->chip_ioremap(mvi))
393 goto err_out;
394 if (!mvs_alloc(mvi, shost))
395 return mvi;
396err_out:
397 mvs_free(mvi);
398 return NULL;
399}
400
401static int pci_go_64(struct pci_dev *pdev)
402{
403 int rc;
404
405 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
406 if (rc) {
407 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
408 if (rc) {
409 dev_printk(KERN_ERR, &pdev->dev,
410 "32-bit DMA enable failed\n");
411 return rc;
412 }
413 }
414
415 return rc;
416}
417
418static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
419 const struct mvs_chip_info *chip_info)
420{
421 int phy_nr, port_nr; unsigned short core_nr;
422 struct asd_sas_phy **arr_phy;
423 struct asd_sas_port **arr_port;
424 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
425
426 core_nr = chip_info->n_host;
427 phy_nr = core_nr * chip_info->n_phy;
428 port_nr = phy_nr;
429
430 memset(sha, 0x00, sizeof(struct sas_ha_struct));
431 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
432 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
433 if (!arr_phy || !arr_port)
434 goto exit_free;
435
436 sha->sas_phy = arr_phy;
437 sha->sas_port = arr_port;
438 sha->core.shost = shost;
439
440 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
441 if (!sha->lldd_ha)
442 goto exit_free;
443
444 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
445
446 shost->transportt = mvs_stt;
447 shost->max_id = MVS_MAX_DEVICES;
448 shost->max_lun = ~0;
449 shost->max_channel = 1;
450 shost->max_cmd_len = 16;
451
452 return 0;
453exit_free:
454 kfree(arr_phy);
455 kfree(arr_port);
456 return -1;
457
458}
459
460static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
461 const struct mvs_chip_info *chip_info)
462{
463 int can_queue, i = 0, j = 0;
464 struct mvs_info *mvi = NULL;
465 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
466 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
467
468 for (j = 0; j < nr_core; j++) {
469 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
470 for (i = 0; i < chip_info->n_phy; i++) {
471 sha->sas_phy[j * chip_info->n_phy + i] =
472 &mvi->phy[i].sas_phy;
473 sha->sas_port[j * chip_info->n_phy + i] =
474 &mvi->port[i].sas_port;
475 }
476 }
477
478 sha->sas_ha_name = DRV_NAME;
479 sha->dev = mvi->dev;
480 sha->lldd_module = THIS_MODULE;
481 sha->sas_addr = &mvi->sas_addr[0];
482
483 sha->num_phys = nr_core * chip_info->n_phy;
484
485 if (mvi->flags & MVF_FLAG_SOC)
486 can_queue = MVS_SOC_CAN_QUEUE;
487 else
488 can_queue = MVS_CHIP_SLOT_SZ;
489
490 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
491 shost->can_queue = can_queue;
492 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
493 sha->core.shost = mvi->shost;
494}
495
496static void mvs_init_sas_add(struct mvs_info *mvi)
497{
498 u8 i;
499 for (i = 0; i < mvi->chip->n_phy; i++) {
500 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
501 mvi->phy[i].dev_sas_addr =
502 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
503 }
504
505 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
506}
507
508static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
509{
510 unsigned int rc, nhost = 0;
511 struct mvs_info *mvi;
512 struct mvs_prv_info *mpi;
513 irq_handler_t irq_handler = mvs_interrupt;
514 struct Scsi_Host *shost = NULL;
515 const struct mvs_chip_info *chip;
516
517 dev_printk(KERN_INFO, &pdev->dev,
518 "mvsas: driver version %s\n", DRV_VERSION);
519 rc = pci_enable_device(pdev);
520 if (rc)
521 goto err_out_enable;
522
523 pci_set_master(pdev);
524
525 rc = pci_request_regions(pdev, DRV_NAME);
526 if (rc)
527 goto err_out_disable;
528
529 rc = pci_go_64(pdev);
530 if (rc)
531 goto err_out_regions;
532
533 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
534 if (!shost) {
535 rc = -ENOMEM;
536 goto err_out_regions;
537 }
538
539 chip = &mvs_chips[ent->driver_data];
540 SHOST_TO_SAS_HA(shost) =
541 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
542 if (!SHOST_TO_SAS_HA(shost)) {
543 scsi_host_put(shost);
544 rc = -ENOMEM;
545 goto err_out_regions;
546 }
547
548 rc = mvs_prep_sas_ha_init(shost, chip);
549 if (rc) {
550 scsi_host_put(shost);
551 rc = -ENOMEM;
552 goto err_out_regions;
553 }
554
555 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
556
557 do {
558 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
559 if (!mvi) {
560 rc = -ENOMEM;
561 goto err_out_regions;
562 }
563
564 memset(&mvi->hba_info_param, 0xFF,
565 sizeof(struct hba_info_page));
566
567 mvs_init_sas_add(mvi);
568
569 mvi->instance = nhost;
570 rc = MVS_CHIP_DISP->chip_init(mvi);
571 if (rc) {
572 mvs_free(mvi);
573 goto err_out_regions;
574 }
575 nhost++;
576 } while (nhost < chip->n_host);
577 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
578#ifdef CONFIG_SCSI_MVSAS_TASKLET
579 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
580 (unsigned long)SHOST_TO_SAS_HA(shost));
581#endif
582
583 mvs_post_sas_ha_init(shost, chip);
584
585 rc = scsi_add_host(shost, &pdev->dev);
586 if (rc)
587 goto err_out_shost;
588
589 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
590 if (rc)
591 goto err_out_shost;
592 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
593 DRV_NAME, SHOST_TO_SAS_HA(shost));
594 if (rc)
595 goto err_not_sas;
596
597 MVS_CHIP_DISP->interrupt_enable(mvi);
598
599 scsi_scan_host(mvi->shost);
600
601 return 0;
602
603err_not_sas:
604 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
605err_out_shost:
606 scsi_remove_host(mvi->shost);
607err_out_regions:
608 pci_release_regions(pdev);
609err_out_disable:
610 pci_disable_device(pdev);
611err_out_enable:
612 return rc;
613}
614
615static void mvs_pci_remove(struct pci_dev *pdev)
616{
617 unsigned short core_nr, i = 0;
618 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
619 struct mvs_info *mvi = NULL;
620
621 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
622 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
623
624#ifdef CONFIG_SCSI_MVSAS_TASKLET
625 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
626#endif
627
628 sas_unregister_ha(sha);
629 sas_remove_host(mvi->shost);
630
631 MVS_CHIP_DISP->interrupt_disable(mvi);
632 free_irq(mvi->pdev->irq, sha);
633 for (i = 0; i < core_nr; i++) {
634 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
635 mvs_free(mvi);
636 }
637 kfree(sha->sas_phy);
638 kfree(sha->sas_port);
639 kfree(sha);
640 pci_release_regions(pdev);
641 pci_disable_device(pdev);
642 return;
643}
644
645static struct pci_device_id mvs_pci_table[] = {
646 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
647 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
648 {
649 .vendor = PCI_VENDOR_ID_MARVELL,
650 .device = 0x6440,
651 .subvendor = PCI_ANY_ID,
652 .subdevice = 0x6480,
653 .class = 0,
654 .class_mask = 0,
655 .driver_data = chip_6485,
656 },
657 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
658 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
659 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
660 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
661 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
662 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
663 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
664 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
665 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
666 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
667 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
668 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
669 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
670 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
671 {
672 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
673 .device = 0x9480,
674 .subvendor = PCI_ANY_ID,
675 .subdevice = 0x9480,
676 .class = 0,
677 .class_mask = 0,
678 .driver_data = chip_9480,
679 },
680 {
681 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
682 .device = 0x9445,
683 .subvendor = PCI_ANY_ID,
684 .subdevice = 0x9480,
685 .class = 0,
686 .class_mask = 0,
687 .driver_data = chip_9445,
688 },
689 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 },
690 { PCI_VDEVICE(OCZ, 0x1021), chip_9485},
691 { PCI_VDEVICE(OCZ, 0x1022), chip_9485},
692 { PCI_VDEVICE(OCZ, 0x1040), chip_9485},
693 { PCI_VDEVICE(OCZ, 0x1041), chip_9485},
694 { PCI_VDEVICE(OCZ, 0x1042), chip_9485},
695 { PCI_VDEVICE(OCZ, 0x1043), chip_9485},
696 { PCI_VDEVICE(OCZ, 0x1044), chip_9485},
697 { PCI_VDEVICE(OCZ, 0x1080), chip_9485},
698 { PCI_VDEVICE(OCZ, 0x1083), chip_9485},
699 { PCI_VDEVICE(OCZ, 0x1084), chip_9485},
700
701 { }
702};
703
704static struct pci_driver mvs_pci_driver = {
705 .name = DRV_NAME,
706 .id_table = mvs_pci_table,
707 .probe = mvs_pci_init,
708 .remove = mvs_pci_remove,
709};
710
711static ssize_t
712mvs_show_driver_version(struct device *cdev,
713 struct device_attribute *attr, char *buffer)
714{
715 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
716}
717
718static DEVICE_ATTR(driver_version,
719 S_IRUGO,
720 mvs_show_driver_version,
721 NULL);
722
723static ssize_t
724mvs_store_interrupt_coalescing(struct device *cdev,
725 struct device_attribute *attr,
726 const char *buffer, size_t size)
727{
728 unsigned int val = 0;
729 struct mvs_info *mvi = NULL;
730 struct Scsi_Host *shost = class_to_shost(cdev);
731 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
732 u8 i, core_nr;
733 if (buffer == NULL)
734 return size;
735
736 if (sscanf(buffer, "%u", &val) != 1)
737 return -EINVAL;
738
739 if (val >= 0x10000) {
740 mv_dprintk("interrupt coalescing timer %d us is"
741 "too long\n", val);
742 return strlen(buffer);
743 }
744
745 interrupt_coalescing = val;
746
747 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
748 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
749
750 if (unlikely(!mvi))
751 return -EINVAL;
752
753 for (i = 0; i < core_nr; i++) {
754 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
755 if (MVS_CHIP_DISP->tune_interrupt)
756 MVS_CHIP_DISP->tune_interrupt(mvi,
757 interrupt_coalescing);
758 }
759 mv_dprintk("set interrupt coalescing time to %d us\n",
760 interrupt_coalescing);
761 return strlen(buffer);
762}
763
764static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
765 struct device_attribute *attr, char *buffer)
766{
767 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
768}
769
770static DEVICE_ATTR(interrupt_coalescing,
771 S_IRUGO|S_IWUSR,
772 mvs_show_interrupt_coalescing,
773 mvs_store_interrupt_coalescing);
774
775
776struct task_struct *mvs_th;
777static int __init mvs_init(void)
778{
779 int rc;
780 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
781 if (!mvs_stt)
782 return -ENOMEM;
783
784 rc = pci_register_driver(&mvs_pci_driver);
785 if (rc)
786 goto err_out;
787
788 return 0;
789
790err_out:
791 sas_release_transport(mvs_stt);
792 return rc;
793}
794
795static void __exit mvs_exit(void)
796{
797 pci_unregister_driver(&mvs_pci_driver);
798 sas_release_transport(mvs_stt);
799}
800
801struct device_attribute *mvst_host_attrs[] = {
802 &dev_attr_driver_version,
803 &dev_attr_interrupt_coalescing,
804 NULL,
805};
806
807module_init(mvs_init);
808module_exit(mvs_exit);
809
810MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
811MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
812MODULE_VERSION(DRV_VERSION);
813MODULE_LICENSE("GPL");
814#ifdef CONFIG_PCI
815MODULE_DEVICE_TABLE(pci, mvs_pci_table);
816#endif
817
