1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 15#ifndef __RTL8822B_REG_H__ 16#define __RTL8822B_REG_H__ 17 18#include "../halmac/halmac_reg_8822b.h" 19#include "../halmac/halmac_bit_8822b.h" 20 21#define TXPKT_BUF_SELECT 0x69 22#define RXPKT_BUF_SELECT 0xA5 23#define DISABLE_TRXPKT_BUF_ACCESS 0x0 24 25/* Page 0 */ 26#define REG_LEDCFG2_8822B 0x004E /* need review */ 27#define REG_SPS0_CTRL_8822B 0x0011 /* need review: swlps */ 28 29#define REG_EFUSE_ACCESS_8822B (REG_PMC_DBG_CTRL2_8822B + 3) /*0x00CF*/ 30#define REG_AFE_XTAL_CTRL_8822B REG_AFE_CTRL1_8822B 31#define REG_AFE_PLL_CTRL_8822B REG_AFE_CTRL2_8822B 32 33/* Page 1 */ 34 35#define MSR (REG_CR_8822B + 2) 36 37/* for MSR 0x102 */ 38#define MSR_NOLINK 0x00 39#define MSR_ADHOC 0x01 40#define MSR_INFRA 0x02 41#define MSR_AP 0x03 42 43/*----------------------------------------------------- 44 * 45 * 0x0200h ~ 0x027Fh TXDMA Configuration 46 * 47 *----------------------------------------------------- 48 */ 49 50/*----------------------------------------------------- 51 * 52 * 0x0280h ~ 0x02FFh RXDMA Configuration 53 * 54 *----------------------------------------------------- 55 */ 56#define REG_RXDMA_CONTROL_8822B (REG_RXPKT_NUM_8822B + 2) /* 0x0286 */ 57 58/*----------------------------------------------------- 59 * 60 * 0x0300h ~ 0x03FFh PCIe 61 * 62 *----------------------------------------------------- 63 */ 64 65/* REG_HIMR3_8822B */ 66#define IMR_H2CDOK BIT_SETH2CDOK_MASK_8822B 67 68/* spec version 11 69 *----------------------------------------------------- 70 * 71 * 0x0400h ~ 0x047Fh Protocol Configuration 72 * 73 *----------------------------------------------------- 74 */ 75 76#define REG_MAX_AGGR_NUM_8822B (REG_PROT_MODE_CTRL_8822B + 2) /*0x04CA*/ 77 78/* for RRSR 0x440 */ 79#define RRSR_RSC_OFFSET 21 80#define RRSR_SHORT_OFFSET 23 81#define RRSR_RSC_BW_40M 0x600000 82#define RRSR_RSC_UPSUBCHNL 0x400000 83#define RRSR_RSC_LOWSUBCHNL 0x200000 84#define RRSR_1M BIT(0) 85#define RRSR_2M BIT(1) 86#define RRSR_5_5M BIT(2) 87#define RRSR_11M BIT(3) 88#define RRSR_6M BIT(4) 89#define RRSR_9M BIT(5) 90#define RRSR_12M BIT(6) 91#define RRSR_18M BIT(7) 92#define RRSR_24M BIT(8) 93#define RRSR_36M BIT(9) 94#define RRSR_48M BIT(10) 95#define RRSR_54M BIT(11) 96#define RRSR_MCS0 BIT(12) 97#define RRSR_MCS1 BIT(13) 98#define RRSR_MCS2 BIT(14) 99#define RRSR_MCS3 BIT(15) 100#define RRSR_MCS4 BIT(16) 101#define RRSR_MCS5 BIT(17) 102#define RRSR_MCS6 BIT(18) 103#define RRSR_MCS7 BIT(19) 104 105#define RRSR_ALL_CCK (RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M) 106#define RRSR_ALL_OFDM_AG \ 107 (RRSR_6M | RRSR_9M | RRSR_12M | RRSR_18M | RRSR_24M | RRSR_36M | \ 108 RRSR_48M | RRSR_54M) 109 110/*----------------------------------------------------- 111 * 112 * 0x0500h ~ 0x05FFh EDCA Configuration 113 * 114 *----------------------------------------------------- 115 */ 116 117#define REG_SIFS_TRX_8822B (REG_SIFS_8822B + 2) /*0x0516*/ 118 119/*----------------------------------------------------- 120 * 121 * 0x0600h ~ 0x07FFh WMAC Configuration 122 * 123 *----------------------------------------------------- 124 */ 125 126#define RATR_1M 0x00000001 127#define RATR_2M 0x00000002 128#define RATR_55M 0x00000004 129#define RATR_11M 0x00000008 130#define RATR_6M 0x00000010 131#define RATR_9M 0x00000020 132#define RATR_12M 0x00000040 133#define RATR_18M 0x00000080 134#define RATR_24M 0x00000100 135#define RATR_36M 0x00000200 136#define RATR_48M 0x00000400 137#define RATR_54M 0x00000800 138#define RATR_MCS0 0x00001000 139#define RATR_MCS1 0x00002000 140#define RATR_MCS2 0x00004000 141#define RATR_MCS3 0x00008000 142#define RATR_MCS4 0x00010000 143#define RATR_MCS5 0x00020000 144#define RATR_MCS6 0x00040000 145#define RATR_MCS7 0x00080000 146#define RATR_MCS8 0x00100000 147#define RATR_MCS9 0x00200000 148#define RATR_MCS10 0x00400000 149#define RATR_MCS11 0x00800000 150#define RATR_MCS12 0x01000000 151#define RATR_MCS13 0x02000000 152#define RATR_MCS14 0x04000000 153#define RATR_MCS15 0x08000000 154 155#define RATE_1M BIT(0) 156#define RATE_2M BIT(1) 157#define RATE_5_5M BIT(2) 158#define RATE_11M BIT(3) 159#define RATE_6M BIT(4) 160#define RATE_9M BIT(5) 161#define RATE_12M BIT(6) 162#define RATE_18M BIT(7) 163#define RATE_24M BIT(8) 164#define RATE_36M BIT(9) 165#define RATE_48M BIT(10) 166#define RATE_54M BIT(11) 167#define RATE_MCS0 BIT(12) 168#define RATE_MCS1 BIT(13) 169#define RATE_MCS2 BIT(14) 170#define RATE_MCS3 BIT(15) 171#define RATE_MCS4 BIT(16) 172#define RATE_MCS5 BIT(17) 173#define RATE_MCS6 BIT(18) 174#define RATE_MCS7 BIT(19) 175#define RATE_MCS8 BIT(20) 176#define RATE_MCS9 BIT(21) 177#define RATE_MCS10 BIT(22) 178#define RATE_MCS11 BIT(23) 179#define RATE_MCS12 BIT(24) 180#define RATE_MCS13 BIT(25) 181#define RATE_MCS14 BIT(26) 182#define RATE_MCS15 BIT(27) 183 184/* CAM definition */ 185 186#define CAM_NONE 0x0 187#define CAM_WEP40 0x01 188#define CAM_TKIP 0x02 189#define CAM_AES 0x04 190#define CAM_WEP104 0x05 191 192/*#define TOTAL_CAM_ENTRY 64*/ 193/*#define HALF_CAM_ENTRY 32*/ 194 195#define CAM_WRITE BIT(16) 196#define CAM_READ 0x00000000 197#define CAM_POLLINIG BIT(31) 198 199/********************************************* 200 * 8822BE IMR/ISR bits 201 ********************************************* 202 */ 203#define IMR_DISABLED 0x0 204/* IMR DW0(0x0060-0063) Bit 0-31 */ 205#define IMR_TIMER2 BIT(31) 206#define IMR_TIMER1 BIT(30) 207#define IMR_PSTIMEOUT BIT(29) 208#define IMR_GTINT4 BIT(28) 209#define IMR_GTINT3 BIT(27) 210#define IMR_TBDER BIT(26) 211#define IMR_TBDOK BIT(25) 212#define IMR_TSF_BIT32_TOGGLE BIT(24) 213#define IMR_BCNDMAINT0 BIT(20) 214#define IMR_BCNDOK0 BIT(16) 215#define IMR_HSISR_IND_ON_INT BIT(15) 216#define IMR_BCNDMAINT_E BIT(14) 217#define IMR_ATIMEND BIT(12) 218#define IMR_HISR1_IND_INT BIT(11) 219#define IMR_C2HCMD BIT(10) 220#define IMR_CPWM2 BIT(9) 221#define IMR_CPWM BIT(8) 222#define IMR_HIGHDOK BIT(7) 223#define IMR_MGNTDOK BIT(6) 224#define IMR_BKDOK BIT(5) 225#define IMR_BEDOK BIT(4) 226#define IMR_VIDOK BIT(3) 227#define IMR_VODOK BIT(2) 228#define IMR_RDU BIT(1) 229#define IMR_ROK BIT(0) 230 231/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 232#define IMR_TXFIFO_TH_INT_8822B BIT_TXFIFO_TH_INT_8822B 233#define IMR_BTON_STS_UPDATE_MASK_8822B BIT_BTON_STS_UPDATE_MASK_8822B 234#define IMR_MCUERR BIT(28) 235#define IMR_BCNDMAINT7 BIT(27) 236#define IMR_BCNDMAINT6 BIT(26) 237#define IMR_BCNDMAINT5 BIT(25) 238#define IMR_BCNDMAINT4 BIT(24) 239#define IMR_BCNDMAINT3 BIT(23) 240#define IMR_BCNDMAINT2 BIT(22) 241#define IMR_BCNDMAINT1 BIT(21) 242#define IMR_BCNDOK7 BIT(20) 243#define IMR_BCNDOK6 BIT(19) 244#define IMR_BCNDOK5 BIT(18) 245#define IMR_BCNDOK4 BIT(17) 246#define IMR_BCNDOK3 BIT(16) 247#define IMR_BCNDOK2 BIT(15) 248#define IMR_BCNDOK1 BIT(14) 249#define IMR_ATIMEND_E BIT(13) 250#define IMR_ATIMEND BIT(12) 251#define IMR_TXERR BIT(11) 252#define IMR_RXERR BIT(10) 253#define IMR_TXFOVW BIT(9) 254#define IMR_RXFOVW BIT(8) 255#define IMR_CPU_MGQ_TXDONE_MSK_8822B BIT_CPU_MGQ_TXDONE_MSK_8822B 256#define IMR_PS_TIMER_C_MSK_8822B BIT_PS_TIMER_C_MSK_8822B 257#define IMR_PS_TIMER_B_MSK_8822B BIT_PS_TIMER_B_MSK_8822B 258#define IMR_PS_TIMER_A_MSK_8822B BIT_PS_TIMER_A_MSK_8822B 259#define IMR_CPUMGQ_TX_TIMER_MSK_8822B BIT_CPUMGQ_TX_TIMER_MSK_8822B 260 261/********************************************* 262 * 8822BE EFUSE definition 263 ********************************************* 264 */ 265#define HWSET_MAX_SIZE 1024 266#define EFUSE_MAX_SECTION 64 267#define EFUSE_REAL_CONTENT_LEN 1024 268#define EFUSE_OOB_PROTECT_BYTES 18 269 270#define EEPROM_DEFAULT_THERMALMETER 0x12 271 272#define RTL8822B_EEPROM_ID 0x8129 273 274#define PPG_BB_GAIN_2G_TXA_OFFSET_8822B 0xEE 275#define PPG_THERMAL_OFFSET_8822B 0xEF 276 277#define EEPROM_TX_PWR_INX_8822B 0x10 278 279#define EEPROM_CHANNEL_PLAN_8822B 0xB8 280#define EEPROM_XTAL_8822B 0xB9 281#define EEPROM_THERMAL_METER_8822B 0xBA 282#define EEPROM_IQK_LCK_8822B 0xBB 283#define EEPROM_2G_5G_PA_TYPE_8822B 0xBC 284/* PATH A & PATH B */ 285#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBD 286/* PATH C & PATH D */ 287#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B 0xBE 288/* PATH A & PATH B */ 289#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBF 290/* PATH C & PATH D */ 291#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B 0xC0 292 293#define EEPROM_RF_BOARD_OPTION_8822B 0xC1 294#define EEPROM_FEATURE_OPTION_8822B 0xC2 295#define EEPROM_RF_BT_SETTING_8822B 0xC3 296#define EEPROM_VERSION_8822B 0xC4 297#define EEPROM_CUSTOM_ID_8822B 0xC5 298#define EEPROM_TX_BBSWING_2G_8822B 0xC6 299#define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8 300#define EEPROM_RF_ANTENNA_OPT_8822B 0xC9 301#define EEPROM_RFE_OPTION_8822B 0xCA 302#define EEPROM_COUNTRY_CODE_8822B 0xCB 303 304#define EEPROM_VID 0xD6 305#define EEPROM_DID 0xD8 306#define EEPROM_SVID 0xDA 307#define EEPROM_SMID 0xDC 308 309/* RTL8822BU */ 310#define EEPROM_MAC_ADDR_8822BU 0x107 311#define EEPROM_VID_8822BU 0x100 312#define EEPROM_PID_8822BU 0x102 313#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU 0x104 314#define EEPROM_USB_MODE_8822BU 0x06 315 316/* RTL8822BS */ 317#define EEPROM_MAC_ADDR_8822BS 0x11A 318 319/* RTL8822BE */ 320#define EEPROM_MAC_ADDR_8822BE 0xD0 321 322/* ------------------------- */ 323 324#define STOPBECON BIT(6) 325#define STOPHIGHT BIT(5) 326#define STOPMGT BIT(4) 327#define STOPVO BIT(3) 328#define STOPVI BIT(2) 329#define STOPBE BIT(1) 330#define STOPBK BIT(0) 331 332#define RCR_APPFCS BIT(31) 333#define RCR_APP_MIC BIT(30) 334#define RCR_APP_ICV BIT(29) 335#define RCR_APP_PHYST_RXFF BIT(28) 336#define RCR_APP_BA_SSN BIT(27) 337#define RCR_VHT_DACK BIT(26) 338#define RCR_ENMBID BIT(24) 339#define RCR_LSIGEN BIT(23) 340#define RCR_MFBEN BIT(22) 341#define RCR_HTC_LOC_CTRL BIT(14) 342#define RCR_AMF BIT(13) 343#define RCR_ACF BIT(12) 344#define RCR_ADF BIT(11) 345#define RCR_AICV BIT(9) 346#define RCR_ACRC32 BIT(8) 347#define RCR_CBSSID_BCN BIT(7) 348#define RCR_CBSSID_DATA BIT(6) 349#define RCR_CBSSID RCR_CBSSID_DATA 350#define RCR_APWRMGT BIT(5) 351#define RCR_ADD3 BIT(4) 352#define RCR_AB BIT(3) 353#define RCR_AM BIT(2) 354#define RCR_APM BIT(1) 355#define RCR_AAP BIT(0) 356#define RCR_MXDMA_OFFSET 8 357#define RCR_FIFO_OFFSET 13 358 359#define RSV_CTRL 0x001C 360#define RD_CTRL 0x0524 361 362#define REG_USB_INFO_8822B 0xFE17 363#define REG_USB_SPECIAL_OPTION_8822B 0xFE55 364#define REG_USB_DMA_AGG_TO_8822B 0xFE5B 365#define REG_USB_AGG_TO_8822B 0xFE5C 366#define REG_USB_AGG_TH_8822B 0xFE5D 367 368#define REG_USB_VID_8822B 0xFE60 369#define REG_USB_PID_8822B 0xFE62 370#define REG_USB_OPTIONAL_8822B 0xFE64 371#define REG_USB_CHIRP_K_8822B 0xFE65 372#define REG_USB_PHY_8822B 0xFE66 373#define REG_USB_MAC_ADDR_8822B 0xFE70 374#define REG_USB_HRPWM_8822B 0xFE58 375#define REG_USB_HCPWM_8822B 0xFE57 376 377#define SW18_FPWM BIT(3) 378 379#define ISO_MD2PP BIT(0) 380#define ISO_UA2USB BIT(1) 381#define ISO_UD2CORE BIT(2) 382#define ISO_PA2PCIE BIT(3) 383#define ISO_PD2CORE BIT(4) 384#define ISO_IP2MAC BIT(5) 385#define ISO_DIOP BIT(6) 386#define ISO_DIOE BIT(7) 387#define ISO_EB2CORE BIT(8) 388#define ISO_DIOR BIT(9) 389 390#define PWC_EV25V BIT(14) 391#define PWC_EV12V BIT(15) 392 393#define FEN_BBRSTB BIT(0) 394#define FEN_BB_GLB_RSTN BIT(1) 395#define FEN_USBA BIT(2) 396#define FEN_UPLL BIT(3) 397#define FEN_USBD BIT(4) 398#define FEN_DIO_PCIE BIT(5) 399#define FEN_PCIEA BIT(6) 400#define FEN_PPLL BIT(7) 401#define FEN_PCIED BIT(8) 402#define FEN_DIOE BIT(9) 403#define FEN_CPUEN BIT(10) 404#define FEN_DCORE BIT(11) 405#define FEN_ELDR BIT(12) 406#define FEN_DIO_RF BIT(13) 407#define FEN_HWPDN BIT(14) 408#define FEN_MREGEN BIT(15) 409 410#define PFM_LDALL BIT(0) 411#define PFM_ALDN BIT(1) 412#define PFM_LDKP BIT(2) 413#define PFM_WOWL BIT(3) 414#define EN_PDN BIT(4) 415#define PDN_PL BIT(5) 416#define APFM_ONMAC BIT(8) 417#define APFM_OFF BIT(9) 418#define APFM_RSM BIT(10) 419#define AFSM_HSUS BIT(11) 420#define AFSM_PCIE BIT(12) 421#define APDM_MAC BIT(13) 422#define APDM_HOST BIT(14) 423#define APDM_HPDN BIT(15) 424#define RDY_MACON BIT(16) 425#define SUS_HOST BIT(17) 426#define ROP_ALD BIT(20) 427#define ROP_PWR BIT(21) 428#define ROP_SPS BIT(22) 429#define SOP_MRST BIT(25) 430#define SOP_FUSE BIT(26) 431#define SOP_ABG BIT(27) 432#define SOP_AMB BIT(28) 433#define SOP_RCK BIT(29) 434#define SOP_A8M BIT(30) 435#define XOP_BTCK BIT(31) 436 437#define ANAD16V_EN BIT(0) 438#define ANA8M BIT(1) 439#define MACSLP BIT(4) 440#define LOADER_CLK_EN BIT(5) 441#define _80M_SSC_DIS BIT(7) 442#define _80M_SSC_EN_HO BIT(8) 443#define PHY_SSC_RSTB BIT(9) 444#define SEC_CLK_EN BIT(10) 445#define MAC_CLK_EN BIT(11) 446#define SYS_CLK_EN BIT(12) 447#define RING_CLK_EN BIT(13) 448 449#define BOOT_FROM_EEPROM BIT(4) 450#define EEPROM_EN BIT(5) 451 452#define AFE_BGEN BIT(0) 453#define AFE_MBEN BIT(1) 454#define MAC_ID_EN BIT(7) 455 456#define WLOCK_ALL BIT(0) 457#define WLOCK_00 BIT(1) 458#define WLOCK_04 BIT(2) 459#define WLOCK_08 BIT(3) 460#define WLOCK_40 BIT(4) 461#define R_DIS_PRST_0 BIT(5) 462#define R_DIS_PRST_1 BIT(6) 463#define LOCK_ALL_EN BIT(7) 464 465#define RF_EN BIT(0) 466#define RF_RSTB BIT(1) 467#define RF_SDMRSTB BIT(2) 468 469#define LDA15_EN BIT(0) 470#define LDA15_STBY BIT(1) 471#define LDA15_OBUF BIT(2) 472#define LDA15_REG_VOS BIT(3) 473#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 474 475#define LDV12_EN BIT(0) 476#define LDV12_SDBY BIT(1) 477#define LPLDO_HSM BIT(2) 478#define LPLDO_LSM_DIS BIT(3) 479#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 480 481#define XTAL_EN BIT(0) 482#define XTAL_BSEL BIT(1) 483#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 484#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 485#define XTAL_GATE_USB BIT(8) 486#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 487#define XTAL_GATE_AFE BIT(11) 488#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 489#define XTAL_RF_GATE BIT(14) 490#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 491#define XTAL_GATE_DIG BIT(17) 492#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 493#define XTAL_BT_GATE BIT(20) 494#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 495#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 496 497#define CKDLY_AFE BIT(26) 498#define CKDLY_USB BIT(27) 499#define CKDLY_DIG BIT(28) 500#define CKDLY_BT BIT(29) 501 502#define APLL_EN BIT(0) 503#define APLL_320_EN BIT(1) 504#define APLL_FREF_SEL BIT(2) 505#define APLL_EDGE_SEL BIT(3) 506#define APLL_WDOGB BIT(4) 507#define APLL_LPFEN BIT(5) 508 509#define APLL_REF_CLK_13MHZ 0x1 510#define APLL_REF_CLK_19_2MHZ 0x2 511#define APLL_REF_CLK_20MHZ 0x3 512#define APLL_REF_CLK_25MHZ 0x4 513#define APLL_REF_CLK_26MHZ 0x5 514#define APLL_REF_CLK_38_4MHZ 0x6 515#define APLL_REF_CLK_40MHZ 0x7 516 517#define APLL_320EN BIT(14) 518#define APLL_80EN BIT(15) 519#define APLL_1MEN BIT(24) 520 521#define ALD_EN BIT(18) 522#define EF_PD BIT(19) 523#define EF_FLAG BIT(31) 524 525#define EF_TRPT BIT(7) 526#define LDOE25_EN BIT(31) 527 528#define RSM_EN BIT(0) 529#define TIMER_EN BIT(4) 530 531#define TRSW0EN BIT(2) 532#define TRSW1EN BIT(3) 533#define EROM_EN BIT(4) 534#define EN_BT BIT(5) 535#define EN_UART BIT(8) 536#define UART_910 BIT(9) 537#define EN_PMAC BIT(10) 538#define SIC_SWRST BIT(11) 539#define EN_SIC BIT(12) 540#define SIC_23 BIT(13) 541#define EN_HDP BIT(14) 542#define SIC_LBK BIT(15) 543 544#define LED0PL BIT(4) 545#define LED1PL BIT(12) 546#define LED0DIS BIT(7) 547 548#define MCUFWDL_EN BIT(0) 549#define MCUFWDL_RDY BIT(1) 550#define FWDL_CHKSUM_RPT BIT(2) 551#define MACINI_RDY BIT(3) 552#define BBINI_RDY BIT(4) 553#define RFINI_RDY BIT(5) 554#define WINTINI_RDY BIT(6) 555#define CPRST BIT(23) 556 557#define XCLK_VLD BIT(0) 558#define ACLK_VLD BIT(1) 559#define UCLK_VLD BIT(2) 560#define PCLK_VLD BIT(3) 561#define PCIRSTB BIT(4) 562#define V15_VLD BIT(5) 563#define TRP_B15V_EN BIT(7) 564#define SIC_IDLE BIT(8) 565#define BD_MAC2 BIT(9) 566#define BD_MAC1 BIT(10) 567#define IC_MACPHY_MODE BIT(11) 568#define VENDOR_ID BIT(19) 569#define PAD_HWPD_IDN BIT(22) 570#define TRP_VAUX_EN BIT(23) 571#define TRP_BT_EN BIT(24) 572#define BD_PKG_SEL BIT(25) 573#define BD_HCI_SEL BIT(26) 574#define TYPE_ID BIT(27) 575 576#define CHIP_VER_RTL_MASK 0xF000 577#define CHIP_VER_RTL_SHIFT 12 578 579#define REG_LBMODE_8822B (REG_CR_8822B + 3) 580 581#define HCI_TXDMA_EN BIT(0) 582#define HCI_RXDMA_EN BIT(1) 583#define TXDMA_EN BIT(2) 584#define RXDMA_EN BIT(3) 585#define PROTOCOL_EN BIT(4) 586#define SCHEDULE_EN BIT(5) 587#define MACTXEN BIT(6) 588#define MACRXEN BIT(7) 589#define ENSWBCN BIT(8) 590#define ENSEC BIT(9) 591 592#define _NETTYPE(x) (((x) & 0x3) << 16) 593#define MASK_NETTYPE 0x30000 594#define NT_NO_LINK 0x0 595#define NT_LINK_AD_HOC 0x1 596#define NT_LINK_AP 0x2 597#define NT_AS_AP 0x3 598 599#define _LBMODE(x) (((x) & 0xF) << 24) 600#define MASK_LBMODE 0xF000000 601#define LOOPBACK_NORMAL 0x0 602#define LOOPBACK_IMMEDIATELY 0xB 603#define LOOPBACK_MAC_DELAY 0x3 604#define LOOPBACK_PHY 0x1 605#define LOOPBACK_DMA 0x7 606 607#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 608#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 609#define _PSRX_MASK 0xF 610#define _PSTX_MASK 0xF0 611#define _PSRX(x) (x) 612#define _PSTX(x) ((x) << 4) 613 614#define PBP_64 0x0 615#define PBP_128 0x1 616#define PBP_256 0x2 617#define PBP_512 0x3 618#define PBP_1024 0x4 619 620#define RXDMA_ARBBW_EN BIT(0) 621#define RXSHFT_EN BIT(1) 622#define RXDMA_AGG_EN BIT(2) 623#define QS_VO_QUEUE BIT(8) 624#define QS_VI_QUEUE BIT(9) 625#define QS_BE_QUEUE BIT(10) 626#define QS_BK_QUEUE BIT(11) 627#define QS_MANAGER_QUEUE BIT(12) 628#define QS_HIGH_QUEUE BIT(13) 629 630#define HQSEL_VOQ BIT(0) 631#define HQSEL_VIQ BIT(1) 632#define HQSEL_BEQ BIT(2) 633#define HQSEL_BKQ BIT(3) 634#define HQSEL_MGTQ BIT(4) 635#define HQSEL_HIQ BIT(5) 636 637#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14) 638#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12) 639#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10) 640#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8) 641#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6) 642#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4) 643 644#define QUEUE_LOW 1 645#define QUEUE_NORMAL 2 646#define QUEUE_HIGH 3 647 648#define _LLT_NO_ACTIVE 0x0 649#define _LLT_WRITE_ACCESS 0x1 650#define _LLT_READ_ACCESS 0x2 651 652#define _LLT_INIT_DATA(x) ((x) & 0xFF) 653#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 654#define _LLT_OP(x) (((x) & 0x3) << 30) 655#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 656 657#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 658#define BB_WRITE_EN BIT(30) 659#define BB_READ_EN BIT(31) 660 661#define _HPQ(x) ((x) & 0xFF) 662#define _LPQ(x) (((x) & 0xFF) << 8) 663#define _PUBQ(x) (((x) & 0xFF) << 16) 664#define _NPQ(x) ((x) & 0xFF) 665 666#define HPQ_PUBLIC_DIS BIT(24) 667#define LPQ_PUBLIC_DIS BIT(25) 668#define LD_RQPN BIT(31) 669 670#define BCN_VALID BIT(16) 671#define BCN_HEAD(x) (((x) & 0xFF) << 8) 672#define BCN_HEAD_MASK 0xFF00 673 674#define BLK_DESC_NUM_SHIFT 4 675#define BLK_DESC_NUM_MASK 0xF 676 677#define DROP_DATA_EN BIT(9) 678 679#define EN_AMPDU_RTY_NEW BIT(7) 680 681#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 682 683#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 684#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 685 686#define RATE_REG_BITMAP_ALL 0xFFFFF 687 688#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 689 690#define _RRSR_RSC(x) (((x) & 0x3) << 21) 691#define RRSR_RSC_RESERVED 0x0 692#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 693#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 694#define RRSR_RSC_DUPLICATE_MODE 0x3 695 696#define USE_SHORT_G1 BIT(20) 697 698#define _AGGLMT_MCS0(x) ((x) & 0xF) 699#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 700#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 701#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 702#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 703#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 704#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 705#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 706 707#define RETRY_LIMIT_SHORT_SHIFT 8 708#define RETRY_LIMIT_LONG_SHIFT 0 709 710#define _DARF_RC1(x) ((x) & 0x1F) 711#define _DARF_RC2(x) (((x) & 0x1F) << 8) 712#define _DARF_RC3(x) (((x) & 0x1F) << 16) 713#define _DARF_RC4(x) (((x) & 0x1F) << 24) 714#define _DARF_RC5(x) ((x) & 0x1F) 715#define _DARF_RC6(x) (((x) & 0x1F) << 8) 716#define _DARF_RC7(x) (((x) & 0x1F) << 16) 717#define _DARF_RC8(x) (((x) & 0x1F) << 24) 718 719#define _RARF_RC1(x) ((x) & 0x1F) 720#define _RARF_RC2(x) (((x) & 0x1F) << 8) 721#define _RARF_RC3(x) (((x) & 0x1F) << 16) 722#define _RARF_RC4(x) (((x) & 0x1F) << 24) 723#define _RARF_RC5(x) ((x) & 0x1F) 724#define _RARF_RC6(x) (((x) & 0x1F) << 8) 725#define _RARF_RC7(x) (((x) & 0x1F) << 16) 726#define _RARF_RC8(x) (((x) & 0x1F) << 24) 727 728#define AC_PARAM_TXOP_LIMIT_OFFSET 16 729#define AC_PARAM_ECW_MAX_OFFSET 12 730#define AC_PARAM_ECW_MIN_OFFSET 8 731#define AC_PARAM_AIFS_OFFSET 0 732 733#define _AIFS(x) (x) 734#define _ECW_MAX_MIN(x) ((x) << 8) 735#define _TXOP_LIMIT(x) ((x) << 16) 736 737#define _BCNIFS(x) ((x) & 0xFF) 738#define _BCNECW(x) ((((x) & 0xF)) << 8) 739 740#define _LRL(x) ((x) & 0x3F) 741#define _SRL(x) (((x) & 0x3F) << 8) 742 743#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 744#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 745 746#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 747#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 748 749#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 750 751#define DIS_EDCA_CNT_DWN BIT(11) 752 753#define EN_MBSSID BIT(1) 754#define EN_TXBCN_RPT BIT(2) 755#define EN_BCN_FUNCTION BIT(3) 756 757#define TSFTR_RST BIT(0) 758#define TSFTR1_RST BIT(1) 759 760#define STOP_BCNQ BIT(6) 761 762#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 763#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 764 765#define ACMHW_HW_EN BIT(0) 766#define ACMHW_BEQ_EN BIT(1) 767#define ACMHW_VIQ_EN BIT(2) 768#define ACMHW_VOQ_EN BIT(3) 769#define ACMHW_BEQ_STATUS BIT(4) 770#define ACMHW_VIQ_STATUS BIT(5) 771#define ACMHW_VOQ_STATUS BIT(6) 772 773#define APSDOFF BIT(6) 774#define APSDOFF_STATUS BIT(7) 775 776#define BW_20MHZ BIT(2) 777 778#define RATE_BITMAP_ALL 0xFFFFF 779 780#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 781 782#define TSFRST BIT(0) 783#define DIS_GCLK BIT(1) 784#define PAD_SEL BIT(2) 785#define PWR_ST BIT(6) 786#define PWRBIT_OW_EN BIT(7) 787#define ACRC BIT(8) 788#define CFENDFORM BIT(9) 789#define ICV BIT(10) 790 791#define AAP BIT(0) 792#define APM BIT(1) 793#define AM BIT(2) 794#define AB BIT(3) 795#define ADD3 BIT(4) 796#define APWRMGT BIT(5) 797#define CBSSID BIT(6) 798#define CBSSID_DATA BIT(6) 799#define CBSSID_BCN BIT(7) 800#define ACRC32 BIT(8) 801#define AICV BIT(9) 802#define ADF BIT(11) 803#define ACF BIT(12) 804#define AMF BIT(13) 805#define HTC_LOC_CTRL BIT(14) 806#define UC_DATA_EN BIT(16) 807#define BM_DATA_EN BIT(17) 808#define MFBEN BIT(22) 809#define LSIGEN BIT(23) 810#define EN_MBID BIT(24) 811#define APP_BASSN BIT(27) 812#define APP_PHYSTS BIT(28) 813#define APP_ICV BIT(29) 814#define APP_MIC BIT(30) 815#define APP_FCS BIT(31) 816 817#define _MIN_SPACE(x) ((x) & 0x7) 818#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 819 820#define RXERR_TYPE_OFDM_PPDU 0 821#define RXERR_TYPE_OFDM_FALSE_ALARM 1 822#define RXERR_TYPE_OFDM_MPDU_OK 2 823#define RXERR_TYPE_OFDM_MPDU_FAIL 3 824#define RXERR_TYPE_CCK_PPDU 4 825#define RXERR_TYPE_CCK_FALSE_ALARM 5 826#define RXERR_TYPE_CCK_MPDU_OK 6 827#define RXERR_TYPE_CCK_MPDU_FAIL 7 828#define RXERR_TYPE_HT_PPDU 8 829#define RXERR_TYPE_HT_FALSE_ALARM 9 830#define RXERR_TYPE_HT_MPDU_TOTAL 10 831#define RXERR_TYPE_HT_MPDU_OK 11 832#define RXERR_TYPE_HT_MPDU_FAIL 12 833#define RXERR_TYPE_RX_FULL_DROP 15 834 835#define RXERR_COUNTER_MASK 0xFFFFF 836#define RXERR_RPT_RST BIT(27) 837#define _RXERR_RPT_SEL(type) ((type) << 28) 838 839#define SCR_TX_USE_DK BIT(0) 840#define SCR_RX_USE_DK BIT(1) 841#define SCR_TX_ENC_ENABLE BIT(2) 842#define SRC_RX_DEC_ENABLE BIT(3) 843#define SCR_SK_BY_A2 BIT(4) 844#define SCR_NO_SKMC BIT(5) 845#define SCR_TXBCUSEDK BIT(6) 846#define SCR_RXBCUSEDK BIT(7) 847 848#define USB_IS_HIGH_SPEED 0 849#define USB_IS_FULL_SPEED 1 850#define USB_SPEED_MASK BIT(5) 851 852#define USB_NORMAL_SIE_EP_MASK 0xF 853#define USB_NORMAL_SIE_EP_SHIFT 4 854 855#define USB_TEST_EP_MASK 0x30 856#define USB_TEST_EP_SHIFT 4 857 858#define USB_AGG_EN BIT(3) 859 860#define MAC_ADDR_LEN 6 861#define LAST_ENTRY_OF_TX_PKT_BUFFER 175 862 863#define POLLING_LLT_THRESHOLD 20 864#define POLLING_READY_TIMEOUT_COUNT 3000 865 866#define MAX_MSS_DENSITY_2T 0x13 867#define MAX_MSS_DENSITY_1T 0x0A 868 869#define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6)) 870#define EPROM_CMD_CONFIG 0x3 871#define EPROM_CMD_LOAD 1 872 873#define HAL_8822B_HW_GPIO_WPS_BIT BIT(2) 874 875/*----------------------------------------------------- 876 * BB / RF register 877 *----------------------------------------------------- 878 */ 879 880#define RFPGA0_XA_HSSIPARAMETER1 0x820 881#define RFPGA0_XA_HSSIPARAMETER2 0x824 882#define RFPGA0_XB_HSSIPARAMETER1 0x828 883#define RFPGA0_XB_HSSIPARAMETER2 0x82c 884#define RCCAONSEC 0x838 885 886#define RFPGA0_XA_LSSIPARAMETER 0x840 887#define RFPGA0_XB_LSSIPARAMETER 0x844 888#define RL1PEAKTH 0x848 889 890#define RFPGA0_RFWAKEUPPARAMETER 0x850 891#define RFPGA0_RFSLEEPUPPARAMETER 0x854 892 893#define RFPGA0_XAB_SWITCHCONTROL 0x858 894#define RFPGA0_XCD_SWITCHCONTROL 0x85c 895 896#define RFPGA0_XA_RFINTERFACEOE 0x860 897#define RFC_AREA 0x860 898#define RFPGA0_XB_RFINTERFACEOE 0x864 899 900#define RFPGA0_XAB_RFINTERFACESW 0x870 901#define RFPGA0_XCD_RFINTERFACESW 0x874 902 903#define RFPGA0_XAB_RF_PARA_METER 0x878 904#define RFPGA0_XCD_RF_PARA_METER 0x87c 905 906#define RFPGA0_ANALOGPARAMETER1 0x880 907#define RFPGA0_ANALOGPARAMETER2 0x884 908#define RFPGA0_ANALOGPARAMETER3 0x888 909#define RFPGA0_ANALOGPARAMETER4 0x88c 910 911#define RFPGA0_XA_LSSIREADBACK 0x8a0 912#define RFPGA0_XB_LSSIREADBACK 0x8a4 913#define RFPGA0_XC_LSSIREADBACK 0x8a8 914/*#define RFPGA0_XD_LSSIREADBACK 0x8ac*/ 915#define RRFMOD 0x8ac 916#define RHSSIREAD_8822BE 0x8b0 917 918#define RFPGA0_PSDREPORT 0x8b4 919#define TRANSCEIVEA_HSPI_READBACK 0x8b8 920#define TRANSCEIVEB_HSPI_READBACK 0x8bc 921/*#define REG_SC_CNT_8822B 0x8c4*/ 922#define RADC_BUF_CLK 0x8c4 923#define RFPGA0_XAB_RFINTERFACERB 0x8e0 924#define RFPGA0_XCD_RFINTERFACERB 0x8e4 925 926/* PageB(0xB00) */ 927 928/*Page C*/ 929 930#define RA_TXPWRTRAING 0xc54 931#define RB_TXPWRTRAING 0xe54 932 933#define RA_LSSIWRITE_8822B 0xc90 934#define RB_LSSIWRITE_8822B 0xe90 935 936#define RA_PIREAD_8822B 0xd04 937#define RB_PIREAD_8822B 0xd44 938#define RA_SIREAD_8822B 0xd08 939#define RB_SIREAD_8822B 0xd48 940 941#define RZEBRA1_HSSIENABLE 0x0 942#define RZEBRA1_TRXENABLE1 0x1 943#define RZEBRA1_TRXENABLE2 0x2 944#define RZEBRA1_AGC 0x4 945#define RZEBRA1_CHARGEPUMP 0x5 946#define RZEBRA1_CHANNEL 0x7 947 948#define RZEBRA1_TXGAIN 0x8 949#define RZEBRA1_TXLPF 0x9 950#define RZEBRA1_RXLPF 0xb 951#define RZEBRA1_RXHPFCORNER 0xc 952 953#define RGLOBALCTRL 0 954#define RRTL8256_TXLPF 19 955#define RRTL8256_RXLPF 11 956#define RRTL8258_TXLPF 0x11 957#define RRTL8258_RXLPF 0x13 958#define RRTL8258_RSSILPF 0xa 959 960#define RF_AC 0x00 961 962#define RF_IQADJ_G1 0x01 963#define RF_IQADJ_G2 0x02 964#define RF_POW_TRSW 0x05 965 966#define RF_GAIN_RX 0x06 967#define RF_GAIN_TX 0x07 968 969#define RF_TXM_IDAC 0x08 970#define RF_BS_IQGEN 0x0F 971 972#define RF_MODE1 0x10 973#define RF_MODE2 0x11 974 975#define RF_RX_AGC_HP 0x12 976#define RF_TX_AGC 0x13 977#define RF_BIAS 0x14 978#define RF_IPA 0x15 979#define RF_POW_ABILITY 0x17 980#define RF_MODE_AG 0x18 981#define RRFCHANNEL 0x18 982#define RF_CHNLBW 0x18 983#define RF_TOP 0x19 984 985#define RF_RX_G1 0x1A 986#define RF_RX_G2 0x1B 987 988#define RF_RX_BB2 0x1C 989#define RF_RX_BB1 0x1D 990 991#define RF_RCK1 0x1E 992#define RF_RCK2 0x1F 993 994#define RF_TX_G1 0x20 995#define RF_TX_G2 0x21 996#define RF_TX_G3 0x22 997 998#define RF_TX_BB1 0x23 999#define RF_T_METER 0x42 1000
1001#define RF_SYN_G1 0x25 1002#define RF_SYN_G2 0x26 1003#define RF_SYN_G3 0x27 1004#define RF_SYN_G4 0x28 1005#define RF_SYN_G5 0x29 1006#define RF_SYN_G6 0x2A 1007#define RF_SYN_G7 0x2B 1008#define RF_SYN_G8 0x2C 1009 1010#define RF_RCK_OS 0x30 1011#define RF_TXPA_G1 0x31 1012#define RF_TXPA_G2 0x32 1013#define RF_TXPA_G3 0x33 1014 1015#define RF_TX_BIAS_A 0x35 1016#define RF_TX_BIAS_D 0x36 1017#define RF_LOBF_9 0x38 1018#define RF_RXRF_A3 0x3C 1019#define RF_TRSW 0x3F 1020 1021#define RF_TXRF_A2 0x41 1022#define RF_TXPA_G4 0x46 1023#define RF_TXPA_A4 0x4B 1024 1025#define RF_APK 0x63 1026 1027#define RF_WE_LUT 0xEF 1028 1029#define BBBRESETB 0x100 1030#define BGLOBALRESETB 0x200 1031#define BOFDMTXSTART 0x4 1032#define BCCKTXSTART 0x8 1033#define BCRC32DEBUG 0x100 1034#define BPMACLOOPBACK 0x10 1035#define BTXLSIG 0xffffff 1036#define BOFDMTXRATE 0xf 1037#define BOFDMTXRESERVED 0x10 1038#define BOFDMTXLENGTH 0x1ffe0 1039#define BOFDMTXPARITY 0x20000 1040#define BTXHTSIG1 0xffffff 1041#define BTXHTMCSRATE 0x7f 1042#define BTXHTBW 0x80 1043#define BTXHTLENGTH 0xffff00 1044#define BTXHTSIG2 0xffffff 1045#define BTXHTSMOOTHING 0x1 1046#define BTXHTSOUNDING 0x2 1047#define BTXHTRESERVED 0x4 1048#define BTXHTAGGREATION 0x8 1049#define BTXHTSTBC 0x30 1050#define BTXHTADVANCECODING 0x40 1051#define BTXHTSHORTGI 0x80 1052#define BTXHTNUMBERHT_LTF 0x300 1053#define BTXHTCRC8 0x3fc00 1054#define BCOUNTERRESET 0x10000 1055#define BNUMOFOFDMTX 0xffff 1056#define BNUMOFCCKTX 0xffff0000 1057#define BTXIDLEINTERVAL 0xffff 1058#define BOFDMSERVICE 0xffff0000 1059#define BTXMACHEADER 0xffffffff 1060#define BTXDATAINIT 0xff 1061#define BTXHTMODE 0x100 1062#define BTXDATATYPE 0x30000 1063#define BTXRANDOMSEED 0xffffffff 1064#define BCCKTXPREAMBLE 0x1 1065#define BCCKTXSFD 0xffff0000 1066#define BCCKTXSIG 0xff 1067#define BCCKTXSERVICE 0xff00 1068#define BCCKLENGTHEXT 0x8000 1069#define BCCKTXLENGHT 0xffff0000 1070#define BCCKTXCRC16 0xffff 1071#define BCCKTXSTATUS 0x1 1072#define BOFDMTXSTATUS 0x2 1073#define IS_BB_REG_OFFSET_92S(_offset) ((_offset >= 0x800) && (_offset <= 0xfff)) 1074 1075#define BRFMOD 0x1 1076#define BJAPANMODE 0x2 1077#define BCCKTXSC 0x30 1078/* Block & Path enable*/ 1079#define ROFDMCCKEN 0x808 1080#define BCCKEN 0x10000000 1081#define BOFDMEN 0x20000000 1082/* Rx antenna*/ 1083#define RRXPATH 0x808 1084#define BRXPATH 0xff 1085/* Tx antenna*/ 1086#define RTXPATH 0x80c 1087#define BTXPATH 0x0fffffff 1088/* for cck rx path selection*/ 1089#define RCCK_RX 0xa04 1090#define BCCK_RX 0x0c000000 1091/* Use LSIG for VHT length*/ 1092#define RVHTLEN_USE_LSIG 0x8c3 1093 1094#define BOFDMRXADCPHASE 0x10000 1095#define BOFDMTXDACPHASE 0x40000 1096#define BXATXAGC 0x3f 1097 1098#define BXBTXAGC 0xf00 1099#define BXCTXAGC 0xf000 1100#define BXDTXAGC 0xf0000 1101 1102#define BPASTART 0xf0000000 1103#define BTRSTART 0x00f00000 1104#define BRFSTART 0x0000f000 1105#define BBBSTART 0x000000f0 1106#define BBBCCKSTART 0x0000000f 1107#define BPAEND 0xf 1108#define BTREND 0x0f000000 1109#define BRFEND 0x000f0000 1110#define BCCAMASK 0x000000f0 1111#define BR2RCCAMASK 0x00000f00 1112#define BHSSI_R2TDELAY 0xf8000000 1113#define BHSSI_T2RDELAY 0xf80000 1114#define BCONTXHSSI 0x400 1115#define BIGFROMCCK 0x200 1116#define BAGCADDRESS 0x3f 1117#define BRXHPTX 0x7000 1118#define BRXHP2RX 0x38000 1119#define BRXHPCCKINI 0xc0000 1120#define BAGCTXCODE 0xc00000 1121#define BAGCRXCODE 0x300000 1122 1123#define B3WIREDATALENGTH 0x800 1124#define B3WIREADDREAALENGTH 0x400 1125 1126#define B3WIRERFPOWERDOWN 0x1 1127#define B5GPAPEPOLARITY 0x40000000 1128#define B2GPAPEPOLARITY 0x80000000 1129#define BRFSW_TXDEFAULTANT 0x3 1130#define BRFSW_TXOPTIONANT 0x30 1131#define BRFSW_RXDEFAULTANT 0x300 1132#define BRFSW_RXOPTIONANT 0x3000 1133#define BRFSI_3WIREDATA 0x1 1134#define BRFSI_3WIRECLOCK 0x2 1135#define BRFSI_3WIRELOAD 0x4 1136#define BRFSI_3WIRERW 0x8 1137#define BRFSI_3WIRE 0xf 1138 1139#define BRFSI_RFENV 0x10 1140 1141#define BRFSI_TRSW 0x20 1142#define BRFSI_TRSWB 0x40 1143#define BRFSI_ANTSW 0x100 1144#define BRFSI_ANTSWB 0x200 1145#define BRFSI_PAPE 0x400 1146#define BRFSI_PAPE5G 0x800 1147#define BBANDSELECT 0x1 1148#define BHTSIG2_GI 0x80 1149#define BHTSIG2_SMOOTHING 0x01 1150#define BHTSIG2_SOUNDING 0x02 1151#define BHTSIG2_AGGREATON 0x08 1152#define BHTSIG2_STBC 0x30 1153#define BHTSIG2_ADVCODING 0x40 1154#define BHTSIG2_NUMOFHTLTF 0x300 1155#define BHTSIG2_CRC8 0x3fc 1156#define BHTSIG1_MCS 0x7f 1157#define BHTSIG1_BANDWIDTH 0x80 1158#define BHTSIG1_HTLENGTH 0xffff 1159#define BLSIG_RATE 0xf 1160#define BLSIG_RESERVED 0x10 1161#define BLSIG_LENGTH 0x1fffe 1162#define BLSIG_PARITY 0x20 1163#define BCCKRXPHASE 0x4 1164 1165#define BLSSIREADADDRESS 0x7f800000 1166#define BLSSIREADEDGE 0x80000000 1167 1168#define BLSSIREADBACKDATA 0xfffff 1169 1170#define BLSSIREADOKFLAG 0x1000 1171#define BCCKSAMPLERATE 0x8 1172#define BREGULATOR0STANDBY 0x1 1173#define BREGULATORPLLSTANDBY 0x2 1174#define BREGULATOR1STANDBY 0x4 1175#define BPLLPOWERUP 0x8 1176#define BDPLLPOWERUP 0x10 1177#define BDA10POWERUP 0x20 1178#define BAD7POWERUP 0x200 1179#define BDA6POWERUP 0x2000 1180#define BXTALPOWERUP 0x4000 1181#define B40MDCLKPOWERUP 0x8000 1182#define BDA6DEBUGMODE 0x20000 1183#define BDA6SWING 0x380000 1184 1185#define BADCLKPHASE 0x4000000 1186#define B80MCLKDELAY 0x18000000 1187#define BAFEWATCHDOGENABLE 0x20000000 1188 1189#define BXTALCAP01 0xc0000000 1190#define BXTALCAP23 0x3 1191#define BXTALCAP92X 0x0f000000 1192#define BXTALCAP 0x0f000000 1193 1194#define BINTDIFCLKENABLE 0x400 1195#define BEXTSIGCLKENABLE 0x800 1196#define BBANDGAP_MBIAS_POWERUP 0x10000 1197#define BAD11SH_GAIN 0xc0000 1198#define BAD11NPUT_RANGE 0x700000 1199#define BAD110P_CURRENT 0x3800000 1200#define BLPATH_LOOPBACK 0x4000000 1201#define BQPATH_LOOPBACK 0x8000000 1202#define BAFE_LOOPBACK 0x10000000 1203#define BDA10_SWING 0x7e0 1204#define BDA10_REVERSE 0x800 1205#define BDA_CLK_SOURCE 0x1000 1206#define BDA7INPUT_RANGE 0x6000 1207#define BDA7_GAIN 0x38000 1208#define BDA7OUTPUT_CM_MODE 0x40000 1209#define BDA7INPUT_CM_MODE 0x380000 1210#define BDA7CURRENT 0xc00000 1211#define BREGULATOR_ADJUST 0x7000000 1212#define BAD11POWERUP_ATTX 0x1 1213#define BDA10PS_ATTX 0x10 1214#define BAD11POWERUP_ATRX 0x100 1215#define BDA10PS_ATRX 0x1000 1216#define BCCKRX_AGC_FORMAT 0x200 1217#define BPSDFFT_SAMPLE_POINT 0xc000 1218#define BPSD_AVERAGE_NUM 0x3000 1219#define BIQPATH_CONTROL 0xc00 1220#define BPSD_FREQ 0x3ff 1221#define BPSD_ANTENNA_PATH 0x30 1222#define BPSD_IQ_SWITCH 0x40 1223#define BPSD_RX_TRIGGER 0x400000 1224#define BPSD_TX_TRIGGER 0x80000000 1225#define BPSD_SINE_TONE_SCALE 0x7f000000 1226#define BPSD_REPORT 0xffff 1227 1228#define BOFDM_TXSC 0x30000000 1229#define BCCK_TXON 0x1 1230#define BOFDM_TXON 0x2 1231#define BDEBUG_PAGE 0xfff 1232#define BDEBUG_ITEM 0xff 1233#define BANTL 0x10 1234#define BANT_NONHT 0x100 1235#define BANT_HT1 0x1000 1236#define BANT_HT2 0x10000 1237#define BANT_HT1S1 0x100000 1238#define BANT_NONHTS1 0x1000000 1239 1240#define BCCK_BBMODE 0x3 1241#define BCCK_TXPOWERSAVING 0x80 1242#define BCCK_RXPOWERSAVING 0x40 1243 1244#define BCCK_SIDEBAND 0x10 1245 1246#define BCCK_SCRAMBLE 0x8 1247#define BCCK_ANTDIVERSITY 0x8000 1248#define BCCK_CARRIER_RECOVERY 0x4000 1249#define BCCK_TXRATE 0x3000 1250#define BCCK_DCCANCEL 0x0800 1251#define BCCK_ISICANCEL 0x0400 1252#define BCCK_MATCH_FILTER 0x0200 1253#define BCCK_EQUALIZER 0x0100 1254#define BCCK_PREAMBLE_DETECT 0x800000 1255#define BCCK_FAST_FALSECCA 0x400000 1256#define BCCK_CH_ESTSTART 0x300000 1257#define BCCK_CCA_COUNT 0x080000 1258#define BCCK_CS_LIM 0x070000 1259#define BCCK_BIST_MODE 0x80000000 1260#define BCCK_CCAMASK 0x40000000 1261#define BCCK_TX_DAC_PHASE 0x4 1262#define BCCK_RX_ADC_PHASE 0x20000000 1263#define BCCKR_CP_MODE 0x0100 1264#define BCCK_TXDC_OFFSET 0xf0 1265#define BCCK_RXDC_OFFSET 0xf 1266#define BCCK_CCA_MODE 0xc000 1267#define BCCK_FALSECS_LIM 0x3f00 1268#define BCCK_CS_RATIO 0xc00000 1269#define BCCK_CORGBIT_SEL 0x300000 1270#define BCCK_PD_LIM 0x0f0000 1271#define BCCK_NEWCCA 0x80000000 1272#define BCCK_RXHP_OF_IG 0x8000 1273#define BCCK_RXIG 0x7f00 1274#define BCCK_LNA_POLARITY 0x800000 1275#define BCCK_RX1ST_BAIN 0x7f0000 1276#define BCCK_RF_EXTEND 0x20000000 1277#define BCCK_RXAGC_SATLEVEL 0x1f000000 1278#define BCCK_RXAGC_SATCOUNT 0xe0 1279#define BCCK_RX_RF_SETTLE 0x1f 1280#define BCCK_FIXED_RXAGC 0x8000 1281#define BCCK_ANTENNA_POLARITY 0x2000 1282#define BCCK_TXFILTER_TYPE 0x0c00 1283#define BCCK_RXAGC_REPORTTYPE 0x0300 1284#define BCCK_RXDAGC_EN 0x80000000 1285#define BCCK_RXDAGC_PERIOD 0x20000000 1286#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1287#define BCCK_TIMING_RECOVERY 0x800000 1288#define BCCK_TXC0 0x3f0000 1289#define BCCK_TXC1 0x3f000000 1290#define BCCK_TXC2 0x3f 1291#define BCCK_TXC3 0x3f00 1292#define BCCK_TXC4 0x3f0000 1293#define BCCK_TXC5 0x3f000000 1294#define BCCK_TXC6 0x3f 1295#define BCCK_TXC7 0x3f00 1296#define BCCK_DEBUGPORT 0xff0000 1297#define BCCK_DAC_DEBUG 0x0f000000 1298#define BCCK_FALSEALARM_ENABLE 0x8000 1299#define BCCK_FALSEALARM_READ 0x4000 1300#define BCCK_TRSSI 0x7f 1301#define BCCK_RXAGC_REPORT 0xfe 1302#define BCCK_RXREPORT_ANTSEL 0x80000000 1303#define BCCK_RXREPORT_MFOFF 0x40000000 1304#define BCCK_RXREPORT_SQLOSS 0x20000000 1305#define BCCK_RXREPORT_PKTLOSS 0x10000000 1306#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1307#define BCCK_RXREPORT_RATEERROR 0x04000000 1308#define BCCK_RXREPORT_RXRATE 0x03000000 1309#define BCCK_RXFA_COUNTER_LOWER 0xff 1310#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1311#define BCCK_RXHPAGC_START 0xe000 1312#define BCCK_RXHPAGC_FINAL 0x1c00 1313#define BCCK_RXFALSEALARM_ENABLE 0x8000 1314#define BCCK_FACOUNTER_FREEZE 0x4000 1315#define BCCK_TXPATH_SEL 0x10000000 1316#define BCCK_DEFAULT_RXPATH 0xc000000 1317#define BCCK_OPTION_RXPATH 0x3000000 1318 1319#define BNUM_OFSTF 0x3 1320#define BSHIFT_L 0xc0 1321#define BGI_TH 0xc 1322#define BRXPATH_A 0x1 1323#define BRXPATH_B 0x2 1324#define BRXPATH_C 0x4 1325#define BRXPATH_D 0x8 1326#define BTXPATH_A 0x1 1327#define BTXPATH_B 0x2 1328#define BTXPATH_C 0x4 1329#define BTXPATH_D 0x8 1330#define BTRSSI_FREQ 0x200 1331#define BADC_BACKOFF 0x3000 1332#define BDFIR_BACKOFF 0xc000 1333#define BTRSSI_LATCH_PHASE 0x10000 1334#define BRX_LDC_OFFSET 0xff 1335#define BRX_QDC_OFFSET 0xff00 1336#define BRX_DFIR_MODE 0x1800000 1337#define BRX_DCNF_TYPE 0xe000000 1338#define BRXIQIMB_A 0x3ff 1339#define BRXIQIMB_B 0xfc00 1340#define BRXIQIMB_C 0x3f0000 1341#define BRXIQIMB_D 0xffc00000 1342#define BDC_DC_NOTCH 0x60000 1343#define BRXNB_NOTCH 0x1f000000 1344#define BPD_TH 0xf 1345#define BPD_TH_OPT2 0xc000 1346#define BPWED_TH 0x700 1347#define BIFMF_WIN_L 0x800 1348#define BPD_OPTION 0x1000 1349#define BMF_WIN_L 0xe000 1350#define BBW_SEARCH_L 0x30000 1351#define BWIN_ENH_L 0xc0000 1352#define BBW_TH 0x700000 1353#define BED_TH2 0x3800000 1354#define BBW_OPTION 0x4000000 1355#define BRADIO_TH 0x18000000 1356#define BWINDOW_L 0xe0000000 1357#define BSBD_OPTION 0x1 1358#define BFRAME_TH 0x1c 1359#define BFS_OPTION 0x60 1360#define BDC_SLOPE_CHECK 0x80 1361#define BFGUARD_COUNTER_DC_L 0xe00 1362#define BFRAME_WEIGHT_SHORT 0x7000 1363#define BSUB_TUNE 0xe00000 1364#define BFRAME_DC_LENGTH 0xe000000 1365#define BSBD_START_OFFSET 0x30000000 1366#define BFRAME_TH_2 0x7 1367#define BFRAME_GI2_TH 0x38 1368#define BGI2_SYNC_EN 0x40 1369#define BSARCH_SHORT_EARLY 0x300 1370#define BSARCH_SHORT_LATE 0xc00 1371#define BSARCH_GI2_LATE 0x70000 1372#define BCFOANTSUM 0x1 1373#define BCFOACC 0x2 1374#define BCFOSTARTOFFSET 0xc 1375#define BCFOLOOPBACK 0x70 1376#define BCFOSUMWEIGHT 0x80 1377#define BDAGCENABLE 0x10000 1378#define BTXIQIMB_A 0x3ff 1379#define BTXIQIMB_b 0xfc00 1380#define BTXIQIMB_C 0x3f0000 1381#define BTXIQIMB_D 0xffc00000 1382#define BTXIDCOFFSET 0xff 1383#define BTXIQDCOFFSET 0xff00 1384#define BTXDFIRMODE 0x10000 1385#define BTXPESUDO_NOISEON 0x4000000 1386#define BTXPESUDO_NOISE_A 0xff 1387#define BTXPESUDO_NOISE_B 0xff00 1388#define BTXPESUDO_NOISE_C 0xff0000 1389#define BTXPESUDO_NOISE_D 0xff000000 1390#define BCCA_DROPOPTION 0x20000 1391#define BCCA_DROPTHRES 0xfff00000 1392#define BEDCCA_H 0xf 1393#define BEDCCA_L 0xf0 1394#define BLAMBDA_ED 0x300 1395#define BRX_INITIALGAIN 0x7f 1396#define BRX_ANTDIV_EN 0x80 1397#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1398#define BRX_HIGHPOWER_FLOW 0x8000 1399#define BRX_AGC_FREEZE_THRES 0xc0000 1400#define BRX_FREEZESTEP_AGC1 0x300000 1401#define BRX_FREEZESTEP_AGC2 0xc00000 1402#define BRX_FREEZESTEP_AGC3 0x3000000 1403#define BRX_FREEZESTEP_AGC0 0xc000000 1404#define BRXRSSI_CMP_EN 0x10000000 1405#define BRXQUICK_AGCEN 0x20000000 1406#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1407#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1408#define BRX_AGCSHIFT 0x7f 1409#define BTRSW_TRI_ONLY 0x80 1410#define BPOWER_THRES 0x300 1411#define BRXAGC_EN 0x1 1412#define BRXAGC_TOGETHER_EN 0x2 1413#define BRXAGC_MIN 0x4 1414#define BRXHP_INI 0x7 1415#define BRXHP_TRLNA 0x70 1416#define BRXHP_RSSI 0x700 1417#define BRXHP_BBP1 0x7000 1418#define BRXHP_BBP2 0x70000 1419#define BRXHP_BBP3 0x700000 1420#define BRSSI_H 0x7f0000 1421#define BRSSI_GEN 0x7f000000 1422#define BRXSETTLE_TRSW 0x7 1423#define BRXSETTLE_LNA 0x38 1424#define BRXSETTLE_RSSI 0x1c0 1425#define BRXSETTLE_BBP 0xe00 1426#define BRXSETTLE_RXHP 0x7000 1427#define BRXSETTLE_ANTSW_RSSI 0x38000 1428#define BRXSETTLE_ANTSW 0xc0000 1429#define BRXPROCESS_TIME_DAGC 0x300000 1430#define BRXSETTLE_HSSI 0x400000 1431#define BRXPROCESS_TIME_BBPPW 0x800000 1432#define BRXANTENNA_POWER_SHIFT 0x3000000 1433#define BRSSI_TABLE_SELECT 0xc000000 1434#define BRXHP_FINAL 0x7000000 1435#define BRXHPSETTLE_BBP 0x7 1436#define BRXHTSETTLE_HSSI 0x8 1437#define BRXHTSETTLE_RXHP 0x70 1438#define BRXHTSETTLE_BBPPW 0x80 1439#define BRXHTSETTLE_IDLE 0x300 1440#define BRXHTSETTLE_RESERVED 0x1c00 1441#define BRXHT_RXHP_EN 0x8000 1442#define BRXAGC_FREEZE_THRES 0x30000 1443#define BRXAGC_TOGETHEREN 0x40000 1444#define BRXHTAGC_MIN 0x80000 1445#define BRXHTAGC_EN 0x100000 1446#define BRXHTDAGC_EN 0x200000 1447#define BRXHT_RXHP_BBP 0x1c00000 1448#define BRXHT_RXHP_FINAL 0xe0000000 1449#define BRXPW_RADIO_TH 0x3 1450#define BRXPW_RADIO_EN 0x4 1451#define BRXMF_HOLD 0x3800 1452#define BRXPD_DELAY_TH1 0x38 1453#define BRXPD_DELAY_TH2 0x1c0 1454#define BRXPD_DC_COUNT_MAX 0x600 1455#define BRXPD_DELAY_TH 0x8000 1456#define BRXPROCESS_DELAY 0xf0000 1457#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1458#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1459#define BRXSGI_GUARD_L 0xc000000 1460#define BRXSGI_SEARCH_L 0x30000000 1461#define BRXSGI_TH 0xc0000000 1462#define BDFSCNT0 0xff 1463#define BDFSCNT1 0xff00 1464#define BDFSFLAG 0xf0000 1465#define BMF_WEIGHT_SUM 0x300000 1466#define BMINIDX_TH 0x7f000000 1467#define BDAFORMAT 0x40000 1468#define BTXCH_EMU_ENABLE 0x01000000 1469#define BTRSW_ISOLATION_A 0x7f 1470#define BTRSW_ISOLATION_B 0x7f00 1471#define BTRSW_ISOLATION_C 0x7f0000 1472#define BTRSW_ISOLATION_D 0x7f000000 1473#define BEXT_LNA_GAIN 0x7c00 1474 1475#define BSTBC_EN 0x4 1476#define BANTENNA_MAPPING 0x10 1477#define BNSS 0x20 1478#define BCFO_ANTSUM_ID 0x200 1479#define BPHY_COUNTER_RESET 0x8000000 1480#define BCFO_REPORT_GET 0x4000000 1481#define BOFDM_CONTINUE_TX 0x10000000 1482#define BOFDM_SINGLE_CARRIER 0x20000000 1483#define BOFDM_SINGLE_TONE 0x40000000 1484#define BHT_DETECT 0x100 1485#define BCFOEN 0x10000 1486#define BCFOVALUE 0xfff00000 1487#define BSIGTONE_RE 0x3f 1488#define BSIGTONE_IM 0x7f00 1489#define BCOUNTER_CCA 0xffff 1490#define BCOUNTER_PARITYFAIL 0xffff0000 1491#define BCOUNTER_RATEILLEGAL 0xffff 1492#define BCOUNTER_CRC8FAIL 0xffff0000 1493#define BCOUNTER_MCSNOSUPPORT 0xffff 1494#define BCOUNTER_FASTSYNC 0xffff 1495#define BSHORTCFO 0xfff 1496#define BSHORTCFOT_LENGTH 12 1497#define BSHORTCFOF_LENGTH 11 1498#define BLONGCFO 0x7ff 1499#define BLONGCFOT_LENGTH 11 1500#define BLONGCFOF_LENGTH 11 1501#define BTAILCFO 0x1fff 1502#define BTAILCFOT_LENGTH 13 1503#define BTAILCFOF_LENGTH 12 1504#define BNOISE_EN_PWDB 0xffff 1505#define BCC_POWER_DB 0xffff0000 1506#define BMOISE_PWDB 0xffff 1507#define BPOWERMEAST_LENGTH 10 1508#define BPOWERMEASF_LENGTH 3 1509#define BRX_HT_BW 0x1 1510#define BRXSC 0x6 1511#define BRX_HT 0x8 1512#define BNB_INTF_DET_ON 0x1 1513#define BINTF_WIN_LEN_CFG 0x30 1514#define BNB_INTF_TH_CFG 0x1c0 1515#define BRFGAIN 0x3f 1516#define BTABLESEL 0x40 1517#define BTRSW 0x80 1518#define BRXSNR_A 0xff 1519#define BRXSNR_B 0xff00 1520#define BRXSNR_C 0xff0000 1521#define BRXSNR_D 0xff000000 1522#define BSNR_EVMT_LENGTH 8 1523#define BSNR_EVMF_LENGTH 1 1524#define BCSI1ST 0xff 1525#define BCSI2ND 0xff00 1526#define BRXEVM1ST 0xff0000 1527#define BRXEVM2ND 0xff000000 1528#define BSIGEVM 0xff 1529#define BPWDB 0xff00 1530#define BSGIEN 0x10000 1531 1532#define BSFACTOR_QMA1 0xf 1533#define BSFACTOR_QMA2 0xf0 1534#define BSFACTOR_QMA3 0xf00 1535#define BSFACTOR_QMA4 0xf000 1536#define BSFACTOR_QMA5 0xf0000 1537#define BSFACTOR_QMA6 0xf0000 1538#define BSFACTOR_QMA7 0xf00000 1539#define BSFACTOR_QMA8 0xf000000 1540#define BSFACTOR_QMA9 0xf0000000 1541#define BCSI_SCHEME 0x100000 1542 1543#define BNOISE_LVL_TOP_SET 0x3 1544#define BCHSMOOTH 0x4 1545#define BCHSMOOTH_CFG1 0x38 1546#define BCHSMOOTH_CFG2 0x1c0 1547#define BCHSMOOTH_CFG3 0xe00 1548#define BCHSMOOTH_CFG4 0x7000 1549#define BMRCMODE 0x800000 1550#define BTHEVMCFG 0x7000000 1551 1552#define BLOOP_FIT_TYPE 0x1 1553#define BUPD_CFO 0x40 1554#define BUPD_CFO_OFFDATA 0x80 1555#define BADV_UPD_CFO 0x100 1556#define BADV_TIME_CTRL 0x800 1557#define BUPD_CLKO 0x1000 1558#define BFC 0x6000 1559#define BTRACKING_MODE 0x8000 1560#define BPHCMP_ENABLE 0x10000 1561#define BUPD_CLKO_LTF 0x20000 1562#define BCOM_CH_CFO 0x40000 1563#define BCSI_ESTI_MODE 0x80000 1564#define BADV_UPD_EQZ 0x100000 1565#define BUCHCFG 0x7000000 1566#define BUPDEQZ 0x8000000 1567 1568#define BRX_PESUDO_NOISE_ON 0x20000000 1569#define BRX_PESUDO_NOISE_A 0xff 1570#define BRX_PESUDO_NOISE_B 0xff00 1571#define BRX_PESUDO_NOISE_C 0xff0000 1572#define BRX_PESUDO_NOISE_D 0xff000000 1573#define BRX_PESUDO_NOISESTATE_A 0xffff 1574#define BRX_PESUDO_NOISESTATE_B 0xffff0000 1575#define BRX_PESUDO_NOISESTATE_C 0xffff 1576#define BRX_PESUDO_NOISESTATE_D 0xffff0000 1577 1578#define BZEBRA1_HSSIENABLE 0x8 1579#define BZEBRA1_TRXCONTROL 0xc00 1580#define BZEBRA1_TRXGAINSETTING 0x07f 1581#define BZEBRA1_RXCOUNTER 0xc00 1582#define BZEBRA1_TXCHANGEPUMP 0x38 1583#define BZEBRA1_RXCHANGEPUMP 0x7 1584#define BZEBRA1_CHANNEL_NUM 0xf80 1585#define BZEBRA1_TXLPFBW 0x400 1586#define BZEBRA1_RXLPFBW 0x600 1587 1588#define BRTL8256REG_MODE_CTRL1 0x100 1589#define BRTL8256REG_MODE_CTRL0 0x40 1590#define BRTL8256REG_TXLPFBW 0x18 1591#define BRTL8256REG_RXLPFBW 0x600 1592 1593#define BRTL8258_TXLPFBW 0xc 1594#define BRTL8258_RXLPFBW 0xc00 1595#define BRTL8258_RSSILPFBW 0xc0 1596 1597#define BBYTE0 0x1 1598#define BBYTE1 0x2 1599#define BBYTE2 0x4 1600#define BBYTE3 0x8 1601#define BWORD0 0x3 1602#define BWORD1 0xc 1603#define BWORD 0xf 1604 1605#define MASKBYTE0 0xff 1606#define MASKBYTE1 0xff00 1607#define MASKBYTE2 0xff0000 1608#define MASKBYTE3 0xff000000 1609#define MASKHWORD 0xffff0000 1610#define MASKLWORD 0x0000ffff 1611#define MASKDWORD 0xffffffff 1612#define MASK12BITS 0xfff 1613#define MASKH4BITS 0xf0000000 1614#define MASKOFDM_D 0xffc00000 1615#define MASKCCK 0x3f3f3f3f 1616 1617#define MASK4BITS 0x0f 1618#define MASK20BITS 0xfffff 1619#define RFREG_OFFSET_MASK 0xfffff 1620 1621#define BMASKBYTE0 0xff 1622#define BMASKBYTE1 0xff00 1623#define BMASKBYTE2 0xff0000 1624#define BMASKBYTE3 0xff000000 1625#define BMASKHWORD 0xffff0000 1626#define BMASKLWORD 0x0000ffff 1627#define BMASKDWORD 0xffffffff 1628#define BMASK12BITS 0xfff 1629#define BMASKH4BITS 0xf0000000 1630#define BMASKOFDM_D 0xffc00000 1631#define BMASKCCK 0x3f3f3f3f 1632 1633#define BRFREGOFFSETMASK 0xfffff 1634 1635/* WOL bit information */ 1636#define WOL_REASON_PTK_UPDATE BIT(0) 1637#define WOL_REASON_GTK_UPDATE BIT(1) 1638#define WOL_REASON_DISASSOC BIT(2) 1639#define WOL_REASON_DEAUTH BIT(3) 1640#define WOL_REASON_FW_DISCONNECT BIT(4) 1641 1642#endif 1643