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13#ifndef _TB_REGS
14#define _TB_REGS
15
16#include <linux/types.h>
17
18
19#define TB_ROUTE_SHIFT 8
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25
26#define TB_MAX_CONFIG_RW_LENGTH 60
27
28enum tb_switch_cap {
29 TB_SWITCH_CAP_VSE = 0x05,
30};
31
32enum tb_switch_vse_cap {
33 TB_VSE_CAP_PLUG_EVENTS = 0x01,
34 TB_VSE_CAP_TIME2 = 0x03,
35 TB_VSE_CAP_IECS = 0x04,
36 TB_VSE_CAP_LINK_CONTROLLER = 0x06,
37};
38
39enum tb_port_cap {
40 TB_PORT_CAP_PHY = 0x01,
41 TB_PORT_CAP_TIME1 = 0x03,
42 TB_PORT_CAP_ADAP = 0x04,
43 TB_PORT_CAP_VSE = 0x05,
44};
45
46enum tb_port_state {
47 TB_PORT_DISABLED = 0,
48 TB_PORT_CONNECTING = 1,
49 TB_PORT_UP = 2,
50 TB_PORT_UNPLUGGED = 7,
51};
52
53
54
55struct tb_cap_basic {
56 u8 next;
57
58 u8 cap;
59} __packed;
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68
69struct tb_cap_extended_short {
70 u8 next;
71 u8 cap;
72 u8 vsec_id;
73 u8 length;
74} __packed;
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84
85struct tb_cap_extended_long {
86 u8 zero1;
87 u8 cap;
88 u8 vsec_id;
89 u8 zero2;
90 u16 next;
91 u16 length;
92} __packed;
93
94
95
96struct tb_cap_link_controller {
97 struct tb_cap_extended_long cap_header;
98 u32 count:4;
99 u32 unknown1:4;
100 u32 base_offset:8;
101
102
103
104 u32 length:12;
105 u32 unknown2:4;
106} __packed;
107
108struct tb_cap_phy {
109 struct tb_cap_basic cap_header;
110 u32 unknown1:16;
111 u32 unknown2:14;
112 bool disable:1;
113 u32 unknown3:11;
114 enum tb_port_state state:4;
115 u32 unknown4:2;
116} __packed;
117
118struct tb_eeprom_ctl {
119 bool clock:1;
120 bool access_low:1;
121 bool data_out:1;
122 bool data_in:1;
123 bool access_high:1;
124 bool not_present:1;
125 bool unknown1:1;
126 bool present:1;
127 u32 unknown2:24;
128} __packed;
129
130struct tb_cap_plug_events {
131 struct tb_cap_extended_short cap_header;
132 u32 __unknown1:2;
133 u32 plug_events:5;
134 u32 __unknown2:25;
135 u32 __unknown3;
136 u32 __unknown4;
137 struct tb_eeprom_ctl eeprom_ctl;
138 u32 __unknown5[7];
139 u32 drom_offset;
140} __packed;
141
142
143
144
145struct tb_regs_switch_header {
146
147 u16 vendor_id;
148 u16 device_id;
149
150 u32 first_cap_offset:8;
151 u32 upstream_port_number:6;
152 u32 max_port_number:6;
153 u32 depth:3;
154 u32 __unknown1:1;
155 u32 revision:8;
156
157 u32 route_lo;
158
159 u32 route_hi:31;
160 bool enabled:1;
161
162 u32 plug_events_delay:8;
163
164
165
166
167 u32 __unknown4:16;
168 u32 thunderbolt_version:8;
169} __packed;
170
171enum tb_port_type {
172 TB_TYPE_INACTIVE = 0x000000,
173 TB_TYPE_PORT = 0x000001,
174 TB_TYPE_NHI = 0x000002,
175
176
177 TB_TYPE_DP_HDMI_IN = 0x0e0101,
178 TB_TYPE_DP_HDMI_OUT = 0x0e0102,
179 TB_TYPE_PCIE_DOWN = 0x100101,
180 TB_TYPE_PCIE_UP = 0x100102,
181
182};
183
184
185struct tb_regs_port_header {
186
187 u16 vendor_id;
188 u16 device_id;
189
190 u32 first_cap_offset:8;
191 u32 max_counters:11;
192 u32 __unknown1:5;
193 u32 revision:8;
194
195 enum tb_port_type type:24;
196 u32 thunderbolt_version:8;
197
198 u32 __unknown2:20;
199 u32 port_number:6;
200 u32 __unknown3:6;
201
202 u32 nfc_credits;
203
204 u32 max_in_hop_id:11;
205 u32 max_out_hop_id:11;
206 u32 __unknown4:10;
207
208 u32 __unknown5;
209
210 u32 __unknown6;
211
212} __packed;
213
214
215struct tb_regs_hop {
216
217 u32 next_hop:11;
218
219
220
221 u32 out_port:6;
222 u32 initial_credits:8;
223 u32 unknown1:6;
224 bool enable:1;
225
226
227 u32 weight:4;
228 u32 unknown2:4;
229 u32 priority:3;
230 bool drop_packages:1;
231 u32 counter:11;
232 bool counter_enable:1;
233 bool ingress_fc:1;
234 bool egress_fc:1;
235 bool ingress_shared_buffer:1;
236 bool egress_shared_buffer:1;
237 u32 unknown3:4;
238} __packed;
239
240
241#endif
242