1
2
3
4
5
6
7
8
9
10
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/gpio/driver.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/regmap.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/spi/spi.h>
26#include <linux/uaccess.h>
27
28#define MAX310X_NAME "max310x"
29#define MAX310X_MAJOR 204
30#define MAX310X_MINOR 209
31#define MAX310X_UART_NRMAX 16
32
33
34#define MAX310X_RHR_REG (0x00)
35#define MAX310X_THR_REG (0x00)
36#define MAX310X_IRQEN_REG (0x01)
37#define MAX310X_IRQSTS_REG (0x02)
38#define MAX310X_LSR_IRQEN_REG (0x03)
39#define MAX310X_LSR_IRQSTS_REG (0x04)
40#define MAX310X_REG_05 (0x05)
41#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05
42#define MAX310X_SPCHR_IRQSTS_REG (0x06)
43#define MAX310X_STS_IRQEN_REG (0x07)
44#define MAX310X_STS_IRQSTS_REG (0x08)
45#define MAX310X_MODE1_REG (0x09)
46#define MAX310X_MODE2_REG (0x0a)
47#define MAX310X_LCR_REG (0x0b)
48#define MAX310X_RXTO_REG (0x0c)
49#define MAX310X_HDPIXDELAY_REG (0x0d)
50#define MAX310X_IRDA_REG (0x0e)
51#define MAX310X_FLOWLVL_REG (0x0f)
52#define MAX310X_FIFOTRIGLVL_REG (0x10)
53#define MAX310X_TXFIFOLVL_REG (0x11)
54#define MAX310X_RXFIFOLVL_REG (0x12)
55#define MAX310X_FLOWCTRL_REG (0x13)
56#define MAX310X_XON1_REG (0x14)
57#define MAX310X_XON2_REG (0x15)
58#define MAX310X_XOFF1_REG (0x16)
59#define MAX310X_XOFF2_REG (0x17)
60#define MAX310X_GPIOCFG_REG (0x18)
61#define MAX310X_GPIODATA_REG (0x19)
62#define MAX310X_PLLCFG_REG (0x1a)
63#define MAX310X_BRGCFG_REG (0x1b)
64#define MAX310X_BRGDIVLSB_REG (0x1c)
65#define MAX310X_BRGDIVMSB_REG (0x1d)
66#define MAX310X_CLKSRC_REG (0x1e)
67#define MAX310X_REG_1F (0x1f)
68
69#define MAX310X_REVID_REG MAX310X_REG_1F
70
71#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F
72#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F
73
74
75#define MAX310X_REVID_EXTREG MAX310X_REG_05
76
77
78#define MAX310X_IRQ_LSR_BIT (1 << 0)
79#define MAX310X_IRQ_SPCHR_BIT (1 << 1)
80#define MAX310X_IRQ_STS_BIT (1 << 2)
81#define MAX310X_IRQ_RXFIFO_BIT (1 << 3)
82#define MAX310X_IRQ_TXFIFO_BIT (1 << 4)
83#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5)
84#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6)
85#define MAX310X_IRQ_CTS_BIT (1 << 7)
86
87
88#define MAX310X_LSR_RXTO_BIT (1 << 0)
89#define MAX310X_LSR_RXOVR_BIT (1 << 1)
90#define MAX310X_LSR_RXPAR_BIT (1 << 2)
91#define MAX310X_LSR_FRERR_BIT (1 << 3)
92#define MAX310X_LSR_RXBRK_BIT (1 << 4)
93#define MAX310X_LSR_RXNOISE_BIT (1 << 5)
94#define MAX310X_LSR_CTS_BIT (1 << 7)
95
96
97#define MAX310X_SPCHR_XON1_BIT (1 << 0)
98#define MAX310X_SPCHR_XON2_BIT (1 << 1)
99#define MAX310X_SPCHR_XOFF1_BIT (1 << 2)
100#define MAX310X_SPCHR_XOFF2_BIT (1 << 3)
101#define MAX310X_SPCHR_BREAK_BIT (1 << 4)
102#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5)
103
104
105#define MAX310X_STS_GPIO0_BIT (1 << 0)
106#define MAX310X_STS_GPIO1_BIT (1 << 1)
107#define MAX310X_STS_GPIO2_BIT (1 << 2)
108#define MAX310X_STS_GPIO3_BIT (1 << 3)
109#define MAX310X_STS_CLKREADY_BIT (1 << 5)
110#define MAX310X_STS_SLEEP_BIT (1 << 6)
111
112
113#define MAX310X_MODE1_RXDIS_BIT (1 << 0)
114#define MAX310X_MODE1_TXDIS_BIT (1 << 1)
115#define MAX310X_MODE1_TXHIZ_BIT (1 << 2)
116#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3)
117#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4)
118#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5)
119#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6)
120#define MAX310X_MODE1_IRQSEL_BIT (1 << 7)
121
122
123#define MAX310X_MODE2_RST_BIT (1 << 0)
124#define MAX310X_MODE2_FIFORST_BIT (1 << 1)
125#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2)
126#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3)
127#define MAX310X_MODE2_SPCHR_BIT (1 << 4)
128#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5)
129#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6)
130#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7)
131
132
133#define MAX310X_LCR_LENGTH0_BIT (1 << 0)
134#define MAX310X_LCR_LENGTH1_BIT (1 << 1)
135
136
137
138
139
140
141
142#define MAX310X_LCR_STOPLEN_BIT (1 << 2)
143
144
145
146
147
148
149
150#define MAX310X_LCR_PARITY_BIT (1 << 3)
151#define MAX310X_LCR_EVENPARITY_BIT (1 << 4)
152#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5)
153#define MAX310X_LCR_TXBREAK_BIT (1 << 6)
154#define MAX310X_LCR_RTS_BIT (1 << 7)
155
156
157#define MAX310X_IRDA_IRDAEN_BIT (1 << 0)
158#define MAX310X_IRDA_SIR_BIT (1 << 1)
159
160
161#define MAX310X_FLOWLVL_HALT_MASK (0x000f)
162#define MAX310X_FLOWLVL_RES_MASK (0x00f0)
163#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
165
166
167#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f)
168#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0)
169#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
171
172
173#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0)
174#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1)
175#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2)
176
177
178
179#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3)
180#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4)
181#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5)
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6)
200#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7)
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215#define MAX310X_PLLCFG_PREDIV_MASK (0x3f)
216#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0)
217
218
219#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4)
220#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5)
221
222
223#define MAX310X_CLKSRC_CRYST_BIT (1 << 1)
224#define MAX310X_CLKSRC_PLL_BIT (1 << 2)
225#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3)
226#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4)
227#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7)
228
229
230#define MAX310X_EXTREG_ENBL (0xce)
231#define MAX310X_EXTREG_DSBL (0xcd)
232
233
234#define MAX310X_FIFO_SIZE (128)
235#define MAX310x_REV_MASK (0xf8)
236#define MAX310X_WRITE_BIT 0x80
237
238
239#define MAX3107_REV_ID (0xa0)
240
241
242#define MAX3109_REV_ID (0xc0)
243
244
245#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6)
246#define MAX14830_REV_ID (0xb0)
247
248struct max310x_devtype {
249 char name[9];
250 int nr;
251 int (*detect)(struct device *);
252 void (*power)(struct uart_port *, int);
253};
254
255struct max310x_one {
256 struct uart_port port;
257 struct work_struct tx_work;
258 struct work_struct md_work;
259 struct work_struct rs_work;
260};
261
262struct max310x_port {
263 struct max310x_devtype *devtype;
264 struct regmap *regmap;
265 struct mutex mutex;
266 struct clk *clk;
267#ifdef CONFIG_GPIOLIB
268 struct gpio_chip gpio;
269#endif
270 struct max310x_one p[0];
271};
272
273static struct uart_driver max310x_uart = {
274 .owner = THIS_MODULE,
275 .driver_name = MAX310X_NAME,
276 .dev_name = "ttyMAX",
277 .major = MAX310X_MAJOR,
278 .minor = MAX310X_MINOR,
279 .nr = MAX310X_UART_NRMAX,
280};
281
282static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
283
284static u8 max310x_port_read(struct uart_port *port, u8 reg)
285{
286 struct max310x_port *s = dev_get_drvdata(port->dev);
287 unsigned int val = 0;
288
289 regmap_read(s->regmap, port->iobase + reg, &val);
290
291 return val;
292}
293
294static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
295{
296 struct max310x_port *s = dev_get_drvdata(port->dev);
297
298 regmap_write(s->regmap, port->iobase + reg, val);
299}
300
301static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
302{
303 struct max310x_port *s = dev_get_drvdata(port->dev);
304
305 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
306}
307
308static int max3107_detect(struct device *dev)
309{
310 struct max310x_port *s = dev_get_drvdata(dev);
311 unsigned int val = 0;
312 int ret;
313
314 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
315 if (ret)
316 return ret;
317
318 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
319 dev_err(dev,
320 "%s ID 0x%02x does not match\n", s->devtype->name, val);
321 return -ENODEV;
322 }
323
324 return 0;
325}
326
327static int max3108_detect(struct device *dev)
328{
329 struct max310x_port *s = dev_get_drvdata(dev);
330 unsigned int val = 0;
331 int ret;
332
333
334
335
336 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
337 if (ret)
338 return ret;
339
340 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
341 dev_err(dev, "%s not present\n", s->devtype->name);
342 return -ENODEV;
343 }
344
345 return 0;
346}
347
348static int max3109_detect(struct device *dev)
349{
350 struct max310x_port *s = dev_get_drvdata(dev);
351 unsigned int val = 0;
352 int ret;
353
354 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
355 MAX310X_EXTREG_ENBL);
356 if (ret)
357 return ret;
358
359 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
360 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
361 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
362 dev_err(dev,
363 "%s ID 0x%02x does not match\n", s->devtype->name, val);
364 return -ENODEV;
365 }
366
367 return 0;
368}
369
370static void max310x_power(struct uart_port *port, int on)
371{
372 max310x_port_update(port, MAX310X_MODE1_REG,
373 MAX310X_MODE1_FORCESLEEP_BIT,
374 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
375 if (on)
376 msleep(50);
377}
378
379static int max14830_detect(struct device *dev)
380{
381 struct max310x_port *s = dev_get_drvdata(dev);
382 unsigned int val = 0;
383 int ret;
384
385 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
386 MAX310X_EXTREG_ENBL);
387 if (ret)
388 return ret;
389
390 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
391 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
392 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
393 dev_err(dev,
394 "%s ID 0x%02x does not match\n", s->devtype->name, val);
395 return -ENODEV;
396 }
397
398 return 0;
399}
400
401static void max14830_power(struct uart_port *port, int on)
402{
403 max310x_port_update(port, MAX310X_BRGCFG_REG,
404 MAX14830_BRGCFG_CLKDIS_BIT,
405 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
406 if (on)
407 msleep(50);
408}
409
410static const struct max310x_devtype max3107_devtype = {
411 .name = "MAX3107",
412 .nr = 1,
413 .detect = max3107_detect,
414 .power = max310x_power,
415};
416
417static const struct max310x_devtype max3108_devtype = {
418 .name = "MAX3108",
419 .nr = 1,
420 .detect = max3108_detect,
421 .power = max310x_power,
422};
423
424static const struct max310x_devtype max3109_devtype = {
425 .name = "MAX3109",
426 .nr = 2,
427 .detect = max3109_detect,
428 .power = max310x_power,
429};
430
431static const struct max310x_devtype max14830_devtype = {
432 .name = "MAX14830",
433 .nr = 4,
434 .detect = max14830_detect,
435 .power = max14830_power,
436};
437
438static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
439{
440 switch (reg & 0x1f) {
441 case MAX310X_IRQSTS_REG:
442 case MAX310X_LSR_IRQSTS_REG:
443 case MAX310X_SPCHR_IRQSTS_REG:
444 case MAX310X_STS_IRQSTS_REG:
445 case MAX310X_TXFIFOLVL_REG:
446 case MAX310X_RXFIFOLVL_REG:
447 return false;
448 default:
449 break;
450 }
451
452 return true;
453}
454
455static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
456{
457 switch (reg & 0x1f) {
458 case MAX310X_RHR_REG:
459 case MAX310X_IRQSTS_REG:
460 case MAX310X_LSR_IRQSTS_REG:
461 case MAX310X_SPCHR_IRQSTS_REG:
462 case MAX310X_STS_IRQSTS_REG:
463 case MAX310X_TXFIFOLVL_REG:
464 case MAX310X_RXFIFOLVL_REG:
465 case MAX310X_GPIODATA_REG:
466 case MAX310X_BRGDIVLSB_REG:
467 case MAX310X_REG_05:
468 case MAX310X_REG_1F:
469 return true;
470 default:
471 break;
472 }
473
474 return false;
475}
476
477static bool max310x_reg_precious(struct device *dev, unsigned int reg)
478{
479 switch (reg & 0x1f) {
480 case MAX310X_RHR_REG:
481 case MAX310X_IRQSTS_REG:
482 case MAX310X_SPCHR_IRQSTS_REG:
483 case MAX310X_STS_IRQSTS_REG:
484 return true;
485 default:
486 break;
487 }
488
489 return false;
490}
491
492static int max310x_set_baud(struct uart_port *port, int baud)
493{
494 unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
495
496
497 if (div < 16)
498 div = 16;
499
500 if (clk % baud && (div / 16) < 0x8000) {
501
502 mode = MAX310X_BRGCFG_2XMODE_BIT;
503 clk = port->uartclk * 2;
504 div = clk / baud;
505
506 if (clk % baud && (div / 16) < 0x8000) {
507
508 mode = MAX310X_BRGCFG_4XMODE_BIT;
509 clk = port->uartclk * 4;
510 div = clk / baud;
511 }
512 }
513
514 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
515 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
516 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
517
518 return DIV_ROUND_CLOSEST(clk, div);
519}
520
521static int max310x_update_best_err(unsigned long f, long *besterr)
522{
523
524 long err = f % (115200 * 16);
525
526 if ((*besterr < 0) || (*besterr > err)) {
527 *besterr = err;
528 return 0;
529 }
530
531 return 1;
532}
533
534static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
535 unsigned long freq, bool xtal)
536{
537 unsigned int div, clksrc, pllcfg = 0;
538 long besterr = -1;
539 unsigned long fdiv, fmul, bestfreq = freq;
540
541
542 max310x_update_best_err(freq, &besterr);
543
544
545 for (div = 1; (div <= 63) && besterr; div++) {
546 fdiv = DIV_ROUND_CLOSEST(freq, div);
547
548
549 fmul = fdiv * 6;
550 if ((fdiv >= 500000) && (fdiv <= 800000))
551 if (!max310x_update_best_err(fmul, &besterr)) {
552 pllcfg = (0 << 6) | div;
553 bestfreq = fmul;
554 }
555
556 fmul = fdiv * 48;
557 if ((fdiv >= 850000) && (fdiv <= 1200000))
558 if (!max310x_update_best_err(fmul, &besterr)) {
559 pllcfg = (1 << 6) | div;
560 bestfreq = fmul;
561 }
562
563 fmul = fdiv * 96;
564 if ((fdiv >= 425000) && (fdiv <= 1000000))
565 if (!max310x_update_best_err(fmul, &besterr)) {
566 pllcfg = (2 << 6) | div;
567 bestfreq = fmul;
568 }
569
570 fmul = fdiv * 144;
571 if ((fdiv >= 390000) && (fdiv <= 667000))
572 if (!max310x_update_best_err(fmul, &besterr)) {
573 pllcfg = (3 << 6) | div;
574 bestfreq = fmul;
575 }
576 }
577
578
579 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
580
581
582 if (pllcfg) {
583 clksrc |= MAX310X_CLKSRC_PLL_BIT;
584 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
585 } else
586 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
587
588 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
589
590
591 if (xtal) {
592 unsigned int val;
593 msleep(10);
594 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
595 if (!(val & MAX310X_STS_CLKREADY_BIT)) {
596 dev_warn(dev, "clock is not stable yet\n");
597 }
598 }
599
600 return (int)bestfreq;
601}
602
603static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
604{
605 u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT };
606 struct spi_transfer xfer[] = {
607 {
608 .tx_buf = &header,
609 .len = sizeof(header),
610 }, {
611 .tx_buf = txbuf,
612 .len = len,
613 }
614 };
615 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
616}
617
618static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
619{
620 u8 header[] = { port->iobase + MAX310X_RHR_REG };
621 struct spi_transfer xfer[] = {
622 {
623 .tx_buf = &header,
624 .len = sizeof(header),
625 }, {
626 .rx_buf = rxbuf,
627 .len = len,
628 }
629 };
630 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
631}
632
633static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
634{
635 unsigned int sts, ch, flag, i;
636 u8 buf[MAX310X_FIFO_SIZE];
637
638 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
639
640
641
642
643
644
645
646
647
648
649
650 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
651 max310x_batch_read(port, buf, rxlen);
652
653 port->icount.rx += rxlen;
654 flag = TTY_NORMAL;
655 sts &= port->read_status_mask;
656
657 if (sts & MAX310X_LSR_RXOVR_BIT) {
658 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
659 port->icount.overrun++;
660 }
661
662 for (i = 0; i < rxlen; ++i) {
663 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag);
664 }
665
666 } else {
667 if (unlikely(rxlen >= port->fifosize)) {
668 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
669 port->icount.buf_overrun++;
670
671 rxlen = port->fifosize;
672 }
673
674 while (rxlen--) {
675 ch = max310x_port_read(port, MAX310X_RHR_REG);
676 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
677
678 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
679 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
680
681 port->icount.rx++;
682 flag = TTY_NORMAL;
683
684 if (unlikely(sts)) {
685 if (sts & MAX310X_LSR_RXBRK_BIT) {
686 port->icount.brk++;
687 if (uart_handle_break(port))
688 continue;
689 } else if (sts & MAX310X_LSR_RXPAR_BIT)
690 port->icount.parity++;
691 else if (sts & MAX310X_LSR_FRERR_BIT)
692 port->icount.frame++;
693 else if (sts & MAX310X_LSR_RXOVR_BIT)
694 port->icount.overrun++;
695
696 sts &= port->read_status_mask;
697 if (sts & MAX310X_LSR_RXBRK_BIT)
698 flag = TTY_BREAK;
699 else if (sts & MAX310X_LSR_RXPAR_BIT)
700 flag = TTY_PARITY;
701 else if (sts & MAX310X_LSR_FRERR_BIT)
702 flag = TTY_FRAME;
703 else if (sts & MAX310X_LSR_RXOVR_BIT)
704 flag = TTY_OVERRUN;
705 }
706
707 if (uart_handle_sysrq_char(port, ch))
708 continue;
709
710 if (sts & port->ignore_status_mask)
711 continue;
712
713 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
714 }
715 }
716
717 tty_flip_buffer_push(&port->state->port);
718}
719
720static void max310x_handle_tx(struct uart_port *port)
721{
722 struct circ_buf *xmit = &port->state->xmit;
723 unsigned int txlen, to_send, until_end;
724
725 if (unlikely(port->x_char)) {
726 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
727 port->icount.tx++;
728 port->x_char = 0;
729 return;
730 }
731
732 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
733 return;
734
735
736 to_send = uart_circ_chars_pending(xmit);
737 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
738 if (likely(to_send)) {
739
740 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
741 txlen = port->fifosize - txlen;
742 to_send = (to_send > txlen) ? txlen : to_send;
743
744 if (until_end < to_send) {
745
746
747 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
748 max310x_batch_write(port, xmit->buf, to_send - until_end);
749 } else {
750 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
751 }
752
753
754 port->icount.tx += to_send;
755 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
756 }
757
758 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
759 uart_write_wakeup(port);
760}
761
762static void max310x_start_tx(struct uart_port *port)
763{
764 struct max310x_one *one = container_of(port, struct max310x_one, port);
765
766 if (!work_pending(&one->tx_work))
767 schedule_work(&one->tx_work);
768}
769
770static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
771{
772 struct uart_port *port = &s->p[portno].port;
773 irqreturn_t res = IRQ_NONE;
774
775 do {
776 unsigned int ists, lsr, rxlen;
777
778
779 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
780 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
781 if (!ists && !rxlen)
782 break;
783
784 res = IRQ_HANDLED;
785
786 if (ists & MAX310X_IRQ_CTS_BIT) {
787 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
788 uart_handle_cts_change(port,
789 !!(lsr & MAX310X_LSR_CTS_BIT));
790 }
791 if (rxlen)
792 max310x_handle_rx(port, rxlen);
793 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
794 max310x_start_tx(port);
795 } while (1);
796 return res;
797}
798
799static irqreturn_t max310x_ist(int irq, void *dev_id)
800{
801 struct max310x_port *s = (struct max310x_port *)dev_id;
802 bool handled = false;
803
804 if (s->devtype->nr > 1) {
805 do {
806 unsigned int val = ~0;
807
808 WARN_ON_ONCE(regmap_read(s->regmap,
809 MAX310X_GLOBALIRQ_REG, &val));
810 val = ((1 << s->devtype->nr) - 1) & ~val;
811 if (!val)
812 break;
813 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
814 handled = true;
815 } while (1);
816 } else {
817 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
818 handled = true;
819 }
820
821 return IRQ_RETVAL(handled);
822}
823
824static void max310x_wq_proc(struct work_struct *ws)
825{
826 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
827 struct max310x_port *s = dev_get_drvdata(one->port.dev);
828
829 mutex_lock(&s->mutex);
830 max310x_handle_tx(&one->port);
831 mutex_unlock(&s->mutex);
832}
833
834static unsigned int max310x_tx_empty(struct uart_port *port)
835{
836 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
837
838 return lvl ? 0 : TIOCSER_TEMT;
839}
840
841static unsigned int max310x_get_mctrl(struct uart_port *port)
842{
843
844
845
846 return TIOCM_DSR | TIOCM_CAR;
847}
848
849static void max310x_md_proc(struct work_struct *ws)
850{
851 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
852
853 max310x_port_update(&one->port, MAX310X_MODE2_REG,
854 MAX310X_MODE2_LOOPBACK_BIT,
855 (one->port.mctrl & TIOCM_LOOP) ?
856 MAX310X_MODE2_LOOPBACK_BIT : 0);
857}
858
859static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
860{
861 struct max310x_one *one = container_of(port, struct max310x_one, port);
862
863 schedule_work(&one->md_work);
864}
865
866static void max310x_break_ctl(struct uart_port *port, int break_state)
867{
868 max310x_port_update(port, MAX310X_LCR_REG,
869 MAX310X_LCR_TXBREAK_BIT,
870 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
871}
872
873static void max310x_set_termios(struct uart_port *port,
874 struct ktermios *termios,
875 struct ktermios *old)
876{
877 unsigned int lcr = 0, flow = 0;
878 int baud;
879
880
881 termios->c_cflag &= ~CMSPAR;
882
883
884 switch (termios->c_cflag & CSIZE) {
885 case CS5:
886 break;
887 case CS6:
888 lcr = MAX310X_LCR_LENGTH0_BIT;
889 break;
890 case CS7:
891 lcr = MAX310X_LCR_LENGTH1_BIT;
892 break;
893 case CS8:
894 default:
895 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
896 break;
897 }
898
899
900 if (termios->c_cflag & PARENB) {
901 lcr |= MAX310X_LCR_PARITY_BIT;
902 if (!(termios->c_cflag & PARODD))
903 lcr |= MAX310X_LCR_EVENPARITY_BIT;
904 }
905
906
907 if (termios->c_cflag & CSTOPB)
908 lcr |= MAX310X_LCR_STOPLEN_BIT;
909
910
911 max310x_port_write(port, MAX310X_LCR_REG, lcr);
912
913
914 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
915 if (termios->c_iflag & INPCK)
916 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
917 MAX310X_LSR_FRERR_BIT;
918 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
919 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
920
921
922 port->ignore_status_mask = 0;
923 if (termios->c_iflag & IGNBRK)
924 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
925 if (!(termios->c_cflag & CREAD))
926 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
927 MAX310X_LSR_RXOVR_BIT |
928 MAX310X_LSR_FRERR_BIT |
929 MAX310X_LSR_RXBRK_BIT;
930
931
932 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
933 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
934 if (termios->c_cflag & CRTSCTS)
935 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
936 MAX310X_FLOWCTRL_AUTORTS_BIT;
937 if (termios->c_iflag & IXON)
938 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
939 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
940 if (termios->c_iflag & IXOFF)
941 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
942 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
943 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
944
945
946 baud = uart_get_baud_rate(port, termios, old,
947 port->uartclk / 16 / 0xffff,
948 port->uartclk / 4);
949
950
951 baud = max310x_set_baud(port, baud);
952
953
954 uart_update_timeout(port, termios->c_cflag, baud);
955}
956
957static void max310x_rs_proc(struct work_struct *ws)
958{
959 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
960 unsigned int val;
961
962 val = (one->port.rs485.delay_rts_before_send << 4) |
963 one->port.rs485.delay_rts_after_send;
964 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
965
966 if (one->port.rs485.flags & SER_RS485_ENABLED) {
967 max310x_port_update(&one->port, MAX310X_MODE1_REG,
968 MAX310X_MODE1_TRNSCVCTRL_BIT,
969 MAX310X_MODE1_TRNSCVCTRL_BIT);
970 max310x_port_update(&one->port, MAX310X_MODE2_REG,
971 MAX310X_MODE2_ECHOSUPR_BIT,
972 MAX310X_MODE2_ECHOSUPR_BIT);
973 } else {
974 max310x_port_update(&one->port, MAX310X_MODE1_REG,
975 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
976 max310x_port_update(&one->port, MAX310X_MODE2_REG,
977 MAX310X_MODE2_ECHOSUPR_BIT, 0);
978 }
979}
980
981static int max310x_rs485_config(struct uart_port *port,
982 struct serial_rs485 *rs485)
983{
984 struct max310x_one *one = container_of(port, struct max310x_one, port);
985
986 if ((rs485->delay_rts_before_send > 0x0f) ||
987 (rs485->delay_rts_after_send > 0x0f))
988 return -ERANGE;
989
990 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
991 memset(rs485->padding, 0, sizeof(rs485->padding));
992 port->rs485 = *rs485;
993
994 schedule_work(&one->rs_work);
995
996 return 0;
997}
998
999static int max310x_startup(struct uart_port *port)
1000{
1001 struct max310x_port *s = dev_get_drvdata(port->dev);
1002 unsigned int val;
1003
1004 s->devtype->power(port, 1);
1005
1006
1007 max310x_port_update(port, MAX310X_MODE1_REG,
1008 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1009
1010
1011 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1012 max310x_port_write(port, MAX310X_MODE2_REG, val);
1013 max310x_port_update(port, MAX310X_MODE2_REG,
1014 MAX310X_MODE2_FIFORST_BIT, 0);
1015
1016
1017
1018 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1019 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1020
1021
1022 max310x_port_read(port, MAX310X_IRQSTS_REG);
1023
1024
1025 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1026 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1027
1028 return 0;
1029}
1030
1031static void max310x_shutdown(struct uart_port *port)
1032{
1033 struct max310x_port *s = dev_get_drvdata(port->dev);
1034
1035
1036 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1037
1038 s->devtype->power(port, 0);
1039}
1040
1041static const char *max310x_type(struct uart_port *port)
1042{
1043 struct max310x_port *s = dev_get_drvdata(port->dev);
1044
1045 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1046}
1047
1048static int max310x_request_port(struct uart_port *port)
1049{
1050
1051 return 0;
1052}
1053
1054static void max310x_config_port(struct uart_port *port, int flags)
1055{
1056 if (flags & UART_CONFIG_TYPE)
1057 port->type = PORT_MAX310X;
1058}
1059
1060static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1061{
1062 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1063 return -EINVAL;
1064 if (s->irq != port->irq)
1065 return -EINVAL;
1066
1067 return 0;
1068}
1069
1070static void max310x_null_void(struct uart_port *port)
1071{
1072
1073}
1074
1075static const struct uart_ops max310x_ops = {
1076 .tx_empty = max310x_tx_empty,
1077 .set_mctrl = max310x_set_mctrl,
1078 .get_mctrl = max310x_get_mctrl,
1079 .stop_tx = max310x_null_void,
1080 .start_tx = max310x_start_tx,
1081 .stop_rx = max310x_null_void,
1082 .break_ctl = max310x_break_ctl,
1083 .startup = max310x_startup,
1084 .shutdown = max310x_shutdown,
1085 .set_termios = max310x_set_termios,
1086 .type = max310x_type,
1087 .request_port = max310x_request_port,
1088 .release_port = max310x_null_void,
1089 .config_port = max310x_config_port,
1090 .verify_port = max310x_verify_port,
1091};
1092
1093static int __maybe_unused max310x_suspend(struct device *dev)
1094{
1095 struct max310x_port *s = dev_get_drvdata(dev);
1096 int i;
1097
1098 for (i = 0; i < s->devtype->nr; i++) {
1099 uart_suspend_port(&max310x_uart, &s->p[i].port);
1100 s->devtype->power(&s->p[i].port, 0);
1101 }
1102
1103 return 0;
1104}
1105
1106static int __maybe_unused max310x_resume(struct device *dev)
1107{
1108 struct max310x_port *s = dev_get_drvdata(dev);
1109 int i;
1110
1111 for (i = 0; i < s->devtype->nr; i++) {
1112 s->devtype->power(&s->p[i].port, 1);
1113 uart_resume_port(&max310x_uart, &s->p[i].port);
1114 }
1115
1116 return 0;
1117}
1118
1119static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1120
1121#ifdef CONFIG_GPIOLIB
1122static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1123{
1124 unsigned int val;
1125 struct max310x_port *s = gpiochip_get_data(chip);
1126 struct uart_port *port = &s->p[offset / 4].port;
1127
1128 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1129
1130 return !!((val >> 4) & (1 << (offset % 4)));
1131}
1132
1133static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1134{
1135 struct max310x_port *s = gpiochip_get_data(chip);
1136 struct uart_port *port = &s->p[offset / 4].port;
1137
1138 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1139 value ? 1 << (offset % 4) : 0);
1140}
1141
1142static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1143{
1144 struct max310x_port *s = gpiochip_get_data(chip);
1145 struct uart_port *port = &s->p[offset / 4].port;
1146
1147 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1148
1149 return 0;
1150}
1151
1152static int max310x_gpio_direction_output(struct gpio_chip *chip,
1153 unsigned offset, int value)
1154{
1155 struct max310x_port *s = gpiochip_get_data(chip);
1156 struct uart_port *port = &s->p[offset / 4].port;
1157
1158 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1159 value ? 1 << (offset % 4) : 0);
1160 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1161 1 << (offset % 4));
1162
1163 return 0;
1164}
1165
1166static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1167 unsigned long config)
1168{
1169 struct max310x_port *s = gpiochip_get_data(chip);
1170 struct uart_port *port = &s->p[offset / 4].port;
1171
1172 switch (pinconf_to_config_param(config)) {
1173 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1174 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1175 1 << ((offset % 4) + 4),
1176 1 << ((offset % 4) + 4));
1177 return 0;
1178 case PIN_CONFIG_DRIVE_PUSH_PULL:
1179 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1180 1 << ((offset % 4) + 4), 0);
1181 return 0;
1182 default:
1183 return -ENOTSUPP;
1184 }
1185}
1186#endif
1187
1188static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1189 struct regmap *regmap, int irq)
1190{
1191 int i, ret, fmin, fmax, freq, uartclk;
1192 struct clk *clk_osc, *clk_xtal;
1193 struct max310x_port *s;
1194 bool xtal = false;
1195
1196 if (IS_ERR(regmap))
1197 return PTR_ERR(regmap);
1198
1199
1200 s = devm_kzalloc(dev, sizeof(*s) +
1201 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1202 if (!s) {
1203 dev_err(dev, "Error allocating port structure\n");
1204 return -ENOMEM;
1205 }
1206
1207 clk_osc = devm_clk_get(dev, "osc");
1208 clk_xtal = devm_clk_get(dev, "xtal");
1209 if (!IS_ERR(clk_osc)) {
1210 s->clk = clk_osc;
1211 fmin = 500000;
1212 fmax = 35000000;
1213 } else if (!IS_ERR(clk_xtal)) {
1214 s->clk = clk_xtal;
1215 fmin = 1000000;
1216 fmax = 4000000;
1217 xtal = true;
1218 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1219 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1220 return -EPROBE_DEFER;
1221 } else {
1222 dev_err(dev, "Cannot get clock\n");
1223 return -EINVAL;
1224 }
1225
1226 ret = clk_prepare_enable(s->clk);
1227 if (ret)
1228 return ret;
1229
1230 freq = clk_get_rate(s->clk);
1231
1232 if (freq < fmin || freq > fmax) {
1233 ret = -ERANGE;
1234 goto out_clk;
1235 }
1236
1237 s->regmap = regmap;
1238 s->devtype = devtype;
1239 dev_set_drvdata(dev, s);
1240
1241
1242 ret = devtype->detect(dev);
1243 if (ret)
1244 goto out_clk;
1245
1246 for (i = 0; i < devtype->nr; i++) {
1247 unsigned int offs = i << 5;
1248
1249
1250 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1251 MAX310X_MODE2_RST_BIT);
1252
1253 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1254
1255
1256 do {
1257 regmap_read(s->regmap,
1258 MAX310X_BRGDIVLSB_REG + offs, &ret);
1259 } while (ret != 0x01);
1260
1261 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1262 MAX310X_MODE1_AUTOSLEEP_BIT,
1263 MAX310X_MODE1_AUTOSLEEP_BIT);
1264 }
1265
1266 uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1267 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1268
1269 mutex_init(&s->mutex);
1270
1271 for (i = 0; i < devtype->nr; i++) {
1272 unsigned int line;
1273
1274 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1275 if (line == MAX310X_UART_NRMAX) {
1276 ret = -ERANGE;
1277 goto out_uart;
1278 }
1279
1280
1281 s->p[i].port.line = line;
1282 s->p[i].port.dev = dev;
1283 s->p[i].port.irq = irq;
1284 s->p[i].port.type = PORT_MAX310X;
1285 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1286 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1287 s->p[i].port.iotype = UPIO_PORT;
1288 s->p[i].port.iobase = i * 0x20;
1289 s->p[i].port.membase = (void __iomem *)~0;
1290 s->p[i].port.uartclk = uartclk;
1291 s->p[i].port.rs485_config = max310x_rs485_config;
1292 s->p[i].port.ops = &max310x_ops;
1293
1294 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1295
1296 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1297
1298 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1299 MAX310X_MODE1_IRQSEL_BIT,
1300 MAX310X_MODE1_IRQSEL_BIT);
1301
1302 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1303
1304 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1305
1306 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1307
1308
1309 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1310 if (ret) {
1311 s->p[i].port.dev = NULL;
1312 goto out_uart;
1313 }
1314 set_bit(line, max310x_lines);
1315
1316
1317 devtype->power(&s->p[i].port, 0);
1318 }
1319
1320#ifdef CONFIG_GPIOLIB
1321
1322 s->gpio.owner = THIS_MODULE;
1323 s->gpio.parent = dev;
1324 s->gpio.label = devtype->name;
1325 s->gpio.direction_input = max310x_gpio_direction_input;
1326 s->gpio.get = max310x_gpio_get;
1327 s->gpio.direction_output= max310x_gpio_direction_output;
1328 s->gpio.set = max310x_gpio_set;
1329 s->gpio.set_config = max310x_gpio_set_config;
1330 s->gpio.base = -1;
1331 s->gpio.ngpio = devtype->nr * 4;
1332 s->gpio.can_sleep = 1;
1333 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1334 if (ret)
1335 goto out_uart;
1336#endif
1337
1338
1339 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1340 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1341 if (!ret)
1342 return 0;
1343
1344 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1345
1346out_uart:
1347 for (i = 0; i < devtype->nr; i++) {
1348 if (s->p[i].port.dev) {
1349 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1350 clear_bit(s->p[i].port.line, max310x_lines);
1351 }
1352 }
1353
1354 mutex_destroy(&s->mutex);
1355
1356out_clk:
1357 clk_disable_unprepare(s->clk);
1358
1359 return ret;
1360}
1361
1362static int max310x_remove(struct device *dev)
1363{
1364 struct max310x_port *s = dev_get_drvdata(dev);
1365 int i;
1366
1367 for (i = 0; i < s->devtype->nr; i++) {
1368 cancel_work_sync(&s->p[i].tx_work);
1369 cancel_work_sync(&s->p[i].md_work);
1370 cancel_work_sync(&s->p[i].rs_work);
1371 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1372 clear_bit(s->p[i].port.line, max310x_lines);
1373 s->devtype->power(&s->p[i].port, 0);
1374 }
1375
1376 mutex_destroy(&s->mutex);
1377 clk_disable_unprepare(s->clk);
1378
1379 return 0;
1380}
1381
1382static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1383 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1384 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1385 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1386 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1387 { }
1388};
1389MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1390
1391static struct regmap_config regcfg = {
1392 .reg_bits = 8,
1393 .val_bits = 8,
1394 .write_flag_mask = MAX310X_WRITE_BIT,
1395 .cache_type = REGCACHE_RBTREE,
1396 .writeable_reg = max310x_reg_writeable,
1397 .volatile_reg = max310x_reg_volatile,
1398 .precious_reg = max310x_reg_precious,
1399};
1400
1401#ifdef CONFIG_SPI_MASTER
1402static int max310x_spi_probe(struct spi_device *spi)
1403{
1404 struct max310x_devtype *devtype;
1405 struct regmap *regmap;
1406 int ret;
1407
1408
1409 spi->bits_per_word = 8;
1410 spi->mode = spi->mode ? : SPI_MODE_0;
1411 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1412 ret = spi_setup(spi);
1413 if (ret)
1414 return ret;
1415
1416 if (spi->dev.of_node) {
1417 const struct of_device_id *of_id =
1418 of_match_device(max310x_dt_ids, &spi->dev);
1419
1420 devtype = (struct max310x_devtype *)of_id->data;
1421 } else {
1422 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1423
1424 devtype = (struct max310x_devtype *)id_entry->driver_data;
1425 }
1426
1427 regcfg.max_register = devtype->nr * 0x20 - 1;
1428 regmap = devm_regmap_init_spi(spi, ®cfg);
1429
1430 return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
1431}
1432
1433static int max310x_spi_remove(struct spi_device *spi)
1434{
1435 return max310x_remove(&spi->dev);
1436}
1437
1438static const struct spi_device_id max310x_id_table[] = {
1439 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1440 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1441 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1442 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1443 { }
1444};
1445MODULE_DEVICE_TABLE(spi, max310x_id_table);
1446
1447static struct spi_driver max310x_spi_driver = {
1448 .driver = {
1449 .name = MAX310X_NAME,
1450 .of_match_table = of_match_ptr(max310x_dt_ids),
1451 .pm = &max310x_pm_ops,
1452 },
1453 .probe = max310x_spi_probe,
1454 .remove = max310x_spi_remove,
1455 .id_table = max310x_id_table,
1456};
1457#endif
1458
1459static int __init max310x_uart_init(void)
1460{
1461 int ret;
1462
1463 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1464
1465 ret = uart_register_driver(&max310x_uart);
1466 if (ret)
1467 return ret;
1468
1469#ifdef CONFIG_SPI_MASTER
1470 spi_register_driver(&max310x_spi_driver);
1471#endif
1472
1473 return 0;
1474}
1475module_init(max310x_uart_init);
1476
1477static void __exit max310x_uart_exit(void)
1478{
1479#ifdef CONFIG_SPI_MASTER
1480 spi_unregister_driver(&max310x_spi_driver);
1481#endif
1482
1483 uart_unregister_driver(&max310x_uart);
1484}
1485module_exit(max310x_uart_exit);
1486
1487MODULE_LICENSE("GPL");
1488MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1489MODULE_DESCRIPTION("MAX310X serial driver");
1490