linux/drivers/video/fbdev/riva/fbdev.c
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   1/*
   2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
   3 *
   4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
   5 *
   6 * Copyright 1999-2000 Jeff Garzik
   7 *
   8 * Contributors:
   9 *
  10 *      Ani Joshi:  Lots of debugging and cleanup work, really helped
  11 *      get the driver going
  12 *
  13 *      Ferenc Bakonyi:  Bug fixes, cleanup, modularization
  14 *
  15 *      Jindrich Makovicka:  Accel code help, hw cursor, mtrr
  16 *
  17 *      Paul Richards:  Bug fixes, updates
  18 *
  19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
  20 * Includes riva_hw.c from nVidia, see copyright below.
  21 * KGI code provided the basis for state storage, init, and mode switching.
  22 *
  23 * This file is subject to the terms and conditions of the GNU General Public
  24 * License.  See the file COPYING in the main directory of this archive
  25 * for more details.
  26 *
  27 * Known bugs and issues:
  28 *      restoring text mode fails
  29 *      doublescan modes are broken
  30 */
  31
  32#include <linux/module.h>
  33#include <linux/kernel.h>
  34#include <linux/errno.h>
  35#include <linux/string.h>
  36#include <linux/mm.h>
  37#include <linux/slab.h>
  38#include <linux/delay.h>
  39#include <linux/fb.h>
  40#include <linux/init.h>
  41#include <linux/pci.h>
  42#include <linux/backlight.h>
  43#include <linux/bitrev.h>
  44#ifdef CONFIG_PMAC_BACKLIGHT
  45#include <asm/machdep.h>
  46#include <asm/backlight.h>
  47#endif
  48
  49#include "rivafb.h"
  50#include "nvreg.h"
  51
  52/* version number of this driver */
  53#define RIVAFB_VERSION "0.9.5b"
  54
  55/* ------------------------------------------------------------------------- *
  56 *
  57 * various helpful macros and constants
  58 *
  59 * ------------------------------------------------------------------------- */
  60#ifdef CONFIG_FB_RIVA_DEBUG
  61#define NVTRACE          printk
  62#else
  63#define NVTRACE          if(0) printk
  64#endif
  65
  66#define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __func__)
  67#define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __func__)
  68
  69#ifdef CONFIG_FB_RIVA_DEBUG
  70#define assert(expr) \
  71        if(!(expr)) { \
  72        printk( "Assertion failed! %s,%s,%s,line=%d\n",\
  73        #expr,__FILE__,__func__,__LINE__); \
  74        BUG(); \
  75        }
  76#else
  77#define assert(expr)
  78#endif
  79
  80#define PFX "rivafb: "
  81
  82/* macro that allows you to set overflow bits */
  83#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
  84#define SetBit(n)               (1<<(n))
  85#define Set8Bits(value)         ((value)&0xff)
  86
  87/* HW cursor parameters */
  88#define MAX_CURS                32
  89
  90/* ------------------------------------------------------------------------- *
  91 *
  92 * prototypes
  93 *
  94 * ------------------------------------------------------------------------- */
  95
  96static int rivafb_blank(int blank, struct fb_info *info);
  97
  98/* ------------------------------------------------------------------------- *
  99 *
 100 * card identification
 101 *
 102 * ------------------------------------------------------------------------- */
 103
 104static const struct pci_device_id rivafb_pci_tbl[] = {
 105        { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
 106          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 107        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
 108          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 109        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
 110          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 111        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
 112          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 113        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
 114          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 115        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
 116          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 117        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
 118          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 119        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
 120          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 121        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
 122          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 123        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
 124          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 125        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
 126          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 127        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
 128          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 129        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
 130          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 131        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
 132          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 133        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
 134          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 135        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
 136          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 137        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
 138          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 139        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
 140          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 141        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
 142          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 143        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
 144          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 145        // NF2/IGP version, GeForce 4 MX, NV18
 146        { PCI_VENDOR_ID_NVIDIA, 0x01f0,
 147          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 148        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
 149          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 150        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
 151          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 152        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
 153          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 154        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
 155          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 156        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
 157          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 158        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
 159          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 160        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
 161          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 162        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
 163          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 164        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
 165          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 166        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
 167          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 168        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
 169          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 170        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
 171          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 172        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
 173          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 174        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
 175          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 176        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
 177          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 178        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
 179          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 180        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
 181          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 182        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
 183          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 184        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
 185          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 186        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
 187          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 188        { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
 189          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 190        { 0, } /* terminate list */
 191};
 192MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
 193
 194/* ------------------------------------------------------------------------- *
 195 *
 196 * global variables
 197 *
 198 * ------------------------------------------------------------------------- */
 199
 200/* command line data, set in rivafb_setup() */
 201static int flatpanel = -1; /* Autodetect later */
 202static int forceCRTC = -1;
 203static bool noaccel  = 0;
 204static bool nomtrr = 0;
 205#ifdef CONFIG_PMAC_BACKLIGHT
 206static int backlight = 1;
 207#else
 208static int backlight = 0;
 209#endif
 210
 211static char *mode_option = NULL;
 212static bool strictmode       = 0;
 213
 214static struct fb_fix_screeninfo rivafb_fix = {
 215        .type           = FB_TYPE_PACKED_PIXELS,
 216        .xpanstep       = 1,
 217        .ypanstep       = 1,
 218};
 219
 220static struct fb_var_screeninfo rivafb_default_var = {
 221        .xres           = 640,
 222        .yres           = 480,
 223        .xres_virtual   = 640,
 224        .yres_virtual   = 480,
 225        .bits_per_pixel = 8,
 226        .red            = {0, 8, 0},
 227        .green          = {0, 8, 0},
 228        .blue           = {0, 8, 0},
 229        .transp         = {0, 0, 0},
 230        .activate       = FB_ACTIVATE_NOW,
 231        .height         = -1,
 232        .width          = -1,
 233        .pixclock       = 39721,
 234        .left_margin    = 40,
 235        .right_margin   = 24,
 236        .upper_margin   = 32,
 237        .lower_margin   = 11,
 238        .hsync_len      = 96,
 239        .vsync_len      = 2,
 240        .vmode          = FB_VMODE_NONINTERLACED
 241};
 242
 243/* from GGI */
 244static const struct riva_regs reg_template = {
 245        {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,        /* ATTR */
 246         0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 247         0x41, 0x01, 0x0F, 0x00, 0x00},
 248        {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,        /* CRT  */
 249         0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
 250         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3,        /* 0x10 */
 251         0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 252         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,        /* 0x20 */
 253         0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 254         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,        /* 0x30 */
 255         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 256         0x00,                                                  /* 0x40 */
 257         },
 258        {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,        /* GRA  */
 259         0xFF},
 260        {0x03, 0x01, 0x0F, 0x00, 0x0E},                         /* SEQ  */
 261        0xEB                                                    /* MISC */
 262};
 263
 264/*
 265 * Backlight control
 266 */
 267#ifdef CONFIG_FB_RIVA_BACKLIGHT
 268/* We do not have any information about which values are allowed, thus
 269 * we used safe values.
 270 */
 271#define MIN_LEVEL 0x158
 272#define MAX_LEVEL 0x534
 273#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
 274
 275static int riva_bl_get_level_brightness(struct riva_par *par,
 276                int level)
 277{
 278        struct fb_info *info = pci_get_drvdata(par->pdev);
 279        int nlevel;
 280
 281        /* Get and convert the value */
 282        /* No locking on bl_curve since accessing a single value */
 283        nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
 284
 285        if (nlevel < 0)
 286                nlevel = 0;
 287        else if (nlevel < MIN_LEVEL)
 288                nlevel = MIN_LEVEL;
 289        else if (nlevel > MAX_LEVEL)
 290                nlevel = MAX_LEVEL;
 291
 292        return nlevel;
 293}
 294
 295static int riva_bl_update_status(struct backlight_device *bd)
 296{
 297        struct riva_par *par = bl_get_data(bd);
 298        U032 tmp_pcrt, tmp_pmc;
 299        int level;
 300
 301        if (bd->props.power != FB_BLANK_UNBLANK ||
 302            bd->props.fb_blank != FB_BLANK_UNBLANK)
 303                level = 0;
 304        else
 305                level = bd->props.brightness;
 306
 307        tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
 308        tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
 309        if(level > 0) {
 310                tmp_pcrt |= 0x1;
 311                tmp_pmc |= (1 << 31); /* backlight bit */
 312                tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
 313        }
 314        NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
 315        NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
 316
 317        return 0;
 318}
 319
 320static const struct backlight_ops riva_bl_ops = {
 321        .update_status  = riva_bl_update_status,
 322};
 323
 324static void riva_bl_init(struct riva_par *par)
 325{
 326        struct backlight_properties props;
 327        struct fb_info *info = pci_get_drvdata(par->pdev);
 328        struct backlight_device *bd;
 329        char name[12];
 330
 331        if (!par->FlatPanel)
 332                return;
 333
 334#ifdef CONFIG_PMAC_BACKLIGHT
 335        if (!machine_is(powermac) ||
 336            !pmac_has_backlight_type("mnca"))
 337                return;
 338#endif
 339
 340        snprintf(name, sizeof(name), "rivabl%d", info->node);
 341
 342        memset(&props, 0, sizeof(struct backlight_properties));
 343        props.type = BACKLIGHT_RAW;
 344        props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
 345        bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
 346                                       &props);
 347        if (IS_ERR(bd)) {
 348                info->bl_dev = NULL;
 349                printk(KERN_WARNING "riva: Backlight registration failed\n");
 350                goto error;
 351        }
 352
 353        info->bl_dev = bd;
 354        fb_bl_default_curve(info, 0,
 355                MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
 356                FB_BACKLIGHT_MAX);
 357
 358        bd->props.brightness = bd->props.max_brightness;
 359        bd->props.power = FB_BLANK_UNBLANK;
 360        backlight_update_status(bd);
 361
 362        printk("riva: Backlight initialized (%s)\n", name);
 363
 364        return;
 365
 366error:
 367        return;
 368}
 369
 370static void riva_bl_exit(struct fb_info *info)
 371{
 372        struct backlight_device *bd = info->bl_dev;
 373
 374        backlight_device_unregister(bd);
 375        printk("riva: Backlight unloaded\n");
 376}
 377#else
 378static inline void riva_bl_init(struct riva_par *par) {}
 379static inline void riva_bl_exit(struct fb_info *info) {}
 380#endif /* CONFIG_FB_RIVA_BACKLIGHT */
 381
 382/* ------------------------------------------------------------------------- *
 383 *
 384 * MMIO access macros
 385 *
 386 * ------------------------------------------------------------------------- */
 387
 388static inline void CRTCout(struct riva_par *par, unsigned char index,
 389                           unsigned char val)
 390{
 391        VGA_WR08(par->riva.PCIO, 0x3d4, index);
 392        VGA_WR08(par->riva.PCIO, 0x3d5, val);
 393}
 394
 395static inline unsigned char CRTCin(struct riva_par *par,
 396                                   unsigned char index)
 397{
 398        VGA_WR08(par->riva.PCIO, 0x3d4, index);
 399        return (VGA_RD08(par->riva.PCIO, 0x3d5));
 400}
 401
 402static inline void GRAout(struct riva_par *par, unsigned char index,
 403                          unsigned char val)
 404{
 405        VGA_WR08(par->riva.PVIO, 0x3ce, index);
 406        VGA_WR08(par->riva.PVIO, 0x3cf, val);
 407}
 408
 409static inline unsigned char GRAin(struct riva_par *par,
 410                                  unsigned char index)
 411{
 412        VGA_WR08(par->riva.PVIO, 0x3ce, index);
 413        return (VGA_RD08(par->riva.PVIO, 0x3cf));
 414}
 415
 416static inline void SEQout(struct riva_par *par, unsigned char index,
 417                          unsigned char val)
 418{
 419        VGA_WR08(par->riva.PVIO, 0x3c4, index);
 420        VGA_WR08(par->riva.PVIO, 0x3c5, val);
 421}
 422
 423static inline unsigned char SEQin(struct riva_par *par,
 424                                  unsigned char index)
 425{
 426        VGA_WR08(par->riva.PVIO, 0x3c4, index);
 427        return (VGA_RD08(par->riva.PVIO, 0x3c5));
 428}
 429
 430static inline void ATTRout(struct riva_par *par, unsigned char index,
 431                           unsigned char val)
 432{
 433        VGA_WR08(par->riva.PCIO, 0x3c0, index);
 434        VGA_WR08(par->riva.PCIO, 0x3c0, val);
 435}
 436
 437static inline unsigned char ATTRin(struct riva_par *par,
 438                                   unsigned char index)
 439{
 440        VGA_WR08(par->riva.PCIO, 0x3c0, index);
 441        return (VGA_RD08(par->riva.PCIO, 0x3c1));
 442}
 443
 444static inline void MISCout(struct riva_par *par, unsigned char val)
 445{
 446        VGA_WR08(par->riva.PVIO, 0x3c2, val);
 447}
 448
 449static inline unsigned char MISCin(struct riva_par *par)
 450{
 451        return (VGA_RD08(par->riva.PVIO, 0x3cc));
 452}
 453
 454static inline void reverse_order(u32 *l)
 455{
 456        u8 *a = (u8 *)l;
 457        a[0] = bitrev8(a[0]);
 458        a[1] = bitrev8(a[1]);
 459        a[2] = bitrev8(a[2]);
 460        a[3] = bitrev8(a[3]);
 461}
 462
 463/* ------------------------------------------------------------------------- *
 464 *
 465 * cursor stuff
 466 *
 467 * ------------------------------------------------------------------------- */
 468
 469/**
 470 * rivafb_load_cursor_image - load cursor image to hardware
 471 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
 472 * @par:  pointer to private data
 473 * @w:    width of cursor image in pixels
 474 * @h:    height of cursor image in scanlines
 475 * @bg:   background color (ARGB1555) - alpha bit determines opacity
 476 * @fg:   foreground color (ARGB1555)
 477 *
 478 * DESCRIPTiON:
 479 * Loads cursor image based on a monochrome source and mask bitmap.  The
 480 * image bits determines the color of the pixel, 0 for background, 1 for
 481 * foreground.  Only the affected region (as determined by @w and @h 
 482 * parameters) will be updated.
 483 *
 484 * CALLED FROM:
 485 * rivafb_cursor()
 486 */
 487static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
 488                                     u16 bg, u16 fg, u32 w, u32 h)
 489{
 490        int i, j, k = 0;
 491        u32 b, tmp;
 492        u32 *data = (u32 *)data8;
 493        bg = le16_to_cpu(bg);
 494        fg = le16_to_cpu(fg);
 495
 496        w = (w + 1) & ~1;
 497
 498        for (i = 0; i < h; i++) {
 499                b = *data++;
 500                reverse_order(&b);
 501                
 502                for (j = 0; j < w/2; j++) {
 503                        tmp = 0;
 504#if defined (__BIG_ENDIAN)
 505                        tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
 506                        b <<= 1;
 507                        tmp |= (b & (1 << 31)) ? fg : bg;
 508                        b <<= 1;
 509#else
 510                        tmp = (b & 1) ? fg : bg;
 511                        b >>= 1;
 512                        tmp |= (b & 1) ? fg << 16 : bg << 16;
 513                        b >>= 1;
 514#endif
 515                        writel(tmp, &par->riva.CURSOR[k++]);
 516                }
 517                k += (MAX_CURS - w)/2;
 518        }
 519}
 520
 521/* ------------------------------------------------------------------------- *
 522 *
 523 * general utility functions
 524 *
 525 * ------------------------------------------------------------------------- */
 526
 527/**
 528 * riva_wclut - set CLUT entry
 529 * @chip: pointer to RIVA_HW_INST object
 530 * @regnum: register number
 531 * @red: red component
 532 * @green: green component
 533 * @blue: blue component
 534 *
 535 * DESCRIPTION:
 536 * Sets color register @regnum.
 537 *
 538 * CALLED FROM:
 539 * rivafb_setcolreg()
 540 */
 541static void riva_wclut(RIVA_HW_INST *chip,
 542                       unsigned char regnum, unsigned char red,
 543                       unsigned char green, unsigned char blue)
 544{
 545        VGA_WR08(chip->PDIO, 0x3c8, regnum);
 546        VGA_WR08(chip->PDIO, 0x3c9, red);
 547        VGA_WR08(chip->PDIO, 0x3c9, green);
 548        VGA_WR08(chip->PDIO, 0x3c9, blue);
 549}
 550
 551/**
 552 * riva_rclut - read fromCLUT register
 553 * @chip: pointer to RIVA_HW_INST object
 554 * @regnum: register number
 555 * @red: red component
 556 * @green: green component
 557 * @blue: blue component
 558 *
 559 * DESCRIPTION:
 560 * Reads red, green, and blue from color register @regnum.
 561 *
 562 * CALLED FROM:
 563 * rivafb_setcolreg()
 564 */
 565static void riva_rclut(RIVA_HW_INST *chip,
 566                       unsigned char regnum, unsigned char *red,
 567                       unsigned char *green, unsigned char *blue)
 568{
 569        
 570        VGA_WR08(chip->PDIO, 0x3c7, regnum);
 571        *red = VGA_RD08(chip->PDIO, 0x3c9);
 572        *green = VGA_RD08(chip->PDIO, 0x3c9);
 573        *blue = VGA_RD08(chip->PDIO, 0x3c9);
 574}
 575
 576/**
 577 * riva_save_state - saves current chip state
 578 * @par: pointer to riva_par object containing info for current riva board
 579 * @regs: pointer to riva_regs object
 580 *
 581 * DESCRIPTION:
 582 * Saves current chip state to @regs.
 583 *
 584 * CALLED FROM:
 585 * rivafb_probe()
 586 */
 587/* from GGI */
 588static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
 589{
 590        int i;
 591
 592        NVTRACE_ENTER();
 593        par->riva.LockUnlock(&par->riva, 0);
 594
 595        par->riva.UnloadStateExt(&par->riva, &regs->ext);
 596
 597        regs->misc_output = MISCin(par);
 598
 599        for (i = 0; i < NUM_CRT_REGS; i++)
 600                regs->crtc[i] = CRTCin(par, i);
 601
 602        for (i = 0; i < NUM_ATC_REGS; i++)
 603                regs->attr[i] = ATTRin(par, i);
 604
 605        for (i = 0; i < NUM_GRC_REGS; i++)
 606                regs->gra[i] = GRAin(par, i);
 607
 608        for (i = 0; i < NUM_SEQ_REGS; i++)
 609                regs->seq[i] = SEQin(par, i);
 610        NVTRACE_LEAVE();
 611}
 612
 613/**
 614 * riva_load_state - loads current chip state
 615 * @par: pointer to riva_par object containing info for current riva board
 616 * @regs: pointer to riva_regs object
 617 *
 618 * DESCRIPTION:
 619 * Loads chip state from @regs.
 620 *
 621 * CALLED FROM:
 622 * riva_load_video_mode()
 623 * rivafb_probe()
 624 * rivafb_remove()
 625 */
 626/* from GGI */
 627static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
 628{
 629        RIVA_HW_STATE *state = &regs->ext;
 630        int i;
 631
 632        NVTRACE_ENTER();
 633        CRTCout(par, 0x11, 0x00);
 634
 635        par->riva.LockUnlock(&par->riva, 0);
 636
 637        par->riva.LoadStateExt(&par->riva, state);
 638
 639        MISCout(par, regs->misc_output);
 640
 641        for (i = 0; i < NUM_CRT_REGS; i++) {
 642                switch (i) {
 643                case 0x19:
 644                case 0x20 ... 0x40:
 645                        break;
 646                default:
 647                        CRTCout(par, i, regs->crtc[i]);
 648                }
 649        }
 650
 651        for (i = 0; i < NUM_ATC_REGS; i++)
 652                ATTRout(par, i, regs->attr[i]);
 653
 654        for (i = 0; i < NUM_GRC_REGS; i++)
 655                GRAout(par, i, regs->gra[i]);
 656
 657        for (i = 0; i < NUM_SEQ_REGS; i++)
 658                SEQout(par, i, regs->seq[i]);
 659        NVTRACE_LEAVE();
 660}
 661
 662/**
 663 * riva_load_video_mode - calculate timings
 664 * @info: pointer to fb_info object containing info for current riva board
 665 *
 666 * DESCRIPTION:
 667 * Calculate some timings and then send em off to riva_load_state().
 668 *
 669 * CALLED FROM:
 670 * rivafb_set_par()
 671 */
 672static int riva_load_video_mode(struct fb_info *info)
 673{
 674        int bpp, width, hDisplaySize, hDisplay, hStart,
 675            hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
 676        int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
 677        int rc;
 678        struct riva_par *par = info->par;
 679        struct riva_regs newmode;
 680        
 681        NVTRACE_ENTER();
 682        /* time to calculate */
 683        rivafb_blank(FB_BLANK_NORMAL, info);
 684
 685        bpp = info->var.bits_per_pixel;
 686        if (bpp == 16 && info->var.green.length == 5)
 687                bpp = 15;
 688        width = info->var.xres_virtual;
 689        hDisplaySize = info->var.xres;
 690        hDisplay = (hDisplaySize / 8) - 1;
 691        hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
 692        hEnd = (hDisplaySize + info->var.right_margin +
 693                info->var.hsync_len) / 8 - 1;
 694        hTotal = (hDisplaySize + info->var.right_margin +
 695                  info->var.hsync_len + info->var.left_margin) / 8 - 5;
 696        hBlankStart = hDisplay;
 697        hBlankEnd = hTotal + 4;
 698
 699        height = info->var.yres_virtual;
 700        vDisplay = info->var.yres - 1;
 701        vStart = info->var.yres + info->var.lower_margin - 1;
 702        vEnd = info->var.yres + info->var.lower_margin +
 703               info->var.vsync_len - 1;
 704        vTotal = info->var.yres + info->var.lower_margin +
 705                 info->var.vsync_len + info->var.upper_margin + 2;
 706        vBlankStart = vDisplay;
 707        vBlankEnd = vTotal + 1;
 708        dotClock = 1000000000 / info->var.pixclock;
 709
 710        memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
 711
 712        if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
 713                vTotal |= 1;
 714
 715        if (par->FlatPanel) {
 716                vStart = vTotal - 3;
 717                vEnd = vTotal - 2;
 718                vBlankStart = vStart;
 719                hStart = hTotal - 3;
 720                hEnd = hTotal - 2;
 721                hBlankEnd = hTotal + 4;
 722        }
 723
 724        newmode.crtc[0x0] = Set8Bits (hTotal); 
 725        newmode.crtc[0x1] = Set8Bits (hDisplay);
 726        newmode.crtc[0x2] = Set8Bits (hBlankStart);
 727        newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
 728        newmode.crtc[0x4] = Set8Bits (hStart);
 729        newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
 730                | SetBitField (hEnd, 4: 0, 4:0);
 731        newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
 732        newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
 733                | SetBitField (vDisplay, 8: 8, 1:1)
 734                | SetBitField (vStart, 8: 8, 2:2)
 735                | SetBitField (vBlankStart, 8: 8, 3:3)
 736                | SetBit (4)
 737                | SetBitField (vTotal, 9: 9, 5:5)
 738                | SetBitField (vDisplay, 9: 9, 6:6)
 739                | SetBitField (vStart, 9: 9, 7:7);
 740        newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
 741                | SetBit (6);
 742        newmode.crtc[0x10] = Set8Bits (vStart);
 743        newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
 744                | SetBit (5);
 745        newmode.crtc[0x12] = Set8Bits (vDisplay);
 746        newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
 747        newmode.crtc[0x15] = Set8Bits (vBlankStart);
 748        newmode.crtc[0x16] = Set8Bits (vBlankEnd);
 749
 750        newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
 751                | SetBitField(vBlankStart,10:10,3:3)
 752                | SetBitField(vStart,10:10,2:2)
 753                | SetBitField(vDisplay,10:10,1:1)
 754                | SetBitField(vTotal,10:10,0:0);
 755        newmode.ext.horiz  = SetBitField(hTotal,8:8,0:0) 
 756                | SetBitField(hDisplay,8:8,1:1)
 757                | SetBitField(hBlankStart,8:8,2:2)
 758                | SetBitField(hStart,8:8,3:3);
 759        newmode.ext.extra  = SetBitField(vTotal,11:11,0:0)
 760                | SetBitField(vDisplay,11:11,2:2)
 761                | SetBitField(vStart,11:11,4:4)
 762                | SetBitField(vBlankStart,11:11,6:6); 
 763
 764        if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 765                int tmp = (hTotal >> 1) & ~1;
 766                newmode.ext.interlace = Set8Bits(tmp);
 767                newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
 768        } else 
 769                newmode.ext.interlace = 0xff; /* interlace off */
 770
 771        if (par->riva.Architecture >= NV_ARCH_10)
 772                par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
 773
 774        if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 775                newmode.misc_output &= ~0x40;
 776        else
 777                newmode.misc_output |= 0x40;
 778        if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 779                newmode.misc_output &= ~0x80;
 780        else
 781                newmode.misc_output |= 0x80;    
 782
 783        rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
 784                          hDisplaySize, height, dotClock);
 785        if (rc)
 786                goto out;
 787
 788        newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
 789                0xfff000ff;
 790        if (par->FlatPanel == 1) {
 791                newmode.ext.pixel |= (1 << 7);
 792                newmode.ext.scale |= (1 << 8);
 793        }
 794        if (par->SecondCRTC) {
 795                newmode.ext.head  = NV_RD32(par->riva.PCRTC0, 0x00000860) &
 796                        ~0x00001000;
 797                newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
 798                        0x00001000;
 799                newmode.ext.crtcOwner = 3;
 800                newmode.ext.pllsel |= 0x20000800;
 801                newmode.ext.vpll2 = newmode.ext.vpll;
 802        } else if (par->riva.twoHeads) {
 803                newmode.ext.head  =  NV_RD32(par->riva.PCRTC0, 0x00000860) |
 804                        0x00001000;
 805                newmode.ext.head2 =  NV_RD32(par->riva.PCRTC0, 0x00002860) &
 806                        ~0x00001000;
 807                newmode.ext.crtcOwner = 0;
 808                newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
 809        }
 810        if (par->FlatPanel == 1) {
 811                newmode.ext.pixel |= (1 << 7);
 812                newmode.ext.scale |= (1 << 8);
 813        }
 814        newmode.ext.cursorConfig = 0x02000100;
 815        par->current_state = newmode;
 816        riva_load_state(par, &par->current_state);
 817        par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
 818
 819out:
 820        rivafb_blank(FB_BLANK_UNBLANK, info);
 821        NVTRACE_LEAVE();
 822
 823        return rc;
 824}
 825
 826static void riva_update_var(struct fb_var_screeninfo *var,
 827                            const struct fb_videomode *modedb)
 828{
 829        NVTRACE_ENTER();
 830        var->xres = var->xres_virtual = modedb->xres;
 831        var->yres = modedb->yres;
 832        if (var->yres_virtual < var->yres)
 833            var->yres_virtual = var->yres;
 834        var->xoffset = var->yoffset = 0;
 835        var->pixclock = modedb->pixclock;
 836        var->left_margin = modedb->left_margin;
 837        var->right_margin = modedb->right_margin;
 838        var->upper_margin = modedb->upper_margin;
 839        var->lower_margin = modedb->lower_margin;
 840        var->hsync_len = modedb->hsync_len;
 841        var->vsync_len = modedb->vsync_len;
 842        var->sync = modedb->sync;
 843        var->vmode = modedb->vmode;
 844        NVTRACE_LEAVE();
 845}
 846
 847/**
 848 * rivafb_do_maximize - 
 849 * @info: pointer to fb_info object containing info for current riva board
 850 * @var:
 851 * @nom:
 852 * @den:
 853 *
 854 * DESCRIPTION:
 855 * .
 856 *
 857 * RETURNS:
 858 * -EINVAL on failure, 0 on success
 859 * 
 860 *
 861 * CALLED FROM:
 862 * rivafb_check_var()
 863 */
 864static int rivafb_do_maximize(struct fb_info *info,
 865                              struct fb_var_screeninfo *var,
 866                              int nom, int den)
 867{
 868        static struct {
 869                int xres, yres;
 870        } modes[] = {
 871                {1600, 1280},
 872                {1280, 1024},
 873                {1024, 768},
 874                {800, 600},
 875                {640, 480},
 876                {-1, -1}
 877        };
 878        int i;
 879
 880        NVTRACE_ENTER();
 881        /* use highest possible virtual resolution */
 882        if (var->xres_virtual == -1 && var->yres_virtual == -1) {
 883                printk(KERN_WARNING PFX
 884                       "using maximum available virtual resolution\n");
 885                for (i = 0; modes[i].xres != -1; i++) {
 886                        if (modes[i].xres * nom / den * modes[i].yres <
 887                            info->fix.smem_len)
 888                                break;
 889                }
 890                if (modes[i].xres == -1) {
 891                        printk(KERN_ERR PFX
 892                               "could not find a virtual resolution that fits into video memory!!\n");
 893                        NVTRACE("EXIT - EINVAL error\n");
 894                        return -EINVAL;
 895                }
 896                var->xres_virtual = modes[i].xres;
 897                var->yres_virtual = modes[i].yres;
 898
 899                printk(KERN_INFO PFX
 900                       "virtual resolution set to maximum of %dx%d\n",
 901                       var->xres_virtual, var->yres_virtual);
 902        } else if (var->xres_virtual == -1) {
 903                var->xres_virtual = (info->fix.smem_len * den /
 904                        (nom * var->yres_virtual)) & ~15;
 905                printk(KERN_WARNING PFX
 906                       "setting virtual X resolution to %d\n", var->xres_virtual);
 907        } else if (var->yres_virtual == -1) {
 908                var->xres_virtual = (var->xres_virtual + 15) & ~15;
 909                var->yres_virtual = info->fix.smem_len * den /
 910                        (nom * var->xres_virtual);
 911                printk(KERN_WARNING PFX
 912                       "setting virtual Y resolution to %d\n", var->yres_virtual);
 913        } else {
 914                var->xres_virtual = (var->xres_virtual + 15) & ~15;
 915                if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
 916                        printk(KERN_ERR PFX
 917                               "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
 918                               var->xres, var->yres, var->bits_per_pixel);
 919                        NVTRACE("EXIT - EINVAL error\n");
 920                        return -EINVAL;
 921                }
 922        }
 923        
 924        if (var->xres_virtual * nom / den >= 8192) {
 925                printk(KERN_WARNING PFX
 926                       "virtual X resolution (%d) is too high, lowering to %d\n",
 927                       var->xres_virtual, 8192 * den / nom - 16);
 928                var->xres_virtual = 8192 * den / nom - 16;
 929        }
 930        
 931        if (var->xres_virtual < var->xres) {
 932                printk(KERN_ERR PFX
 933                       "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
 934                return -EINVAL;
 935        }
 936
 937        if (var->yres_virtual < var->yres) {
 938                printk(KERN_ERR PFX
 939                       "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
 940                return -EINVAL;
 941        }
 942        if (var->yres_virtual > 0x7fff/nom)
 943                var->yres_virtual = 0x7fff/nom;
 944        if (var->xres_virtual > 0x7fff/nom)
 945                var->xres_virtual = 0x7fff/nom;
 946        NVTRACE_LEAVE();
 947        return 0;
 948}
 949
 950static void
 951riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
 952{
 953        RIVA_FIFO_FREE(par->riva, Patt, 4);
 954        NV_WR32(&par->riva.Patt->Color0, 0, clr0);
 955        NV_WR32(&par->riva.Patt->Color1, 0, clr1);
 956        NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
 957        NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
 958}
 959
 960/* acceleration routines */
 961static inline void wait_for_idle(struct riva_par *par)
 962{
 963        while (par->riva.Busy(&par->riva));
 964}
 965
 966/*
 967 * Set ROP.  Translate X rop into ROP3.  Internal routine.
 968 */
 969static void
 970riva_set_rop_solid(struct riva_par *par, int rop)
 971{
 972        riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 973        RIVA_FIFO_FREE(par->riva, Rop, 1);
 974        NV_WR32(&par->riva.Rop->Rop3, 0, rop);
 975
 976}
 977
 978static void riva_setup_accel(struct fb_info *info)
 979{
 980        struct riva_par *par = info->par;
 981
 982        RIVA_FIFO_FREE(par->riva, Clip, 2);
 983        NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
 984        NV_WR32(&par->riva.Clip->WidthHeight, 0,
 985                (info->var.xres_virtual & 0xffff) |
 986                (info->var.yres_virtual << 16));
 987        riva_set_rop_solid(par, 0xcc);
 988        wait_for_idle(par);
 989}
 990
 991/**
 992 * riva_get_cmap_len - query current color map length
 993 * @var: standard kernel fb changeable data
 994 *
 995 * DESCRIPTION:
 996 * Get current color map length.
 997 *
 998 * RETURNS:
 999 * Length of color map
1000 *
1001 * CALLED FROM:
1002 * rivafb_setcolreg()
1003 */
1004static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1005{
1006        int rc = 256;           /* reasonable default */
1007
1008        switch (var->green.length) {
1009        case 8:
1010                rc = 256;       /* 256 entries (2^8), 8 bpp and RGB8888 */
1011                break;
1012        case 5:
1013                rc = 32;        /* 32 entries (2^5), 16 bpp, RGB555 */
1014                break;
1015        case 6:
1016                rc = 64;        /* 64 entries (2^6), 16 bpp, RGB565 */
1017                break;          
1018        default:
1019                /* should not occur */
1020                break;
1021        }
1022        return rc;
1023}
1024
1025/* ------------------------------------------------------------------------- *
1026 *
1027 * framebuffer operations
1028 *
1029 * ------------------------------------------------------------------------- */
1030
1031static int rivafb_open(struct fb_info *info, int user)
1032{
1033        struct riva_par *par = info->par;
1034
1035        NVTRACE_ENTER();
1036        mutex_lock(&par->open_lock);
1037        if (!par->ref_count) {
1038#ifdef CONFIG_X86
1039                memset(&par->state, 0, sizeof(struct vgastate));
1040                par->state.flags = VGA_SAVE_MODE  | VGA_SAVE_FONTS;
1041                /* save the DAC for Riva128 */
1042                if (par->riva.Architecture == NV_ARCH_03)
1043                        par->state.flags |= VGA_SAVE_CMAP;
1044                save_vga(&par->state);
1045#endif
1046                /* vgaHWunlock() + riva unlock (0x7F) */
1047                CRTCout(par, 0x11, 0xFF);
1048                par->riva.LockUnlock(&par->riva, 0);
1049        
1050                riva_save_state(par, &par->initial_state);
1051        }
1052        par->ref_count++;
1053        mutex_unlock(&par->open_lock);
1054        NVTRACE_LEAVE();
1055        return 0;
1056}
1057
1058static int rivafb_release(struct fb_info *info, int user)
1059{
1060        struct riva_par *par = info->par;
1061
1062        NVTRACE_ENTER();
1063        mutex_lock(&par->open_lock);
1064        if (!par->ref_count) {
1065                mutex_unlock(&par->open_lock);
1066                return -EINVAL;
1067        }
1068        if (par->ref_count == 1) {
1069                par->riva.LockUnlock(&par->riva, 0);
1070                par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1071                riva_load_state(par, &par->initial_state);
1072#ifdef CONFIG_X86
1073                restore_vga(&par->state);
1074#endif
1075                par->riva.LockUnlock(&par->riva, 1);
1076        }
1077        par->ref_count--;
1078        mutex_unlock(&par->open_lock);
1079        NVTRACE_LEAVE();
1080        return 0;
1081}
1082
1083static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1084{
1085        const struct fb_videomode *mode;
1086        struct riva_par *par = info->par;
1087        int nom, den;           /* translating from pixels->bytes */
1088        int mode_valid = 0;
1089        
1090        NVTRACE_ENTER();
1091        switch (var->bits_per_pixel) {
1092        case 1 ... 8:
1093                var->red.offset = var->green.offset = var->blue.offset = 0;
1094                var->red.length = var->green.length = var->blue.length = 8;
1095                var->bits_per_pixel = 8;
1096                nom = den = 1;
1097                break;
1098        case 9 ... 15:
1099                var->green.length = 5;
1100                /* fall through */
1101        case 16:
1102                var->bits_per_pixel = 16;
1103                /* The Riva128 supports RGB555 only */
1104                if (par->riva.Architecture == NV_ARCH_03)
1105                        var->green.length = 5;
1106                if (var->green.length == 5) {
1107                        /* 0rrrrrgg gggbbbbb */
1108                        var->red.offset = 10;
1109                        var->green.offset = 5;
1110                        var->blue.offset = 0;
1111                        var->red.length = 5;
1112                        var->green.length = 5;
1113                        var->blue.length = 5;
1114                } else {
1115                        /* rrrrrggg gggbbbbb */
1116                        var->red.offset = 11;
1117                        var->green.offset = 5;
1118                        var->blue.offset = 0;
1119                        var->red.length = 5;
1120                        var->green.length = 6;
1121                        var->blue.length = 5;
1122                }
1123                nom = 2;
1124                den = 1;
1125                break;
1126        case 17 ... 32:
1127                var->red.length = var->green.length = var->blue.length = 8;
1128                var->bits_per_pixel = 32;
1129                var->red.offset = 16;
1130                var->green.offset = 8;
1131                var->blue.offset = 0;
1132                nom = 4;
1133                den = 1;
1134                break;
1135        default:
1136                printk(KERN_ERR PFX
1137                       "mode %dx%dx%d rejected...color depth not supported.\n",
1138                       var->xres, var->yres, var->bits_per_pixel);
1139                NVTRACE("EXIT, returning -EINVAL\n");
1140                return -EINVAL;
1141        }
1142
1143        if (!strictmode) {
1144                if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1145                    !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1146                        mode_valid = 1;
1147        }
1148
1149        /* calculate modeline if supported by monitor */
1150        if (!mode_valid && info->monspecs.gtf) {
1151                if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1152                        mode_valid = 1;
1153        }
1154
1155        if (!mode_valid) {
1156                mode = fb_find_best_mode(var, &info->modelist);
1157                if (mode) {
1158                        riva_update_var(var, mode);
1159                        mode_valid = 1;
1160                }
1161        }
1162
1163        if (!mode_valid && info->monspecs.modedb_len)
1164                return -EINVAL;
1165
1166        if (var->xres_virtual < var->xres)
1167                var->xres_virtual = var->xres;
1168        if (var->yres_virtual <= var->yres)
1169                var->yres_virtual = -1;
1170        if (rivafb_do_maximize(info, var, nom, den) < 0)
1171                return -EINVAL;
1172
1173        /* truncate xoffset and yoffset to maximum if too high */
1174        if (var->xoffset > var->xres_virtual - var->xres)
1175                var->xoffset = var->xres_virtual - var->xres - 1;
1176
1177        if (var->yoffset > var->yres_virtual - var->yres)
1178                var->yoffset = var->yres_virtual - var->yres - 1;
1179
1180        var->red.msb_right = 
1181            var->green.msb_right =
1182            var->blue.msb_right =
1183            var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1184        NVTRACE_LEAVE();
1185        return 0;
1186}
1187
1188static int rivafb_set_par(struct fb_info *info)
1189{
1190        struct riva_par *par = info->par;
1191        int rc = 0;
1192
1193        NVTRACE_ENTER();
1194        /* vgaHWunlock() + riva unlock (0x7F) */
1195        CRTCout(par, 0x11, 0xFF);
1196        par->riva.LockUnlock(&par->riva, 0);
1197        rc = riva_load_video_mode(info);
1198        if (rc)
1199                goto out;
1200        if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1201                riva_setup_accel(info);
1202        
1203        par->cursor_reset = 1;
1204        info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1205        info->fix.visual = (info->var.bits_per_pixel == 8) ?
1206                                FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1207
1208        if (info->flags & FBINFO_HWACCEL_DISABLED)
1209                info->pixmap.scan_align = 1;
1210        else
1211                info->pixmap.scan_align = 4;
1212
1213out:
1214        NVTRACE_LEAVE();
1215        return rc;
1216}
1217
1218/**
1219 * rivafb_pan_display
1220 * @var: standard kernel fb changeable data
1221 * @con: TODO
1222 * @info: pointer to fb_info object containing info for current riva board
1223 *
1224 * DESCRIPTION:
1225 * Pan (or wrap, depending on the `vmode' field) the display using the
1226 * `xoffset' and `yoffset' fields of the `var' structure.
1227 * If the values don't fit, return -EINVAL.
1228 *
1229 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1230 */
1231static int rivafb_pan_display(struct fb_var_screeninfo *var,
1232                              struct fb_info *info)
1233{
1234        struct riva_par *par = info->par;
1235        unsigned int base;
1236
1237        NVTRACE_ENTER();
1238        base = var->yoffset * info->fix.line_length + var->xoffset;
1239        par->riva.SetStartAddress(&par->riva, base);
1240        NVTRACE_LEAVE();
1241        return 0;
1242}
1243
1244static int rivafb_blank(int blank, struct fb_info *info)
1245{
1246        struct riva_par *par= info->par;
1247        unsigned char tmp, vesa;
1248
1249        tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1250        vesa = CRTCin(par, 0x1a) & ~0xc0;       /* sync on/off */
1251
1252        NVTRACE_ENTER();
1253
1254        if (blank)
1255                tmp |= 0x20;
1256
1257        switch (blank) {
1258        case FB_BLANK_UNBLANK:
1259        case FB_BLANK_NORMAL:
1260                break;
1261        case FB_BLANK_VSYNC_SUSPEND:
1262                vesa |= 0x80;
1263                break;
1264        case FB_BLANK_HSYNC_SUSPEND:
1265                vesa |= 0x40;
1266                break;
1267        case FB_BLANK_POWERDOWN:
1268                vesa |= 0xc0;
1269                break;
1270        }
1271
1272        SEQout(par, 0x01, tmp);
1273        CRTCout(par, 0x1a, vesa);
1274
1275        NVTRACE_LEAVE();
1276
1277        return 0;
1278}
1279
1280/**
1281 * rivafb_setcolreg
1282 * @regno: register index
1283 * @red: red component
1284 * @green: green component
1285 * @blue: blue component
1286 * @transp: transparency
1287 * @info: pointer to fb_info object containing info for current riva board
1288 *
1289 * DESCRIPTION:
1290 * Set a single color register. The values supplied have a 16 bit
1291 * magnitude.
1292 *
1293 * RETURNS:
1294 * Return != 0 for invalid regno.
1295 *
1296 * CALLED FROM:
1297 * fbcmap.c:fb_set_cmap()
1298 */
1299static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1300                          unsigned blue, unsigned transp,
1301                          struct fb_info *info)
1302{
1303        struct riva_par *par = info->par;
1304        RIVA_HW_INST *chip = &par->riva;
1305        int i;
1306
1307        if (regno >= riva_get_cmap_len(&info->var))
1308                        return -EINVAL;
1309
1310        if (info->var.grayscale) {
1311                /* gray = 0.30*R + 0.59*G + 0.11*B */
1312                red = green = blue =
1313                    (red * 77 + green * 151 + blue * 28) >> 8;
1314        }
1315
1316        if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1317                ((u32 *) info->pseudo_palette)[regno] =
1318                        (regno << info->var.red.offset) |
1319                        (regno << info->var.green.offset) |
1320                        (regno << info->var.blue.offset);
1321                /*
1322                 * The Riva128 2D engine requires color information in
1323                 * TrueColor format even if framebuffer is in DirectColor
1324                 */
1325                if (par->riva.Architecture == NV_ARCH_03) {
1326                        switch (info->var.bits_per_pixel) {
1327                        case 16:
1328                                par->palette[regno] = ((red & 0xf800) >> 1) |
1329                                        ((green & 0xf800) >> 6) |
1330                                        ((blue & 0xf800) >> 11);
1331                                break;
1332                        case 32:
1333                                par->palette[regno] = ((red & 0xff00) << 8) |
1334                                        ((green & 0xff00)) |
1335                                        ((blue & 0xff00) >> 8);
1336                                break;
1337                        }
1338                }
1339        }
1340
1341        switch (info->var.bits_per_pixel) {
1342        case 8:
1343                /* "transparent" stuff is completely ignored. */
1344                riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1345                break;
1346        case 16:
1347                if (info->var.green.length == 5) {
1348                        for (i = 0; i < 8; i++) {
1349                                riva_wclut(chip, regno*8+i, red >> 8,
1350                                           green >> 8, blue >> 8);
1351                        }
1352                } else {
1353                        u8 r, g, b;
1354
1355                        if (regno < 32) {
1356                                for (i = 0; i < 8; i++) {
1357                                        riva_wclut(chip, regno*8+i,
1358                                                   red >> 8, green >> 8,
1359                                                   blue >> 8);
1360                                }
1361                        }
1362                        riva_rclut(chip, regno*4, &r, &g, &b);
1363                        for (i = 0; i < 4; i++)
1364                                riva_wclut(chip, regno*4+i, r,
1365                                           green >> 8, b);
1366                }
1367                break;
1368        case 32:
1369                riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1370                break;
1371        default:
1372                /* do nothing */
1373                break;
1374        }
1375        return 0;
1376}
1377
1378/**
1379 * rivafb_fillrect - hardware accelerated color fill function
1380 * @info: pointer to fb_info structure
1381 * @rect: pointer to fb_fillrect structure
1382 *
1383 * DESCRIPTION:
1384 * This function fills up a region of framebuffer memory with a solid
1385 * color with a choice of two different ROP's, copy or invert.
1386 *
1387 * CALLED FROM:
1388 * framebuffer hook
1389 */
1390static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1391{
1392        struct riva_par *par = info->par;
1393        u_int color, rop = 0;
1394
1395        if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1396                cfb_fillrect(info, rect);
1397                return;
1398        }
1399
1400        if (info->var.bits_per_pixel == 8)
1401                color = rect->color;
1402        else {
1403                if (par->riva.Architecture != NV_ARCH_03)
1404                        color = ((u32 *)info->pseudo_palette)[rect->color];
1405                else
1406                        color = par->palette[rect->color];
1407        }
1408
1409        switch (rect->rop) {
1410        case ROP_XOR:
1411                rop = 0x66;
1412                break;
1413        case ROP_COPY:
1414        default:
1415                rop = 0xCC;
1416                break;
1417        }
1418
1419        riva_set_rop_solid(par, rop);
1420
1421        RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1422        NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1423
1424        RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1425        NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1426                (rect->dx << 16) | rect->dy);
1427        mb();
1428        NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1429                (rect->width << 16) | rect->height);
1430        mb();
1431        riva_set_rop_solid(par, 0xcc);
1432
1433}
1434
1435/**
1436 * rivafb_copyarea - hardware accelerated blit function
1437 * @info: pointer to fb_info structure
1438 * @region: pointer to fb_copyarea structure
1439 *
1440 * DESCRIPTION:
1441 * This copies an area of pixels from one location to another
1442 *
1443 * CALLED FROM:
1444 * framebuffer hook
1445 */
1446static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1447{
1448        struct riva_par *par = info->par;
1449
1450        if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1451                cfb_copyarea(info, region);
1452                return;
1453        }
1454
1455        RIVA_FIFO_FREE(par->riva, Blt, 3);
1456        NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1457                (region->sy << 16) | region->sx);
1458        NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1459                (region->dy << 16) | region->dx);
1460        mb();
1461        NV_WR32(&par->riva.Blt->WidthHeight, 0,
1462                (region->height << 16) | region->width);
1463        mb();
1464}
1465
1466static inline void convert_bgcolor_16(u32 *col)
1467{
1468        *col = ((*col & 0x0000F800) << 8)
1469                | ((*col & 0x00007E0) << 5)
1470                | ((*col & 0x0000001F) << 3)
1471                |          0xFF000000;
1472        mb();
1473}
1474
1475/**
1476 * rivafb_imageblit: hardware accelerated color expand function
1477 * @info: pointer to fb_info structure
1478 * @image: pointer to fb_image structure
1479 *
1480 * DESCRIPTION:
1481 * If the source is a monochrome bitmap, the function fills up a a region
1482 * of framebuffer memory with pixels whose color is determined by the bit
1483 * setting of the bitmap, 1 - foreground, 0 - background.
1484 *
1485 * If the source is not a monochrome bitmap, color expansion is not done.
1486 * In this case, it is channeled to a software function.
1487 *
1488 * CALLED FROM:
1489 * framebuffer hook
1490 */
1491static void rivafb_imageblit(struct fb_info *info, 
1492                             const struct fb_image *image)
1493{
1494        struct riva_par *par = info->par;
1495        u32 fgx = 0, bgx = 0, width, tmp;
1496        u8 *cdat = (u8 *) image->data;
1497        volatile u32 __iomem *d;
1498        int i, size;
1499
1500        if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1501                cfb_imageblit(info, image);
1502                return;
1503        }
1504
1505        switch (info->var.bits_per_pixel) {
1506        case 8:
1507                fgx = image->fg_color;
1508                bgx = image->bg_color;
1509                break;
1510        case 16:
1511        case 32:
1512                if (par->riva.Architecture != NV_ARCH_03) {
1513                        fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1514                        bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1515                } else {
1516                        fgx = par->palette[image->fg_color];
1517                        bgx = par->palette[image->bg_color];
1518                }
1519                if (info->var.green.length == 6)
1520                        convert_bgcolor_16(&bgx);       
1521                break;
1522        }
1523
1524        RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1525        NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1526                (image->dy << 16) | (image->dx & 0xFFFF));
1527        NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1528                (((image->dy + image->height) << 16) |
1529                 ((image->dx + image->width) & 0xffff)));
1530        NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1531        NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1532        NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1533                (image->height << 16) | ((image->width + 31) & ~31));
1534        NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1535                (image->height << 16) | ((image->width + 31) & ~31));
1536        NV_WR32(&par->riva.Bitmap->PointE, 0,
1537                (image->dy << 16) | (image->dx & 0xFFFF));
1538
1539        d = &par->riva.Bitmap->MonochromeData01E;
1540
1541        width = (image->width + 31)/32;
1542        size = width * image->height;
1543        while (size >= 16) {
1544                RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1545                for (i = 0; i < 16; i++) {
1546                        tmp = *((u32 *)cdat);
1547                        cdat = (u8 *)((u32 *)cdat + 1);
1548                        reverse_order(&tmp);
1549                        NV_WR32(d, i*4, tmp);
1550                }
1551                size -= 16;
1552        }
1553        if (size) {
1554                RIVA_FIFO_FREE(par->riva, Bitmap, size);
1555                for (i = 0; i < size; i++) {
1556                        tmp = *((u32 *) cdat);
1557                        cdat = (u8 *)((u32 *)cdat + 1);
1558                        reverse_order(&tmp);
1559                        NV_WR32(d, i*4, tmp);
1560                }
1561        }
1562}
1563
1564/**
1565 * rivafb_cursor - hardware cursor function
1566 * @info: pointer to info structure
1567 * @cursor: pointer to fbcursor structure
1568 *
1569 * DESCRIPTION:
1570 * A cursor function that supports displaying a cursor image via hardware.
1571 * Within the kernel, copy and invert rops are supported.  If exported
1572 * to user space, only the copy rop will be supported.
1573 *
1574 * CALLED FROM
1575 * framebuffer hook
1576 */
1577static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1578{
1579        struct riva_par *par = info->par;
1580        u8 data[MAX_CURS * MAX_CURS/8];
1581        int i, set = cursor->set;
1582        u16 fg, bg;
1583
1584        if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1585                return -ENXIO;
1586
1587        par->riva.ShowHideCursor(&par->riva, 0);
1588
1589        if (par->cursor_reset) {
1590                set = FB_CUR_SETALL;
1591                par->cursor_reset = 0;
1592        }
1593
1594        if (set & FB_CUR_SETSIZE)
1595                memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1596
1597        if (set & FB_CUR_SETPOS) {
1598                u32 xx, yy, temp;
1599
1600                yy = cursor->image.dy - info->var.yoffset;
1601                xx = cursor->image.dx - info->var.xoffset;
1602                temp = xx & 0xFFFF;
1603                temp |= yy << 16;
1604
1605                NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1606        }
1607
1608
1609        if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1610                u32 bg_idx = cursor->image.bg_color;
1611                u32 fg_idx = cursor->image.fg_color;
1612                u32 s_pitch = (cursor->image.width+7) >> 3;
1613                u32 d_pitch = MAX_CURS/8;
1614                u8 *dat = (u8 *) cursor->image.data;
1615                u8 *msk = (u8 *) cursor->mask;
1616                u8 *src;
1617                
1618                src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
1619
1620                if (src) {
1621                        switch (cursor->rop) {
1622                        case ROP_XOR:
1623                                for (i = 0; i < s_pitch * cursor->image.height; i++)
1624                                        src[i] = dat[i] ^ msk[i];
1625                                break;
1626                        case ROP_COPY:
1627                        default:
1628                                for (i = 0; i < s_pitch * cursor->image.height; i++)
1629                                        src[i] = dat[i] & msk[i];
1630                                break;
1631                        }
1632
1633                        fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1634                                                cursor->image.height);
1635
1636                        bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1637                                ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1638                                ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1639                                1 << 15;
1640
1641                        fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1642                                ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1643                                ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1644                                1 << 15;
1645
1646                        par->riva.LockUnlock(&par->riva, 0);
1647
1648                        rivafb_load_cursor_image(par, data, bg, fg,
1649                                                 cursor->image.width,
1650                                                 cursor->image.height);
1651                        kfree(src);
1652                }
1653        }
1654
1655        if (cursor->enable)
1656                par->riva.ShowHideCursor(&par->riva, 1);
1657
1658        return 0;
1659}
1660
1661static int rivafb_sync(struct fb_info *info)
1662{
1663        struct riva_par *par = info->par;
1664
1665        wait_for_idle(par);
1666        return 0;
1667}
1668
1669/* ------------------------------------------------------------------------- *
1670 *
1671 * initialization helper functions
1672 *
1673 * ------------------------------------------------------------------------- */
1674
1675/* kernel interface */
1676static struct fb_ops riva_fb_ops = {
1677        .owner          = THIS_MODULE,
1678        .fb_open        = rivafb_open,
1679        .fb_release     = rivafb_release,
1680        .fb_check_var   = rivafb_check_var,
1681        .fb_set_par     = rivafb_set_par,
1682        .fb_setcolreg   = rivafb_setcolreg,
1683        .fb_pan_display = rivafb_pan_display,
1684        .fb_blank       = rivafb_blank,
1685        .fb_fillrect    = rivafb_fillrect,
1686        .fb_copyarea    = rivafb_copyarea,
1687        .fb_imageblit   = rivafb_imageblit,
1688        .fb_cursor      = rivafb_cursor,        
1689        .fb_sync        = rivafb_sync,
1690};
1691
1692static int riva_set_fbinfo(struct fb_info *info)
1693{
1694        unsigned int cmap_len;
1695        struct riva_par *par = info->par;
1696
1697        NVTRACE_ENTER();
1698        info->flags = FBINFO_DEFAULT
1699                    | FBINFO_HWACCEL_XPAN
1700                    | FBINFO_HWACCEL_YPAN
1701                    | FBINFO_HWACCEL_COPYAREA
1702                    | FBINFO_HWACCEL_FILLRECT
1703                    | FBINFO_HWACCEL_IMAGEBLIT;
1704
1705        /* Accel seems to not work properly on NV30 yet...*/
1706        if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1707                printk(KERN_DEBUG PFX "disabling acceleration\n");
1708                info->flags |= FBINFO_HWACCEL_DISABLED;
1709        }
1710
1711        info->var = rivafb_default_var;
1712        info->fix.visual = (info->var.bits_per_pixel == 8) ?
1713                                FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1714
1715        info->pseudo_palette = par->pseudo_palette;
1716
1717        cmap_len = riva_get_cmap_len(&info->var);
1718        fb_alloc_cmap(&info->cmap, cmap_len, 0);        
1719
1720        info->pixmap.size = 8 * 1024;
1721        info->pixmap.buf_align = 4;
1722        info->pixmap.access_align = 32;
1723        info->pixmap.flags = FB_PIXMAP_SYSTEM;
1724        info->var.yres_virtual = -1;
1725        NVTRACE_LEAVE();
1726        return (rivafb_check_var(&info->var, info));
1727}
1728
1729static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1730{
1731        struct riva_par *par = info->par;
1732        struct device_node *dp;
1733        const unsigned char *pedid = NULL;
1734        const unsigned char *disptype = NULL;
1735        static char *propnames[] = {
1736                "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1737        int i;
1738
1739        NVTRACE_ENTER();
1740        dp = pci_device_to_OF_node(pd);
1741        for (; dp != NULL; dp = dp->child) {
1742                disptype = of_get_property(dp, "display-type", NULL);
1743                if (disptype == NULL)
1744                        continue;
1745                if (strncmp(disptype, "LCD", 3) != 0)
1746                        continue;
1747                for (i = 0; propnames[i] != NULL; ++i) {
1748                        pedid = of_get_property(dp, propnames[i], NULL);
1749                        if (pedid != NULL) {
1750                                par->EDID = (unsigned char *)pedid;
1751                                NVTRACE("LCD found.\n");
1752                                return 1;
1753                        }
1754                }
1755        }
1756        NVTRACE_LEAVE();
1757        return 0;
1758}
1759
1760#if defined(CONFIG_FB_RIVA_I2C)
1761static int riva_get_EDID_i2c(struct fb_info *info)
1762{
1763        struct riva_par *par = info->par;
1764        struct fb_var_screeninfo var;
1765        int i;
1766
1767        NVTRACE_ENTER();
1768        par->riva.LockUnlock(&par->riva, 0);
1769        riva_create_i2c_busses(par);
1770        for (i = 0; i < 3; i++) {
1771                if (!par->chan[i].par)
1772                        continue;
1773                riva_probe_i2c_connector(par, i, &par->EDID);
1774                if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1775                        printk(PFX "Found EDID Block from BUS %i\n", i);
1776                        break;
1777                }
1778        }
1779
1780        NVTRACE_LEAVE();
1781        return (par->EDID) ? 1 : 0;
1782}
1783#endif /* CONFIG_FB_RIVA_I2C */
1784
1785static void riva_update_default_var(struct fb_var_screeninfo *var,
1786                                    struct fb_info *info)
1787{
1788        struct fb_monspecs *specs = &info->monspecs;
1789        struct fb_videomode modedb;
1790
1791        NVTRACE_ENTER();
1792        /* respect mode options */
1793        if (mode_option) {
1794                fb_find_mode(var, info, mode_option,
1795                             specs->modedb, specs->modedb_len,
1796                             NULL, 8);
1797        } else if (specs->modedb != NULL) {
1798                /* get first mode in database as fallback */
1799                modedb = specs->modedb[0];
1800                /* get preferred timing */
1801                if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1802                        int i;
1803
1804                        for (i = 0; i < specs->modedb_len; i++) {
1805                                if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1806                                        modedb = specs->modedb[i];
1807                                        break;
1808                                }
1809                        }
1810                }
1811                var->bits_per_pixel = 8;
1812                riva_update_var(var, &modedb);
1813        }
1814        NVTRACE_LEAVE();
1815}
1816
1817
1818static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1819{
1820        NVTRACE_ENTER();
1821        if (riva_get_EDID_OF(info, pdev)) {
1822                NVTRACE_LEAVE();
1823                return;
1824        }
1825        if (IS_ENABLED(CONFIG_OF))
1826                printk(PFX "could not retrieve EDID from OF\n");
1827#if defined(CONFIG_FB_RIVA_I2C)
1828        if (!riva_get_EDID_i2c(info))
1829                printk(PFX "could not retrieve EDID from DDC/I2C\n");
1830#endif
1831        NVTRACE_LEAVE();
1832}
1833
1834
1835static void riva_get_edidinfo(struct fb_info *info)
1836{
1837        struct fb_var_screeninfo *var = &rivafb_default_var;
1838        struct riva_par *par = info->par;
1839
1840        fb_edid_to_monspecs(par->EDID, &info->monspecs);
1841        fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1842                                 &info->modelist);
1843        riva_update_default_var(var, info);
1844
1845        /* if user specified flatpanel, we respect that */
1846        if (info->monspecs.input & FB_DISP_DDI)
1847                par->FlatPanel = 1;
1848}
1849
1850/* ------------------------------------------------------------------------- *
1851 *
1852 * PCI bus
1853 *
1854 * ------------------------------------------------------------------------- */
1855
1856static u32 riva_get_arch(struct pci_dev *pd)
1857{
1858        u32 arch = 0;
1859
1860        switch (pd->device & 0x0ff0) {
1861                case 0x0100:   /* GeForce 256 */
1862                case 0x0110:   /* GeForce2 MX */
1863                case 0x0150:   /* GeForce2 */
1864                case 0x0170:   /* GeForce4 MX */
1865                case 0x0180:   /* GeForce4 MX (8x AGP) */
1866                case 0x01A0:   /* nForce */
1867                case 0x01F0:   /* nForce2 */
1868                     arch =  NV_ARCH_10;
1869                     break;
1870                case 0x0200:   /* GeForce3 */
1871                case 0x0250:   /* GeForce4 Ti */
1872                case 0x0280:   /* GeForce4 Ti (8x AGP) */
1873                     arch =  NV_ARCH_20;
1874                     break;
1875                case 0x0300:   /* GeForceFX 5800 */
1876                case 0x0310:   /* GeForceFX 5600 */
1877                case 0x0320:   /* GeForceFX 5200 */
1878                case 0x0330:   /* GeForceFX 5900 */
1879                case 0x0340:   /* GeForceFX 5700 */
1880                     arch =  NV_ARCH_30;
1881                     break;
1882                case 0x0020:   /* TNT, TNT2 */
1883                     arch =  NV_ARCH_04;
1884                     break;
1885                case 0x0010:   /* Riva128 */
1886                     arch =  NV_ARCH_03;
1887                     break;
1888                default:   /* unknown architecture */
1889                     break;
1890        }
1891        return arch;
1892}
1893
1894static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1895{
1896        struct riva_par *default_par;
1897        struct fb_info *info;
1898        int ret;
1899
1900        NVTRACE_ENTER();
1901        assert(pd != NULL);
1902
1903        info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1904        if (!info) {
1905                printk (KERN_ERR PFX "could not allocate memory\n");
1906                ret = -ENOMEM;
1907                goto err_ret;
1908        }
1909        default_par = info->par;
1910        default_par->pdev = pd;
1911
1912        info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1913        if (info->pixmap.addr == NULL) {
1914                ret = -ENOMEM;
1915                goto err_framebuffer_release;
1916        }
1917
1918        ret = pci_enable_device(pd);
1919        if (ret < 0) {
1920                printk(KERN_ERR PFX "cannot enable PCI device\n");
1921                goto err_free_pixmap;
1922        }
1923
1924        ret = pci_request_regions(pd, "rivafb");
1925        if (ret < 0) {
1926                printk(KERN_ERR PFX "cannot request PCI regions\n");
1927                goto err_disable_device;
1928        }
1929
1930        mutex_init(&default_par->open_lock);
1931        default_par->riva.Architecture = riva_get_arch(pd);
1932
1933        default_par->Chipset = (pd->vendor << 16) | pd->device;
1934        printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1935        
1936        if(default_par->riva.Architecture == 0) {
1937                printk(KERN_ERR PFX "unknown NV_ARCH\n");
1938                ret=-ENODEV;
1939                goto err_release_region;
1940        }
1941        if(default_par->riva.Architecture == NV_ARCH_10 ||
1942           default_par->riva.Architecture == NV_ARCH_20 ||
1943           default_par->riva.Architecture == NV_ARCH_30) {
1944                sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1945        } else {
1946                sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1947        }
1948
1949        default_par->FlatPanel = flatpanel;
1950        if (flatpanel == 1)
1951                printk(KERN_INFO PFX "flatpanel support enabled\n");
1952        default_par->forceCRTC = forceCRTC;
1953        
1954        rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1955        rivafb_fix.smem_len = pci_resource_len(pd, 1);
1956
1957        {
1958                /* enable IO and mem if not already done */
1959                unsigned short cmd;
1960
1961                pci_read_config_word(pd, PCI_COMMAND, &cmd);
1962                cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1963                pci_write_config_word(pd, PCI_COMMAND, cmd);
1964        }
1965        
1966        rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1967        rivafb_fix.smem_start = pci_resource_start(pd, 1);
1968
1969        default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1970                                         rivafb_fix.mmio_len);
1971        if (!default_par->ctrl_base) {
1972                printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1973                ret = -EIO;
1974                goto err_release_region;
1975        }
1976
1977        switch (default_par->riva.Architecture) {
1978        case NV_ARCH_03:
1979                /* Riva128's PRAMIN is in the "framebuffer" space
1980                 * Since these cards were never made with more than 8 megabytes
1981                 * we can safely allocate this separately.
1982                 */
1983                default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1984                if (!default_par->riva.PRAMIN) {
1985                        printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1986                        ret = -EIO;
1987                        goto err_iounmap_ctrl_base;
1988                }
1989                break;
1990        case NV_ARCH_04:
1991        case NV_ARCH_10:
1992        case NV_ARCH_20:
1993        case NV_ARCH_30:
1994                default_par->riva.PCRTC0 =
1995                        (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1996                default_par->riva.PRAMIN =
1997                        (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
1998                break;
1999        }
2000        riva_common_setup(default_par);
2001
2002        if (default_par->riva.Architecture == NV_ARCH_03) {
2003                default_par->riva.PCRTC = default_par->riva.PCRTC0
2004                                        = default_par->riva.PGRAPH;
2005        }
2006
2007        rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2008        default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2009        info->screen_base = ioremap_wc(rivafb_fix.smem_start,
2010                                       rivafb_fix.smem_len);
2011        if (!info->screen_base) {
2012                printk(KERN_ERR PFX "cannot ioremap FB base\n");
2013                ret = -EIO;
2014                goto err_iounmap_pramin;
2015        }
2016
2017        if (!nomtrr)
2018                default_par->wc_cookie =
2019                        arch_phys_wc_add(rivafb_fix.smem_start,
2020                                         rivafb_fix.smem_len);
2021
2022        info->fbops = &riva_fb_ops;
2023        info->fix = rivafb_fix;
2024        riva_get_EDID(info, pd);
2025        riva_get_edidinfo(info);
2026
2027        ret=riva_set_fbinfo(info);
2028        if (ret < 0) {
2029                printk(KERN_ERR PFX "error setting initial video mode\n");
2030                goto err_iounmap_screen_base;
2031        }
2032
2033        fb_destroy_modedb(info->monspecs.modedb);
2034        info->monspecs.modedb = NULL;
2035
2036        pci_set_drvdata(pd, info);
2037
2038        if (backlight)
2039                riva_bl_init(info->par);
2040
2041        ret = register_framebuffer(info);
2042        if (ret < 0) {
2043                printk(KERN_ERR PFX
2044                        "error registering riva framebuffer\n");
2045                goto err_iounmap_screen_base;
2046        }
2047
2048        printk(KERN_INFO PFX
2049                "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2050                info->fix.id,
2051                RIVAFB_VERSION,
2052                info->fix.smem_len / (1024 * 1024),
2053                info->fix.smem_start);
2054
2055        NVTRACE_LEAVE();
2056        return 0;
2057
2058err_iounmap_screen_base:
2059#ifdef CONFIG_FB_RIVA_I2C
2060        riva_delete_i2c_busses(info->par);
2061#endif
2062        iounmap(info->screen_base);
2063err_iounmap_pramin:
2064        if (default_par->riva.Architecture == NV_ARCH_03) 
2065                iounmap(default_par->riva.PRAMIN);
2066err_iounmap_ctrl_base:
2067        iounmap(default_par->ctrl_base);
2068err_release_region:
2069        pci_release_regions(pd);
2070err_disable_device:
2071err_free_pixmap:
2072        kfree(info->pixmap.addr);
2073err_framebuffer_release:
2074        framebuffer_release(info);
2075err_ret:
2076        return ret;
2077}
2078
2079static void rivafb_remove(struct pci_dev *pd)
2080{
2081        struct fb_info *info = pci_get_drvdata(pd);
2082        struct riva_par *par = info->par;
2083        
2084        NVTRACE_ENTER();
2085
2086#ifdef CONFIG_FB_RIVA_I2C
2087        riva_delete_i2c_busses(par);
2088        kfree(par->EDID);
2089#endif
2090
2091        unregister_framebuffer(info);
2092
2093        riva_bl_exit(info);
2094        arch_phys_wc_del(par->wc_cookie);
2095        iounmap(par->ctrl_base);
2096        iounmap(info->screen_base);
2097        if (par->riva.Architecture == NV_ARCH_03)
2098                iounmap(par->riva.PRAMIN);
2099        pci_release_regions(pd);
2100        kfree(info->pixmap.addr);
2101        framebuffer_release(info);
2102        NVTRACE_LEAVE();
2103}
2104
2105/* ------------------------------------------------------------------------- *
2106 *
2107 * initialization
2108 *
2109 * ------------------------------------------------------------------------- */
2110
2111#ifndef MODULE
2112static int rivafb_setup(char *options)
2113{
2114        char *this_opt;
2115
2116        NVTRACE_ENTER();
2117        if (!options || !*options)
2118                return 0;
2119
2120        while ((this_opt = strsep(&options, ",")) != NULL) {
2121                if (!strncmp(this_opt, "forceCRTC", 9)) {
2122                        char *p;
2123                        
2124                        p = this_opt + 9;
2125                        if (!*p || !*(++p)) continue; 
2126                        forceCRTC = *p - '0';
2127                        if (forceCRTC < 0 || forceCRTC > 1) 
2128                                forceCRTC = -1;
2129                } else if (!strncmp(this_opt, "flatpanel", 9)) {
2130                        flatpanel = 1;
2131                } else if (!strncmp(this_opt, "backlight:", 10)) {
2132                        backlight = simple_strtoul(this_opt+10, NULL, 0);
2133                } else if (!strncmp(this_opt, "nomtrr", 6)) {
2134                        nomtrr = 1;
2135                } else if (!strncmp(this_opt, "strictmode", 10)) {
2136                        strictmode = 1;
2137                } else if (!strncmp(this_opt, "noaccel", 7)) {
2138                        noaccel = 1;
2139                } else
2140                        mode_option = this_opt;
2141        }
2142        NVTRACE_LEAVE();
2143        return 0;
2144}
2145#endif /* !MODULE */
2146
2147static struct pci_driver rivafb_driver = {
2148        .name           = "rivafb",
2149        .id_table       = rivafb_pci_tbl,
2150        .probe          = rivafb_probe,
2151        .remove         = rivafb_remove,
2152};
2153
2154
2155
2156/* ------------------------------------------------------------------------- *
2157 *
2158 * modularization
2159 *
2160 * ------------------------------------------------------------------------- */
2161
2162static int rivafb_init(void)
2163{
2164#ifndef MODULE
2165        char *option = NULL;
2166
2167        if (fb_get_options("rivafb", &option))
2168                return -ENODEV;
2169        rivafb_setup(option);
2170#endif
2171        return pci_register_driver(&rivafb_driver);
2172}
2173
2174
2175module_init(rivafb_init);
2176
2177static void __exit rivafb_exit(void)
2178{
2179        pci_unregister_driver(&rivafb_driver);
2180}
2181
2182module_exit(rivafb_exit);
2183
2184module_param(noaccel, bool, 0);
2185MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2186module_param(flatpanel, int, 0);
2187MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2188module_param(forceCRTC, int, 0);
2189MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2190module_param(nomtrr, bool, 0);
2191MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2192module_param(strictmode, bool, 0);
2193MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2194
2195MODULE_AUTHOR("Ani Joshi, maintainer");
2196MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2197MODULE_LICENSE("GPL");
2198