1/******************************************************************************* 2 3 Header file for stmmac platform data 4 5 Copyright (C) 2009 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24*******************************************************************************/ 25 26#ifndef __STMMAC_PLATFORM_DATA 27#define __STMMAC_PLATFORM_DATA 28 29#include <linux/platform_device.h> 30 31#define MTL_MAX_RX_QUEUES 8 32#define MTL_MAX_TX_QUEUES 8 33#define STMMAC_CH_MAX 8 34 35#define STMMAC_RX_COE_NONE 0 36#define STMMAC_RX_COE_TYPE1 1 37#define STMMAC_RX_COE_TYPE2 2 38 39/* Define the macros for CSR clock range parameters to be passed by 40 * platform code. 41 * This could also be configured at run time using CPU freq framework. */ 42 43/* MDC Clock Selection define*/ 44#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 45#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 46#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 47#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 48#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 49#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 50 51/* MTL algorithms identifiers */ 52#define MTL_TX_ALGORITHM_WRR 0x0 53#define MTL_TX_ALGORITHM_WFQ 0x1 54#define MTL_TX_ALGORITHM_DWRR 0x2 55#define MTL_TX_ALGORITHM_SP 0x3 56#define MTL_RX_ALGORITHM_SP 0x4 57#define MTL_RX_ALGORITHM_WSP 0x5 58 59/* RX/TX Queue Mode */ 60#define MTL_QUEUE_AVB 0x0 61#define MTL_QUEUE_DCB 0x1 62 63/* The MDC clock could be set higher than the IEEE 802.3 64 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 65 * of value different than the above defined values. The resultant MDIO 66 * clock frequency of 12.5 MHz is applicable for the interfacing chips 67 * supporting higher MDC clocks. 68 * The MDC clock selection macros need to be defined for MDC clock rate 69 * of 12.5 MHz, corresponding to the following selection. 70 */ 71#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 72#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 73#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 74#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 75#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 76#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 77#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 78#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 79 80/* AXI DMA Burst length supported */ 81#define DMA_AXI_BLEN_4 (1 << 1) 82#define DMA_AXI_BLEN_8 (1 << 2) 83#define DMA_AXI_BLEN_16 (1 << 3) 84#define DMA_AXI_BLEN_32 (1 << 4) 85#define DMA_AXI_BLEN_64 (1 << 5) 86#define DMA_AXI_BLEN_128 (1 << 6) 87#define DMA_AXI_BLEN_256 (1 << 7) 88#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 89 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 90 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 91 92/* Platfrom data for platform device structure's platform_data field */ 93 94struct stmmac_mdio_bus_data { 95 int (*phy_reset)(void *priv); 96 unsigned int phy_mask; 97 int *irqs; 98 int probed_phy_irq; 99#ifdef CONFIG_OF 100 int reset_gpio, active_low; 101 u32 delays[3]; 102#endif 103}; 104 105struct stmmac_dma_cfg { 106 int pbl; 107 int txpbl; 108 int rxpbl; 109 bool pblx8; 110 int fixed_burst; 111 int mixed_burst; 112 bool aal; 113}; 114 115#define AXI_BLEN 7 116struct stmmac_axi { 117 bool axi_lpi_en; 118 bool axi_xit_frm; 119 u32 axi_wr_osr_lmt; 120 u32 axi_rd_osr_lmt; 121 bool axi_kbbe; 122 u32 axi_blen[AXI_BLEN]; 123 bool axi_fb; 124 bool axi_mb; 125 bool axi_rb; 126}; 127 128struct stmmac_rxq_cfg { 129 u8 mode_to_use; 130 u32 chan; 131 u8 pkt_route; 132 bool use_prio; 133 u32 prio; 134}; 135 136struct stmmac_txq_cfg { 137 u32 weight; 138 u8 mode_to_use; 139 /* Credit Base Shaper parameters */ 140 u32 send_slope; 141 u32 idle_slope; 142 u32 high_credit; 143 u32 low_credit; 144 bool use_prio; 145 u32 prio; 146}; 147 148struct plat_stmmacenet_data { 149 int bus_id; 150 int phy_addr; 151 int interface; 152 struct stmmac_mdio_bus_data *mdio_bus_data; 153 struct device_node *phy_node; 154 struct device_node *mdio_node; 155 struct stmmac_dma_cfg *dma_cfg; 156 int clk_csr; 157 int has_gmac; 158 int enh_desc; 159 int tx_coe; 160 int rx_coe; 161 int bugged_jumbo; 162 int pmt; 163 int force_sf_dma_mode; 164 int force_thresh_dma_mode; 165 int riwt_off; 166 int max_speed; 167 int maxmtu; 168 int multicast_filter_bins; 169 int unicast_filter_entries; 170 int tx_fifo_size; 171 int rx_fifo_size; 172 u32 rx_queues_to_use; 173 u32 tx_queues_to_use; 174 u8 rx_sched_algorithm; 175 u8 tx_sched_algorithm; 176 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 177 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 178 void (*fix_mac_speed)(void *priv, unsigned int speed); 179 int (*init)(struct platform_device *pdev, void *priv); 180 void (*exit)(struct platform_device *pdev, void *priv); 181 struct mac_device_info *(*setup)(void *priv); 182 void *bsp_priv; 183 struct clk *stmmac_clk; 184 struct clk *pclk; 185 struct clk *clk_ptp_ref; 186 unsigned int clk_ptp_rate; 187 unsigned int clk_ref_rate; 188 struct reset_control *stmmac_rst; 189 struct stmmac_axi *axi; 190 int has_gmac4; 191 bool has_sun8i; 192 bool tso_en; 193 int mac_port_sel_speed; 194 bool en_tx_lpi_clockgating; 195 int has_xgmac; 196}; 197#endif 198