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16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/version.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/i2c.h>
23#include <linux/gpio.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include <linux/gpio/consumer.h>
29#include <linux/of.h>
30#include <linux/of_gpio.h>
31#include <linux/of_device.h>
32#include <sound/core.h>
33#include <sound/pcm.h>
34#include <sound/pcm_params.h>
35#include <sound/soc.h>
36#include <sound/soc-dapm.h>
37#include <sound/initval.h>
38#include <sound/tlv.h>
39#include <dt-bindings/sound/cs42l42.h>
40
41#include "cs42l42.h"
42
43static const struct reg_default cs42l42_reg_defaults[] = {
44 { CS42L42_FRZ_CTL, 0x00 },
45 { CS42L42_SRC_CTL, 0x10 },
46 { CS42L42_MCLK_STATUS, 0x02 },
47 { CS42L42_MCLK_CTL, 0x02 },
48 { CS42L42_SFTRAMP_RATE, 0xA4 },
49 { CS42L42_I2C_DEBOUNCE, 0x88 },
50 { CS42L42_I2C_STRETCH, 0x03 },
51 { CS42L42_I2C_TIMEOUT, 0xB7 },
52 { CS42L42_PWR_CTL1, 0xFF },
53 { CS42L42_PWR_CTL2, 0x84 },
54 { CS42L42_PWR_CTL3, 0x20 },
55 { CS42L42_RSENSE_CTL1, 0x40 },
56 { CS42L42_RSENSE_CTL2, 0x00 },
57 { CS42L42_OSC_SWITCH, 0x00 },
58 { CS42L42_OSC_SWITCH_STATUS, 0x05 },
59 { CS42L42_RSENSE_CTL3, 0x1B },
60 { CS42L42_TSENSE_CTL, 0x1B },
61 { CS42L42_TSRS_INT_DISABLE, 0x00 },
62 { CS42L42_TRSENSE_STATUS, 0x00 },
63 { CS42L42_HSDET_CTL1, 0x77 },
64 { CS42L42_HSDET_CTL2, 0x00 },
65 { CS42L42_HS_SWITCH_CTL, 0xF3 },
66 { CS42L42_HS_DET_STATUS, 0x00 },
67 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
68 { CS42L42_MCLK_SRC_SEL, 0x00 },
69 { CS42L42_SPDIF_CLK_CFG, 0x00 },
70 { CS42L42_FSYNC_PW_LOWER, 0x00 },
71 { CS42L42_FSYNC_PW_UPPER, 0x00 },
72 { CS42L42_FSYNC_P_LOWER, 0xF9 },
73 { CS42L42_FSYNC_P_UPPER, 0x00 },
74 { CS42L42_ASP_CLK_CFG, 0x00 },
75 { CS42L42_ASP_FRM_CFG, 0x10 },
76 { CS42L42_FS_RATE_EN, 0x00 },
77 { CS42L42_IN_ASRC_CLK, 0x00 },
78 { CS42L42_OUT_ASRC_CLK, 0x00 },
79 { CS42L42_PLL_DIV_CFG1, 0x00 },
80 { CS42L42_ADC_OVFL_STATUS, 0x00 },
81 { CS42L42_MIXER_STATUS, 0x00 },
82 { CS42L42_SRC_STATUS, 0x00 },
83 { CS42L42_ASP_RX_STATUS, 0x00 },
84 { CS42L42_ASP_TX_STATUS, 0x00 },
85 { CS42L42_CODEC_STATUS, 0x00 },
86 { CS42L42_DET_INT_STATUS1, 0x00 },
87 { CS42L42_DET_INT_STATUS2, 0x00 },
88 { CS42L42_SRCPL_INT_STATUS, 0x00 },
89 { CS42L42_VPMON_STATUS, 0x00 },
90 { CS42L42_PLL_LOCK_STATUS, 0x00 },
91 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
92 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
93 { CS42L42_MIXER_INT_MASK, 0x0F },
94 { CS42L42_SRC_INT_MASK, 0x0F },
95 { CS42L42_ASP_RX_INT_MASK, 0x1F },
96 { CS42L42_ASP_TX_INT_MASK, 0x0F },
97 { CS42L42_CODEC_INT_MASK, 0x03 },
98 { CS42L42_SRCPL_INT_MASK, 0xFF },
99 { CS42L42_VPMON_INT_MASK, 0x01 },
100 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
101 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
102 { CS42L42_PLL_CTL1, 0x00 },
103 { CS42L42_PLL_DIV_FRAC0, 0x00 },
104 { CS42L42_PLL_DIV_FRAC1, 0x00 },
105 { CS42L42_PLL_DIV_FRAC2, 0x00 },
106 { CS42L42_PLL_DIV_INT, 0x40 },
107 { CS42L42_PLL_CTL3, 0x10 },
108 { CS42L42_PLL_CAL_RATIO, 0x80 },
109 { CS42L42_PLL_CTL4, 0x03 },
110 { CS42L42_LOAD_DET_RCSTAT, 0x00 },
111 { CS42L42_LOAD_DET_DONE, 0x00 },
112 { CS42L42_LOAD_DET_EN, 0x00 },
113 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
114 { CS42L42_WAKE_CTL, 0xC0 },
115 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
116 { CS42L42_TIPSENSE_CTL, 0x02 },
117 { CS42L42_MISC_DET_CTL, 0x03 },
118 { CS42L42_MIC_DET_CTL1, 0x1F },
119 { CS42L42_MIC_DET_CTL2, 0x2F },
120 { CS42L42_DET_STATUS1, 0x00 },
121 { CS42L42_DET_STATUS2, 0x00 },
122 { CS42L42_DET_INT1_MASK, 0xE0 },
123 { CS42L42_DET_INT2_MASK, 0xFF },
124 { CS42L42_HS_BIAS_CTL, 0xC2 },
125 { CS42L42_ADC_CTL, 0x00 },
126 { CS42L42_ADC_VOLUME, 0x00 },
127 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
128 { CS42L42_DAC_CTL1, 0x00 },
129 { CS42L42_DAC_CTL2, 0x02 },
130 { CS42L42_HP_CTL, 0x0D },
131 { CS42L42_CLASSH_CTL, 0x07 },
132 { CS42L42_MIXER_CHA_VOL, 0x3F },
133 { CS42L42_MIXER_ADC_VOL, 0x3F },
134 { CS42L42_MIXER_CHB_VOL, 0x3F },
135 { CS42L42_EQ_COEF_IN0, 0x22 },
136 { CS42L42_EQ_COEF_IN1, 0x00 },
137 { CS42L42_EQ_COEF_IN2, 0x00 },
138 { CS42L42_EQ_COEF_IN3, 0x00 },
139 { CS42L42_EQ_COEF_RW, 0x00 },
140 { CS42L42_EQ_COEF_OUT0, 0x00 },
141 { CS42L42_EQ_COEF_OUT1, 0x00 },
142 { CS42L42_EQ_COEF_OUT2, 0x00 },
143 { CS42L42_EQ_COEF_OUT3, 0x00 },
144 { CS42L42_EQ_INIT_STAT, 0x00 },
145 { CS42L42_EQ_START_FILT, 0x00 },
146 { CS42L42_EQ_MUTE_CTL, 0x00 },
147 { CS42L42_SP_RX_CH_SEL, 0x04 },
148 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
149 { CS42L42_SP_RX_FS, 0x8C },
150 { CS42l42_SPDIF_CH_SEL, 0x0E },
151 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
152 { CS42L42_SP_TX_FS, 0xCC },
153 { CS42L42_SPDIF_SW_CTL1, 0x3F },
154 { CS42L42_SRC_SDIN_FS, 0x40 },
155 { CS42L42_SRC_SDOUT_FS, 0x40 },
156 { CS42L42_SPDIF_CTL1, 0x01 },
157 { CS42L42_SPDIF_CTL2, 0x00 },
158 { CS42L42_SPDIF_CTL3, 0x00 },
159 { CS42L42_SPDIF_CTL4, 0x42 },
160 { CS42L42_ASP_TX_SZ_EN, 0x00 },
161 { CS42L42_ASP_TX_CH_EN, 0x00 },
162 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
163 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
164 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
165 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
166 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
167 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
168 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
169 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
170 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
171 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
172 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
173 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
174 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
175 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
176 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
177 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
178 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
179 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
180 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
181 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
182 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
183 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
184 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
185 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
186 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
187 { CS42L42_SUB_REVID, 0x03 },
188};
189
190static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
191{
192 switch (reg) {
193 case CS42L42_PAGE_REGISTER:
194 case CS42L42_DEVID_AB:
195 case CS42L42_DEVID_CD:
196 case CS42L42_DEVID_E:
197 case CS42L42_FABID:
198 case CS42L42_REVID:
199 case CS42L42_FRZ_CTL:
200 case CS42L42_SRC_CTL:
201 case CS42L42_MCLK_STATUS:
202 case CS42L42_MCLK_CTL:
203 case CS42L42_SFTRAMP_RATE:
204 case CS42L42_I2C_DEBOUNCE:
205 case CS42L42_I2C_STRETCH:
206 case CS42L42_I2C_TIMEOUT:
207 case CS42L42_PWR_CTL1:
208 case CS42L42_PWR_CTL2:
209 case CS42L42_PWR_CTL3:
210 case CS42L42_RSENSE_CTL1:
211 case CS42L42_RSENSE_CTL2:
212 case CS42L42_OSC_SWITCH:
213 case CS42L42_OSC_SWITCH_STATUS:
214 case CS42L42_RSENSE_CTL3:
215 case CS42L42_TSENSE_CTL:
216 case CS42L42_TSRS_INT_DISABLE:
217 case CS42L42_TRSENSE_STATUS:
218 case CS42L42_HSDET_CTL1:
219 case CS42L42_HSDET_CTL2:
220 case CS42L42_HS_SWITCH_CTL:
221 case CS42L42_HS_DET_STATUS:
222 case CS42L42_HS_CLAMP_DISABLE:
223 case CS42L42_MCLK_SRC_SEL:
224 case CS42L42_SPDIF_CLK_CFG:
225 case CS42L42_FSYNC_PW_LOWER:
226 case CS42L42_FSYNC_PW_UPPER:
227 case CS42L42_FSYNC_P_LOWER:
228 case CS42L42_FSYNC_P_UPPER:
229 case CS42L42_ASP_CLK_CFG:
230 case CS42L42_ASP_FRM_CFG:
231 case CS42L42_FS_RATE_EN:
232 case CS42L42_IN_ASRC_CLK:
233 case CS42L42_OUT_ASRC_CLK:
234 case CS42L42_PLL_DIV_CFG1:
235 case CS42L42_ADC_OVFL_STATUS:
236 case CS42L42_MIXER_STATUS:
237 case CS42L42_SRC_STATUS:
238 case CS42L42_ASP_RX_STATUS:
239 case CS42L42_ASP_TX_STATUS:
240 case CS42L42_CODEC_STATUS:
241 case CS42L42_DET_INT_STATUS1:
242 case CS42L42_DET_INT_STATUS2:
243 case CS42L42_SRCPL_INT_STATUS:
244 case CS42L42_VPMON_STATUS:
245 case CS42L42_PLL_LOCK_STATUS:
246 case CS42L42_TSRS_PLUG_STATUS:
247 case CS42L42_ADC_OVFL_INT_MASK:
248 case CS42L42_MIXER_INT_MASK:
249 case CS42L42_SRC_INT_MASK:
250 case CS42L42_ASP_RX_INT_MASK:
251 case CS42L42_ASP_TX_INT_MASK:
252 case CS42L42_CODEC_INT_MASK:
253 case CS42L42_SRCPL_INT_MASK:
254 case CS42L42_VPMON_INT_MASK:
255 case CS42L42_PLL_LOCK_INT_MASK:
256 case CS42L42_TSRS_PLUG_INT_MASK:
257 case CS42L42_PLL_CTL1:
258 case CS42L42_PLL_DIV_FRAC0:
259 case CS42L42_PLL_DIV_FRAC1:
260 case CS42L42_PLL_DIV_FRAC2:
261 case CS42L42_PLL_DIV_INT:
262 case CS42L42_PLL_CTL3:
263 case CS42L42_PLL_CAL_RATIO:
264 case CS42L42_PLL_CTL4:
265 case CS42L42_LOAD_DET_RCSTAT:
266 case CS42L42_LOAD_DET_DONE:
267 case CS42L42_LOAD_DET_EN:
268 case CS42L42_HSBIAS_SC_AUTOCTL:
269 case CS42L42_WAKE_CTL:
270 case CS42L42_ADC_DISABLE_MUTE:
271 case CS42L42_TIPSENSE_CTL:
272 case CS42L42_MISC_DET_CTL:
273 case CS42L42_MIC_DET_CTL1:
274 case CS42L42_MIC_DET_CTL2:
275 case CS42L42_DET_STATUS1:
276 case CS42L42_DET_STATUS2:
277 case CS42L42_DET_INT1_MASK:
278 case CS42L42_DET_INT2_MASK:
279 case CS42L42_HS_BIAS_CTL:
280 case CS42L42_ADC_CTL:
281 case CS42L42_ADC_VOLUME:
282 case CS42L42_ADC_WNF_HPF_CTL:
283 case CS42L42_DAC_CTL1:
284 case CS42L42_DAC_CTL2:
285 case CS42L42_HP_CTL:
286 case CS42L42_CLASSH_CTL:
287 case CS42L42_MIXER_CHA_VOL:
288 case CS42L42_MIXER_ADC_VOL:
289 case CS42L42_MIXER_CHB_VOL:
290 case CS42L42_EQ_COEF_IN0:
291 case CS42L42_EQ_COEF_IN1:
292 case CS42L42_EQ_COEF_IN2:
293 case CS42L42_EQ_COEF_IN3:
294 case CS42L42_EQ_COEF_RW:
295 case CS42L42_EQ_COEF_OUT0:
296 case CS42L42_EQ_COEF_OUT1:
297 case CS42L42_EQ_COEF_OUT2:
298 case CS42L42_EQ_COEF_OUT3:
299 case CS42L42_EQ_INIT_STAT:
300 case CS42L42_EQ_START_FILT:
301 case CS42L42_EQ_MUTE_CTL:
302 case CS42L42_SP_RX_CH_SEL:
303 case CS42L42_SP_RX_ISOC_CTL:
304 case CS42L42_SP_RX_FS:
305 case CS42l42_SPDIF_CH_SEL:
306 case CS42L42_SP_TX_ISOC_CTL:
307 case CS42L42_SP_TX_FS:
308 case CS42L42_SPDIF_SW_CTL1:
309 case CS42L42_SRC_SDIN_FS:
310 case CS42L42_SRC_SDOUT_FS:
311 case CS42L42_SPDIF_CTL1:
312 case CS42L42_SPDIF_CTL2:
313 case CS42L42_SPDIF_CTL3:
314 case CS42L42_SPDIF_CTL4:
315 case CS42L42_ASP_TX_SZ_EN:
316 case CS42L42_ASP_TX_CH_EN:
317 case CS42L42_ASP_TX_CH_AP_RES:
318 case CS42L42_ASP_TX_CH1_BIT_MSB:
319 case CS42L42_ASP_TX_CH1_BIT_LSB:
320 case CS42L42_ASP_TX_HIZ_DLY_CFG:
321 case CS42L42_ASP_TX_CH2_BIT_MSB:
322 case CS42L42_ASP_TX_CH2_BIT_LSB:
323 case CS42L42_ASP_RX_DAI0_EN:
324 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
325 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
326 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
327 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
328 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
329 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
330 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
331 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
332 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
333 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
334 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
335 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
336 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
337 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
338 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
339 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
340 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
341 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
342 case CS42L42_SUB_REVID:
343 return true;
344 default:
345 return false;
346 }
347}
348
349static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
350{
351 switch (reg) {
352 case CS42L42_DEVID_AB:
353 case CS42L42_DEVID_CD:
354 case CS42L42_DEVID_E:
355 case CS42L42_MCLK_STATUS:
356 case CS42L42_TRSENSE_STATUS:
357 case CS42L42_HS_DET_STATUS:
358 case CS42L42_ADC_OVFL_STATUS:
359 case CS42L42_MIXER_STATUS:
360 case CS42L42_SRC_STATUS:
361 case CS42L42_ASP_RX_STATUS:
362 case CS42L42_ASP_TX_STATUS:
363 case CS42L42_CODEC_STATUS:
364 case CS42L42_DET_INT_STATUS1:
365 case CS42L42_DET_INT_STATUS2:
366 case CS42L42_SRCPL_INT_STATUS:
367 case CS42L42_VPMON_STATUS:
368 case CS42L42_PLL_LOCK_STATUS:
369 case CS42L42_TSRS_PLUG_STATUS:
370 case CS42L42_LOAD_DET_RCSTAT:
371 case CS42L42_LOAD_DET_DONE:
372 case CS42L42_DET_STATUS1:
373 case CS42L42_DET_STATUS2:
374 return true;
375 default:
376 return false;
377 }
378}
379
380static const struct regmap_range_cfg cs42l42_page_range = {
381 .name = "Pages",
382 .range_min = 0,
383 .range_max = CS42L42_MAX_REGISTER,
384 .selector_reg = CS42L42_PAGE_REGISTER,
385 .selector_mask = 0xff,
386 .selector_shift = 0,
387 .window_start = 0,
388 .window_len = 256,
389};
390
391static const struct regmap_config cs42l42_regmap = {
392 .reg_bits = 8,
393 .val_bits = 8,
394
395 .readable_reg = cs42l42_readable_register,
396 .volatile_reg = cs42l42_volatile_register,
397
398 .ranges = &cs42l42_page_range,
399 .num_ranges = 1,
400
401 .max_register = CS42L42_MAX_REGISTER,
402 .reg_defaults = cs42l42_reg_defaults,
403 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
404 .cache_type = REGCACHE_RBTREE,
405};
406
407static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false);
408static DECLARE_TLV_DB_SCALE(mixer_tlv, -6200, 100, false);
409
410static const char * const cs42l42_hpf_freq_text[] = {
411 "1.86Hz", "120Hz", "235Hz", "466Hz"
412};
413
414static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
415 CS42L42_ADC_HPF_CF_SHIFT,
416 cs42l42_hpf_freq_text);
417
418static const char * const cs42l42_wnf3_freq_text[] = {
419 "160Hz", "180Hz", "200Hz", "220Hz",
420 "240Hz", "260Hz", "280Hz", "300Hz"
421};
422
423static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
424 CS42L42_ADC_WNF_CF_SHIFT,
425 cs42l42_wnf3_freq_text);
426
427static const char * const cs42l42_wnf05_freq_text[] = {
428 "280Hz", "315Hz", "350Hz", "385Hz",
429 "420Hz", "455Hz", "490Hz", "525Hz"
430};
431
432static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
433 CS42L42_ADC_WNF_CF_SHIFT,
434 cs42l42_wnf05_freq_text);
435
436static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
437
438 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
439 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false),
440 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
441 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
442 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
443 CS42L42_ADC_INV_SHIFT, true, false),
444 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
445 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
446 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME,
447 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv),
448 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
449 CS42L42_ADC_WNF_EN_SHIFT, true, false),
450 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
451 CS42L42_ADC_HPF_EN_SHIFT, true, false),
452 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
453 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
454 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
455
456
457 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
458 CS42L42_DACA_INV_SHIFT, true, false),
459 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
460 CS42L42_DACB_INV_SHIFT, true, false),
461 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
462 CS42L42_DAC_HPF_EN_SHIFT, true, false),
463 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
464 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
465 0x3e, 1, mixer_tlv)
466};
467
468static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
469 struct snd_kcontrol *kcontrol, int event)
470{
471 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
472
473 if (event & SND_SOC_DAPM_POST_PMU) {
474
475 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
476 CS42L42_ASP_RX0_CH_EN_MASK,
477 (CS42L42_ASP_RX0_CH1_EN |
478 CS42L42_ASP_RX0_CH2_EN) <<
479 CS42L42_ASP_RX0_CH_EN_SHIFT);
480
481
482 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
483 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
484 CS42L42_HP_PDN_MASK, 0);
485 } else if (event & SND_SOC_DAPM_PRE_PMD) {
486
487 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
488 CS42L42_ASP_RX0_CH_EN_MASK, 0);
489
490
491 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
492 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
493 CS42L42_HP_PDN_MASK,
494 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
495 CS42L42_HP_PDN_MASK);
496 } else {
497 dev_err(component->dev, "Invalid event 0x%x\n", event);
498 }
499 return 0;
500}
501
502static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
503 SND_SOC_DAPM_OUTPUT("HP"),
504 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
505 CS42L42_ASP_SCLK_EN_SHIFT, false),
506 SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
507 0, NULL, 0, cs42l42_hpdrv_evt,
508 SND_SOC_DAPM_POST_PMU |
509 SND_SOC_DAPM_PRE_PMD)
510};
511
512static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
513 {"SDIN", NULL, "Playback"},
514 {"HPDRV", NULL, "SDIN"},
515 {"HP", NULL, "HPDRV"}
516};
517
518static int cs42l42_set_bias_level(struct snd_soc_component *component,
519 enum snd_soc_bias_level level)
520{
521 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
522 int ret;
523
524 switch (level) {
525 case SND_SOC_BIAS_ON:
526 break;
527 case SND_SOC_BIAS_PREPARE:
528 break;
529 case SND_SOC_BIAS_STANDBY:
530 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
531 regcache_cache_only(cs42l42->regmap, false);
532 regcache_sync(cs42l42->regmap);
533 ret = regulator_bulk_enable(
534 ARRAY_SIZE(cs42l42->supplies),
535 cs42l42->supplies);
536 if (ret != 0) {
537 dev_err(component->dev,
538 "Failed to enable regulators: %d\n",
539 ret);
540 return ret;
541 }
542 }
543 break;
544 case SND_SOC_BIAS_OFF:
545
546 regcache_cache_only(cs42l42->regmap, true);
547 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
548 cs42l42->supplies);
549 break;
550 }
551
552 return 0;
553}
554
555static int cs42l42_component_probe(struct snd_soc_component *component)
556{
557 struct cs42l42_private *cs42l42 =
558 (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
559
560 cs42l42->component = component;
561
562 return 0;
563}
564
565static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
566 .probe = cs42l42_component_probe,
567 .set_bias_level = cs42l42_set_bias_level,
568 .dapm_widgets = cs42l42_dapm_widgets,
569 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
570 .dapm_routes = cs42l42_audio_map,
571 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
572 .controls = cs42l42_snd_controls,
573 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
574 .idle_bias_on = 1,
575 .endianness = 1,
576 .non_legacy_dai_naming = 1,
577};
578
579struct cs42l42_pll_params {
580 u32 sclk;
581 u8 mclk_div;
582 u8 mclk_src_sel;
583 u8 sclk_prediv;
584 u8 pll_div_int;
585 u32 pll_div_frac;
586 u8 pll_mode;
587 u8 pll_divout;
588 u32 mclk_int;
589 u8 pll_cal_ratio;
590};
591
592
593
594
595
596static const struct cs42l42_pll_params pll_ratio_table[] = {
597 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
598 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
599 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
600 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
601 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
602 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
603 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
604 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
605 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
606 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
607 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
608 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
609 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
610 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
611 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
612};
613
614static int cs42l42_pll_config(struct snd_soc_component *component)
615{
616 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
617 int i;
618 u32 fsync;
619
620 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
621 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
622
623 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
624 CS42L42_INTERNAL_FS_MASK,
625 ((pll_ratio_table[i].mclk_int !=
626 12000000) &&
627 (pll_ratio_table[i].mclk_int !=
628 24000000)) <<
629 CS42L42_INTERNAL_FS_SHIFT);
630
631
632
633 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
634 CS42L42_MCLK_SRC_SEL_MASK |
635 CS42L42_MCLKDIV_MASK,
636 (pll_ratio_table[i].mclk_src_sel
637 << CS42L42_MCLK_SRC_SEL_SHIFT) |
638 (pll_ratio_table[i].mclk_div <<
639 CS42L42_MCLKDIV_SHIFT));
640
641 fsync = cs42l42->sclk / cs42l42->srate;
642 if (((fsync * cs42l42->srate) != cs42l42->sclk)
643 || ((fsync % 2) != 0)) {
644 dev_err(component->dev,
645 "Unsupported sclk %d/sample rate %d\n",
646 cs42l42->sclk,
647 cs42l42->srate);
648 return -EINVAL;
649 }
650
651 snd_soc_component_update_bits(component,
652 CS42L42_FSYNC_P_LOWER,
653 CS42L42_FSYNC_PERIOD_MASK,
654 CS42L42_FRAC0_VAL(fsync - 1) <<
655 CS42L42_FSYNC_PERIOD_SHIFT);
656 snd_soc_component_update_bits(component,
657 CS42L42_FSYNC_P_UPPER,
658 CS42L42_FSYNC_PERIOD_MASK,
659 CS42L42_FRAC1_VAL(fsync - 1) <<
660 CS42L42_FSYNC_PERIOD_SHIFT);
661
662 fsync = fsync / 2;
663 snd_soc_component_update_bits(component,
664 CS42L42_FSYNC_PW_LOWER,
665 CS42L42_FSYNC_PULSE_WIDTH_MASK,
666 CS42L42_FRAC0_VAL(fsync - 1) <<
667 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
668 snd_soc_component_update_bits(component,
669 CS42L42_FSYNC_PW_UPPER,
670 CS42L42_FSYNC_PULSE_WIDTH_MASK,
671 CS42L42_FRAC1_VAL(fsync - 1) <<
672 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
673 snd_soc_component_update_bits(component,
674 CS42L42_ASP_FRM_CFG,
675 CS42L42_ASP_5050_MASK,
676 CS42L42_ASP_5050_MASK);
677
678 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG,
679 CS42L42_ASP_FSD_MASK,
680 CS42L42_ASP_FSD_1_0 <<
681 CS42L42_ASP_FSD_SHIFT);
682
683 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
684 CS42L42_FS_EN_MASK,
685 (CS42L42_FS_EN_IASRC_96K |
686 CS42L42_FS_EN_OASRC_96K) <<
687 CS42L42_FS_EN_SHIFT);
688
689 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
690 CS42L42_CLK_IASRC_SEL_MASK,
691 CS42L42_CLK_IASRC_SEL_12 <<
692 CS42L42_CLK_IASRC_SEL_SHIFT);
693 snd_soc_component_update_bits(component,
694 CS42L42_OUT_ASRC_CLK,
695 CS42L42_CLK_OASRC_SEL_MASK,
696 CS42L42_CLK_OASRC_SEL_12 <<
697 CS42L42_CLK_OASRC_SEL_SHIFT);
698
699 snd_soc_component_update_bits(component,
700 CS42L42_ASP_RX_DAI0_CH1_AP_RES,
701 CS42L42_ASP_RX_CH_AP_MASK |
702 CS42L42_ASP_RX_CH_RES_MASK,
703 (CS42L42_ASP_RX_CH_AP_LOW <<
704 CS42L42_ASP_RX_CH_AP_SHIFT) |
705 (CS42L42_ASP_RX_CH_RES_32 <<
706 CS42L42_ASP_RX_CH_RES_SHIFT));
707
708 snd_soc_component_update_bits(component,
709 CS42L42_ASP_RX_DAI0_CH2_AP_RES,
710 CS42L42_ASP_RX_CH_AP_MASK |
711 CS42L42_ASP_RX_CH_RES_MASK,
712 (CS42L42_ASP_RX_CH_AP_HI <<
713 CS42L42_ASP_RX_CH_AP_SHIFT) |
714 (CS42L42_ASP_RX_CH_RES_32 <<
715 CS42L42_ASP_RX_CH_RES_SHIFT));
716 if (pll_ratio_table[i].mclk_src_sel == 0) {
717
718 snd_soc_component_update_bits(component,
719 CS42L42_PLL_CTL1,
720 CS42L42_PLL_START_MASK, 0);
721 } else {
722
723 snd_soc_component_update_bits(component,
724 CS42L42_PLL_DIV_CFG1,
725 CS42L42_SCLK_PREDIV_MASK,
726 pll_ratio_table[i].sclk_prediv
727 << CS42L42_SCLK_PREDIV_SHIFT);
728 snd_soc_component_update_bits(component,
729 CS42L42_PLL_DIV_INT,
730 CS42L42_PLL_DIV_INT_MASK,
731 pll_ratio_table[i].pll_div_int
732 << CS42L42_PLL_DIV_INT_SHIFT);
733 snd_soc_component_update_bits(component,
734 CS42L42_PLL_DIV_FRAC0,
735 CS42L42_PLL_DIV_FRAC_MASK,
736 CS42L42_FRAC0_VAL(
737 pll_ratio_table[i].pll_div_frac)
738 << CS42L42_PLL_DIV_FRAC_SHIFT);
739 snd_soc_component_update_bits(component,
740 CS42L42_PLL_DIV_FRAC1,
741 CS42L42_PLL_DIV_FRAC_MASK,
742 CS42L42_FRAC1_VAL(
743 pll_ratio_table[i].pll_div_frac)
744 << CS42L42_PLL_DIV_FRAC_SHIFT);
745 snd_soc_component_update_bits(component,
746 CS42L42_PLL_DIV_FRAC2,
747 CS42L42_PLL_DIV_FRAC_MASK,
748 CS42L42_FRAC2_VAL(
749 pll_ratio_table[i].pll_div_frac)
750 << CS42L42_PLL_DIV_FRAC_SHIFT);
751 snd_soc_component_update_bits(component,
752 CS42L42_PLL_CTL4,
753 CS42L42_PLL_MODE_MASK,
754 pll_ratio_table[i].pll_mode
755 << CS42L42_PLL_MODE_SHIFT);
756 snd_soc_component_update_bits(component,
757 CS42L42_PLL_CTL3,
758 CS42L42_PLL_DIVOUT_MASK,
759 pll_ratio_table[i].pll_divout
760 << CS42L42_PLL_DIVOUT_SHIFT);
761 snd_soc_component_update_bits(component,
762 CS42L42_PLL_CAL_RATIO,
763 CS42L42_PLL_CAL_RATIO_MASK,
764 pll_ratio_table[i].pll_cal_ratio
765 << CS42L42_PLL_CAL_RATIO_SHIFT);
766 }
767 return 0;
768 }
769 }
770
771 return -EINVAL;
772}
773
774static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
775{
776 struct snd_soc_component *component = codec_dai->component;
777 u32 asp_cfg_val = 0;
778
779 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
780 case SND_SOC_DAIFMT_CBS_CFM:
781 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
782 CS42L42_ASP_MODE_SHIFT;
783 break;
784 case SND_SOC_DAIFMT_CBS_CFS:
785 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
786 CS42L42_ASP_MODE_SHIFT;
787 break;
788 default:
789 return -EINVAL;
790 }
791
792
793 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
794 case SND_SOC_DAIFMT_I2S:
795 case SND_SOC_DAIFMT_LEFT_J:
796 break;
797 default:
798 return -EINVAL;
799 }
800
801
802 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
803 case SND_SOC_DAIFMT_NB_NF:
804 break;
805 case SND_SOC_DAIFMT_NB_IF:
806 asp_cfg_val |= CS42L42_ASP_POL_INV <<
807 CS42L42_ASP_LCPOL_IN_SHIFT;
808 break;
809 case SND_SOC_DAIFMT_IB_NF:
810 asp_cfg_val |= CS42L42_ASP_POL_INV <<
811 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
812 break;
813 case SND_SOC_DAIFMT_IB_IF:
814 asp_cfg_val |= CS42L42_ASP_POL_INV <<
815 CS42L42_ASP_LCPOL_IN_SHIFT;
816 asp_cfg_val |= CS42L42_ASP_POL_INV <<
817 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
818 break;
819 }
820
821 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG,
822 CS42L42_ASP_MODE_MASK |
823 CS42L42_ASP_SCPOL_IN_DAC_MASK |
824 CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val);
825
826 return 0;
827}
828
829static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
830 struct snd_pcm_hw_params *params,
831 struct snd_soc_dai *dai)
832{
833 struct snd_soc_component *component = dai->component;
834 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
835 int retval;
836
837 cs42l42->srate = params_rate(params);
838 cs42l42->swidth = params_width(params);
839
840 retval = cs42l42_pll_config(component);
841
842 return retval;
843}
844
845static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
846 int clk_id, unsigned int freq, int dir)
847{
848 struct snd_soc_component *component = dai->component;
849 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
850
851 cs42l42->sclk = freq;
852
853 return 0;
854}
855
856static int cs42l42_digital_mute(struct snd_soc_dai *dai, int mute)
857{
858 struct snd_soc_component *component = dai->component;
859 unsigned int regval;
860 u8 fullScaleVol;
861
862 if (mute) {
863
864
865
866 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
867 CS42L42_SCLK_PRESENT_MASK, 0);
868
869 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
870 CS42L42_PLL_START_MASK,
871 0 << CS42L42_PLL_START_SHIFT);
872
873
874 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
875 CS42L42_HP_ANA_AMUTE_MASK |
876 CS42L42_HP_ANA_BMUTE_MASK,
877 CS42L42_HP_ANA_AMUTE_MASK |
878 CS42L42_HP_ANA_BMUTE_MASK);
879 } else {
880 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
881 CS42L42_PLL_START_MASK,
882 1 << CS42L42_PLL_START_SHIFT);
883
884 regval = snd_soc_component_read32(component, CS42L42_LOAD_DET_RCSTAT);
885 if (((regval & CS42L42_RLA_STAT_MASK) >>
886 CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
887 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
888 } else {
889 fullScaleVol = 0;
890 }
891
892
893 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
894 CS42L42_HP_ANA_AMUTE_MASK |
895 CS42L42_HP_ANA_BMUTE_MASK |
896 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
897
898
899 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
900 CS42L42_SCLK_PRESENT_MASK,
901 CS42L42_SCLK_PRESENT_MASK);
902 }
903
904 return 0;
905}
906
907#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
908 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
909 SNDRV_PCM_FMTBIT_S32_LE)
910
911
912static const struct snd_soc_dai_ops cs42l42_ops = {
913 .hw_params = cs42l42_pcm_hw_params,
914 .set_fmt = cs42l42_set_dai_fmt,
915 .set_sysclk = cs42l42_set_sysclk,
916 .digital_mute = cs42l42_digital_mute
917};
918
919static struct snd_soc_dai_driver cs42l42_dai = {
920 .name = "cs42l42",
921 .playback = {
922 .stream_name = "Playback",
923 .channels_min = 1,
924 .channels_max = 2,
925 .rates = SNDRV_PCM_RATE_8000_192000,
926 .formats = CS42L42_FORMATS,
927 },
928 .capture = {
929 .stream_name = "Capture",
930 .channels_min = 1,
931 .channels_max = 2,
932 .rates = SNDRV_PCM_RATE_8000_192000,
933 .formats = CS42L42_FORMATS,
934 },
935 .ops = &cs42l42_ops,
936};
937
938static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
939{
940 unsigned int hs_det_status;
941 unsigned int int_status;
942
943
944 regmap_update_bits(cs42l42->regmap,
945 CS42L42_CODEC_INT_MASK,
946 CS42L42_PDN_DONE_MASK |
947 CS42L42_HSDET_AUTO_DONE_MASK,
948 (1 << CS42L42_PDN_DONE_SHIFT) |
949 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
950
951
952 regmap_update_bits(cs42l42->regmap,
953 CS42L42_HSDET_CTL2,
954 CS42L42_HSDET_CTRL_MASK |
955 CS42L42_HSDET_SET_MASK |
956 CS42L42_HSBIAS_REF_MASK |
957 CS42L42_HSDET_AUTO_TIME_MASK,
958 (2 << CS42L42_HSDET_CTRL_SHIFT) |
959 (2 << CS42L42_HSDET_SET_SHIFT) |
960 (0 << CS42L42_HSBIAS_REF_SHIFT) |
961 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
962
963
964 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
965
966 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
967 CS42L42_HSDET_TYPE_SHIFT;
968
969
970 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
971 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
972
973 regmap_update_bits(cs42l42->regmap,
974 CS42L42_HSBIAS_SC_AUTOCTL,
975 CS42L42_HSBIAS_SENSE_EN_MASK |
976 CS42L42_AUTO_HSBIAS_HIZ_MASK |
977 CS42L42_TIP_SENSE_EN_MASK |
978 CS42L42_HSBIAS_SENSE_TRIP_MASK,
979 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
980 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
981 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
982 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
983
984
985 regmap_update_bits(cs42l42->regmap,
986 CS42L42_MIC_DET_CTL1,
987 CS42L42_LATCH_TO_VP_MASK |
988 CS42L42_EVENT_STAT_SEL_MASK |
989 CS42L42_HS_DET_LEVEL_MASK,
990 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
991 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
992 (cs42l42->bias_thresholds[0] <<
993 CS42L42_HS_DET_LEVEL_SHIFT));
994
995
996 regmap_update_bits(cs42l42->regmap,
997 CS42L42_HSBIAS_SC_AUTOCTL,
998 CS42L42_HSBIAS_SENSE_EN_MASK |
999 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1000 CS42L42_TIP_SENSE_EN_MASK |
1001 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1002 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1003 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1004 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1005 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1006
1007
1008 regmap_update_bits(cs42l42->regmap,
1009 CS42L42_MISC_DET_CTL,
1010 CS42L42_DETECT_MODE_MASK |
1011 CS42L42_HSBIAS_CTL_MASK |
1012 CS42L42_PDN_MIC_LVL_DET_MASK,
1013 (0 << CS42L42_DETECT_MODE_SHIFT) |
1014 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1015 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1016
1017 msleep(cs42l42->btn_det_init_dbnce);
1018
1019
1020 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1021 &int_status);
1022
1023
1024 regmap_update_bits(cs42l42->regmap,
1025 CS42L42_DET_INT2_MASK,
1026 CS42L42_M_DETECT_TF_MASK |
1027 CS42L42_M_DETECT_FT_MASK |
1028 CS42L42_M_HSBIAS_HIZ_MASK |
1029 CS42L42_M_SHORT_RLS_MASK |
1030 CS42L42_M_SHORT_DET_MASK,
1031 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1032 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1033 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1034 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1035 (1 << CS42L42_M_SHORT_DET_SHIFT));
1036 } else {
1037
1038 regmap_update_bits(cs42l42->regmap,
1039 CS42L42_MISC_DET_CTL,
1040 CS42L42_DETECT_MODE_MASK |
1041 CS42L42_HSBIAS_CTL_MASK |
1042 CS42L42_PDN_MIC_LVL_DET_MASK,
1043 (0 << CS42L42_DETECT_MODE_SHIFT) |
1044 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1045 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1046 }
1047
1048 regmap_update_bits(cs42l42->regmap,
1049 CS42L42_DAC_CTL2,
1050 CS42L42_HPOUT_PULLDOWN_MASK |
1051 CS42L42_HPOUT_LOAD_MASK |
1052 CS42L42_HPOUT_CLAMP_MASK |
1053 CS42L42_DAC_HPF_EN_MASK |
1054 CS42L42_DAC_MON_EN_MASK,
1055 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1056 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1057 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1058 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1059 (0 << CS42L42_DAC_MON_EN_SHIFT));
1060
1061
1062 regmap_update_bits(cs42l42->regmap,
1063 CS42L42_TSRS_PLUG_INT_MASK,
1064 CS42L42_RS_PLUG_MASK |
1065 CS42L42_RS_UNPLUG_MASK |
1066 CS42L42_TS_PLUG_MASK |
1067 CS42L42_TS_UNPLUG_MASK,
1068 (1 << CS42L42_RS_PLUG_SHIFT) |
1069 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1070 (0 << CS42L42_TS_PLUG_SHIFT) |
1071 (0 << CS42L42_TS_UNPLUG_SHIFT));
1072}
1073
1074static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1075{
1076
1077 regmap_update_bits(cs42l42->regmap,
1078 CS42L42_TSRS_PLUG_INT_MASK,
1079 CS42L42_RS_PLUG_MASK |
1080 CS42L42_RS_UNPLUG_MASK |
1081 CS42L42_TS_PLUG_MASK |
1082 CS42L42_TS_UNPLUG_MASK,
1083 (1 << CS42L42_RS_PLUG_SHIFT) |
1084 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1085 (1 << CS42L42_TS_PLUG_SHIFT) |
1086 (1 << CS42L42_TS_UNPLUG_SHIFT));
1087
1088
1089 regmap_update_bits(cs42l42->regmap,
1090 CS42L42_MISC_DET_CTL,
1091 CS42L42_DETECT_MODE_MASK |
1092 CS42L42_HSBIAS_CTL_MASK |
1093 CS42L42_PDN_MIC_LVL_DET_MASK,
1094 (0 << CS42L42_DETECT_MODE_SHIFT) |
1095 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1096 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1097
1098
1099 regmap_update_bits(cs42l42->regmap,
1100 CS42L42_HSBIAS_SC_AUTOCTL,
1101 CS42L42_HSBIAS_SENSE_EN_MASK |
1102 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1103 CS42L42_TIP_SENSE_EN_MASK |
1104 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1105 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1106 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1107 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1108 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1109
1110
1111 regmap_update_bits(cs42l42->regmap,
1112 CS42L42_HSDET_CTL2,
1113 CS42L42_HSDET_CTRL_MASK |
1114 CS42L42_HSDET_SET_MASK |
1115 CS42L42_HSBIAS_REF_MASK |
1116 CS42L42_HSDET_AUTO_TIME_MASK,
1117 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1118 (2 << CS42L42_HSDET_SET_SHIFT) |
1119 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1120 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1121
1122 regmap_update_bits(cs42l42->regmap,
1123 CS42L42_DAC_CTL2,
1124 CS42L42_HPOUT_PULLDOWN_MASK |
1125 CS42L42_HPOUT_LOAD_MASK |
1126 CS42L42_HPOUT_CLAMP_MASK |
1127 CS42L42_DAC_HPF_EN_MASK |
1128 CS42L42_DAC_MON_EN_MASK,
1129 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1130 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1131 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1132 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1133 (1 << CS42L42_DAC_MON_EN_SHIFT));
1134
1135
1136 regmap_update_bits(cs42l42->regmap,
1137 CS42L42_MISC_DET_CTL,
1138 CS42L42_DETECT_MODE_MASK |
1139 CS42L42_HSBIAS_CTL_MASK |
1140 CS42L42_PDN_MIC_LVL_DET_MASK,
1141 (0 << CS42L42_DETECT_MODE_SHIFT) |
1142 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1143 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1144
1145
1146 msleep(cs42l42->hs_bias_ramp_time);
1147
1148
1149 regmap_update_bits(cs42l42->regmap,
1150 CS42L42_CODEC_INT_MASK,
1151 CS42L42_PDN_DONE_MASK |
1152 CS42L42_HSDET_AUTO_DONE_MASK,
1153 (1 << CS42L42_PDN_DONE_SHIFT) |
1154 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1155
1156
1157 regmap_update_bits(cs42l42->regmap,
1158 CS42L42_HSDET_CTL2,
1159 CS42L42_HSDET_CTRL_MASK |
1160 CS42L42_HSDET_SET_MASK |
1161 CS42L42_HSBIAS_REF_MASK |
1162 CS42L42_HSDET_AUTO_TIME_MASK,
1163 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1164 (2 << CS42L42_HSDET_SET_SHIFT) |
1165 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1166 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1167}
1168
1169static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1170{
1171
1172 regmap_update_bits(cs42l42->regmap,
1173 CS42L42_DET_INT2_MASK,
1174 CS42L42_M_DETECT_TF_MASK |
1175 CS42L42_M_DETECT_FT_MASK |
1176 CS42L42_M_HSBIAS_HIZ_MASK |
1177 CS42L42_M_SHORT_RLS_MASK |
1178 CS42L42_M_SHORT_DET_MASK,
1179 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1180 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1181 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1182 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1183 (1 << CS42L42_M_SHORT_DET_SHIFT));
1184
1185
1186 regmap_update_bits(cs42l42->regmap,
1187 CS42L42_MISC_DET_CTL,
1188 CS42L42_DETECT_MODE_MASK |
1189 CS42L42_HSBIAS_CTL_MASK |
1190 CS42L42_PDN_MIC_LVL_DET_MASK,
1191 (0 << CS42L42_DETECT_MODE_SHIFT) |
1192 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1193 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1194
1195
1196 regmap_update_bits(cs42l42->regmap,
1197 CS42L42_HSBIAS_SC_AUTOCTL,
1198 CS42L42_HSBIAS_SENSE_EN_MASK |
1199 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1200 CS42L42_TIP_SENSE_EN_MASK |
1201 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1202 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1203 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1204 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1205 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1206
1207
1208 regmap_update_bits(cs42l42->regmap,
1209 CS42L42_HSDET_CTL2,
1210 CS42L42_HSDET_CTRL_MASK |
1211 CS42L42_HSDET_SET_MASK |
1212 CS42L42_HSBIAS_REF_MASK |
1213 CS42L42_HSDET_AUTO_TIME_MASK,
1214 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1215 (2 << CS42L42_HSDET_SET_SHIFT) |
1216 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1217 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1218}
1219
1220static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1221{
1222 int bias_level;
1223 unsigned int detect_status;
1224
1225
1226 regmap_update_bits(cs42l42->regmap,
1227 CS42L42_DET_INT2_MASK,
1228 CS42L42_M_DETECT_TF_MASK |
1229 CS42L42_M_DETECT_FT_MASK |
1230 CS42L42_M_HSBIAS_HIZ_MASK |
1231 CS42L42_M_SHORT_RLS_MASK |
1232 CS42L42_M_SHORT_DET_MASK,
1233 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1234 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1235 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1236 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1237 (1 << CS42L42_M_SHORT_DET_SHIFT));
1238
1239 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1240 cs42l42->btn_det_event_dbnce * 2000);
1241
1242
1243 bias_level = 1;
1244 do {
1245
1246 regmap_update_bits(cs42l42->regmap,
1247 CS42L42_MIC_DET_CTL1,
1248 CS42L42_LATCH_TO_VP_MASK |
1249 CS42L42_EVENT_STAT_SEL_MASK |
1250 CS42L42_HS_DET_LEVEL_MASK,
1251 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1252 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1253 (cs42l42->bias_thresholds[bias_level] <<
1254 CS42L42_HS_DET_LEVEL_SHIFT));
1255
1256 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1257 &detect_status);
1258 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1259 (++bias_level < CS42L42_NUM_BIASES));
1260
1261 switch (bias_level) {
1262 case 1:
1263 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1264 break;
1265 case 2:
1266 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1267 break;
1268 case 3:
1269 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1270 break;
1271 case 4:
1272 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1273 break;
1274 }
1275
1276
1277 regmap_update_bits(cs42l42->regmap,
1278 CS42L42_MIC_DET_CTL1,
1279 CS42L42_LATCH_TO_VP_MASK |
1280 CS42L42_EVENT_STAT_SEL_MASK |
1281 CS42L42_HS_DET_LEVEL_MASK,
1282 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1283 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1284 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1285
1286
1287 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1288 &detect_status);
1289
1290
1291 regmap_update_bits(cs42l42->regmap,
1292 CS42L42_DET_INT2_MASK,
1293 CS42L42_M_DETECT_TF_MASK |
1294 CS42L42_M_DETECT_FT_MASK |
1295 CS42L42_M_HSBIAS_HIZ_MASK |
1296 CS42L42_M_SHORT_RLS_MASK |
1297 CS42L42_M_SHORT_DET_MASK,
1298 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1299 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1300 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1301 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1302 (1 << CS42L42_M_SHORT_DET_SHIFT));
1303}
1304
1305struct cs42l42_irq_params {
1306 u16 status_addr;
1307 u16 mask_addr;
1308 u8 mask;
1309};
1310
1311static const struct cs42l42_irq_params irq_params_table[] = {
1312 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1313 CS42L42_ADC_OVFL_VAL_MASK},
1314 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1315 CS42L42_MIXER_VAL_MASK},
1316 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1317 CS42L42_SRC_VAL_MASK},
1318 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1319 CS42L42_ASP_RX_VAL_MASK},
1320 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1321 CS42L42_ASP_TX_VAL_MASK},
1322 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1323 CS42L42_CODEC_VAL_MASK},
1324 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1325 CS42L42_DET_INT_VAL1_MASK},
1326 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1327 CS42L42_DET_INT_VAL2_MASK},
1328 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1329 CS42L42_SRCPL_VAL_MASK},
1330 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1331 CS42L42_VPMON_VAL_MASK},
1332 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1333 CS42L42_PLL_LOCK_VAL_MASK},
1334 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1335 CS42L42_TSRS_PLUG_VAL_MASK}
1336};
1337
1338static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1339{
1340 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1341 struct snd_soc_component *component = cs42l42->component;
1342 unsigned int stickies[12];
1343 unsigned int masks[12];
1344 unsigned int current_plug_status;
1345 unsigned int current_button_status;
1346 unsigned int i;
1347
1348
1349 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1350 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1351 &(stickies[i]));
1352 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1353 &(masks[i]));
1354 stickies[i] = stickies[i] & (~masks[i]) &
1355 irq_params_table[i].mask;
1356 }
1357
1358
1359 current_plug_status = (stickies[11] &
1360 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1361 CS42L42_TS_PLUG_SHIFT;
1362
1363
1364 current_button_status = stickies[7] &
1365 (CS42L42_M_DETECT_TF_MASK |
1366 CS42L42_M_DETECT_FT_MASK |
1367 CS42L42_M_HSBIAS_HIZ_MASK);
1368
1369
1370 if ((~masks[5]) & irq_params_table[5].mask) {
1371 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1372 cs42l42_process_hs_type_detect(cs42l42);
1373 dev_dbg(component->dev,
1374 "Auto detect done (%d)\n",
1375 cs42l42->hs_type);
1376 }
1377 }
1378
1379
1380 if ((~masks[11]) & irq_params_table[11].mask) {
1381 switch (current_plug_status) {
1382 case CS42L42_TS_PLUG:
1383 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1384 cs42l42->plug_state = CS42L42_TS_PLUG;
1385 cs42l42_init_hs_type_detect(cs42l42);
1386 }
1387 break;
1388
1389 case CS42L42_TS_UNPLUG:
1390 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1391 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1392 cs42l42_cancel_hs_type_detect(cs42l42);
1393 dev_dbg(component->dev,
1394 "Unplug event\n");
1395 }
1396 break;
1397
1398 default:
1399 if (cs42l42->plug_state != CS42L42_TS_TRANS)
1400 cs42l42->plug_state = CS42L42_TS_TRANS;
1401 }
1402 }
1403
1404
1405 if ((~masks[7]) & irq_params_table[7].mask) {
1406 if (!(current_button_status &
1407 CS42L42_M_HSBIAS_HIZ_MASK)) {
1408
1409 if (current_button_status &
1410 CS42L42_M_DETECT_TF_MASK) {
1411 dev_dbg(component->dev,
1412 "Button released\n");
1413 } else if (current_button_status &
1414 CS42L42_M_DETECT_FT_MASK) {
1415 cs42l42_handle_button_press(cs42l42);
1416 }
1417 }
1418 }
1419
1420 return IRQ_HANDLED;
1421}
1422
1423static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1424{
1425 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1426 CS42L42_ADC_OVFL_MASK,
1427 (1 << CS42L42_ADC_OVFL_SHIFT));
1428
1429 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1430 CS42L42_MIX_CHB_OVFL_MASK |
1431 CS42L42_MIX_CHA_OVFL_MASK |
1432 CS42L42_EQ_OVFL_MASK |
1433 CS42L42_EQ_BIQUAD_OVFL_MASK,
1434 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1435 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1436 (1 << CS42L42_EQ_OVFL_SHIFT) |
1437 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1438
1439 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1440 CS42L42_SRC_ILK_MASK |
1441 CS42L42_SRC_OLK_MASK |
1442 CS42L42_SRC_IUNLK_MASK |
1443 CS42L42_SRC_OUNLK_MASK,
1444 (1 << CS42L42_SRC_ILK_SHIFT) |
1445 (1 << CS42L42_SRC_OLK_SHIFT) |
1446 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1447 (1 << CS42L42_SRC_OUNLK_SHIFT));
1448
1449 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1450 CS42L42_ASPRX_NOLRCK_MASK |
1451 CS42L42_ASPRX_EARLY_MASK |
1452 CS42L42_ASPRX_LATE_MASK |
1453 CS42L42_ASPRX_ERROR_MASK |
1454 CS42L42_ASPRX_OVLD_MASK,
1455 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1456 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1457 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1458 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1459 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1460
1461 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1462 CS42L42_ASPTX_NOLRCK_MASK |
1463 CS42L42_ASPTX_EARLY_MASK |
1464 CS42L42_ASPTX_LATE_MASK |
1465 CS42L42_ASPTX_SMERROR_MASK,
1466 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1467 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1468 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1469 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1470
1471 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1472 CS42L42_PDN_DONE_MASK |
1473 CS42L42_HSDET_AUTO_DONE_MASK,
1474 (1 << CS42L42_PDN_DONE_SHIFT) |
1475 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1476
1477 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1478 CS42L42_SRCPL_ADC_LK_MASK |
1479 CS42L42_SRCPL_DAC_LK_MASK |
1480 CS42L42_SRCPL_ADC_UNLK_MASK |
1481 CS42L42_SRCPL_DAC_UNLK_MASK,
1482 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1483 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1484 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1485 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1486
1487 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1488 CS42L42_TIP_SENSE_UNPLUG_MASK |
1489 CS42L42_TIP_SENSE_PLUG_MASK |
1490 CS42L42_HSBIAS_SENSE_MASK,
1491 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1492 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1493 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1494
1495 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1496 CS42L42_M_DETECT_TF_MASK |
1497 CS42L42_M_DETECT_FT_MASK |
1498 CS42L42_M_HSBIAS_HIZ_MASK |
1499 CS42L42_M_SHORT_RLS_MASK |
1500 CS42L42_M_SHORT_DET_MASK,
1501 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1502 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1503 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1504 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1505 (1 << CS42L42_M_SHORT_DET_SHIFT));
1506
1507 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1508 CS42L42_VPMON_MASK,
1509 (1 << CS42L42_VPMON_SHIFT));
1510
1511 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1512 CS42L42_PLL_LOCK_MASK,
1513 (1 << CS42L42_PLL_LOCK_SHIFT));
1514
1515 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1516 CS42L42_RS_PLUG_MASK |
1517 CS42L42_RS_UNPLUG_MASK |
1518 CS42L42_TS_PLUG_MASK |
1519 CS42L42_TS_UNPLUG_MASK,
1520 (1 << CS42L42_RS_PLUG_SHIFT) |
1521 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1522 (0 << CS42L42_TS_PLUG_SHIFT) |
1523 (0 << CS42L42_TS_UNPLUG_SHIFT));
1524}
1525
1526static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1527{
1528 unsigned int reg;
1529
1530 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1531
1532
1533 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1534 CS42L42_LATCH_TO_VP_MASK |
1535 CS42L42_EVENT_STAT_SEL_MASK |
1536 CS42L42_HS_DET_LEVEL_MASK,
1537 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1538 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1539 (cs42l42->bias_thresholds[0] <<
1540 CS42L42_HS_DET_LEVEL_SHIFT));
1541
1542
1543 regmap_update_bits(cs42l42->regmap,
1544 CS42L42_HS_CLAMP_DISABLE,
1545 CS42L42_HS_CLAMP_DISABLE_MASK,
1546 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1547
1548
1549 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1550 CS42L42_TIP_SENSE_CTRL_MASK |
1551 CS42L42_TIP_SENSE_INV_MASK |
1552 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1553 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1554 (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1555 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1556
1557
1558 regmap_read(cs42l42->regmap,
1559 CS42L42_TSRS_PLUG_STATUS,
1560 ®);
1561 cs42l42->plug_state = (((char) reg) &
1562 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1563 CS42L42_TS_PLUG_SHIFT;
1564}
1565
1566static const unsigned int threshold_defaults[] = {
1567 CS42L42_HS_DET_LEVEL_15,
1568 CS42L42_HS_DET_LEVEL_8,
1569 CS42L42_HS_DET_LEVEL_4,
1570 CS42L42_HS_DET_LEVEL_1
1571};
1572
1573static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1574 struct cs42l42_private *cs42l42)
1575{
1576 struct device_node *np = i2c_client->dev.of_node;
1577 unsigned int val;
1578 unsigned int thresholds[CS42L42_NUM_BIASES];
1579 int ret;
1580 int i;
1581
1582 ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1583
1584 if (!ret) {
1585 switch (val) {
1586 case CS42L42_TS_INV_EN:
1587 case CS42L42_TS_INV_DIS:
1588 cs42l42->ts_inv = val;
1589 break;
1590 default:
1591 dev_err(&i2c_client->dev,
1592 "Wrong cirrus,ts-inv DT value %d\n",
1593 val);
1594 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1595 }
1596 } else {
1597 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1598 }
1599
1600 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1601 CS42L42_TS_INV_MASK,
1602 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1603
1604 ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1605
1606 if (!ret) {
1607 switch (val) {
1608 case CS42L42_TS_DBNCE_0:
1609 case CS42L42_TS_DBNCE_125:
1610 case CS42L42_TS_DBNCE_250:
1611 case CS42L42_TS_DBNCE_500:
1612 case CS42L42_TS_DBNCE_750:
1613 case CS42L42_TS_DBNCE_1000:
1614 case CS42L42_TS_DBNCE_1250:
1615 case CS42L42_TS_DBNCE_1500:
1616 cs42l42->ts_dbnc_rise = val;
1617 break;
1618 default:
1619 dev_err(&i2c_client->dev,
1620 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1621 val);
1622 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1623 }
1624 } else {
1625 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1626 }
1627
1628 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1629 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1630 (cs42l42->ts_dbnc_rise <<
1631 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1632
1633 ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1634
1635 if (!ret) {
1636 switch (val) {
1637 case CS42L42_TS_DBNCE_0:
1638 case CS42L42_TS_DBNCE_125:
1639 case CS42L42_TS_DBNCE_250:
1640 case CS42L42_TS_DBNCE_500:
1641 case CS42L42_TS_DBNCE_750:
1642 case CS42L42_TS_DBNCE_1000:
1643 case CS42L42_TS_DBNCE_1250:
1644 case CS42L42_TS_DBNCE_1500:
1645 cs42l42->ts_dbnc_fall = val;
1646 break;
1647 default:
1648 dev_err(&i2c_client->dev,
1649 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1650 val);
1651 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1652 }
1653 } else {
1654 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1655 }
1656
1657 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1658 CS42L42_TS_FALL_DBNCE_TIME_MASK,
1659 (cs42l42->ts_dbnc_fall <<
1660 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1661
1662 ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1663
1664 if (!ret) {
1665 if ((val >= CS42L42_BTN_DET_INIT_DBNCE_MIN) &&
1666 (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX))
1667 cs42l42->btn_det_init_dbnce = val;
1668 else {
1669 dev_err(&i2c_client->dev,
1670 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1671 val);
1672 cs42l42->btn_det_init_dbnce =
1673 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1674 }
1675 } else {
1676 cs42l42->btn_det_init_dbnce =
1677 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1678 }
1679
1680 ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1681
1682 if (!ret) {
1683 if ((val >= CS42L42_BTN_DET_EVENT_DBNCE_MIN) &&
1684 (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX))
1685 cs42l42->btn_det_event_dbnce = val;
1686 else {
1687 dev_err(&i2c_client->dev,
1688 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1689 cs42l42->btn_det_event_dbnce =
1690 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1691 }
1692 } else {
1693 cs42l42->btn_det_event_dbnce =
1694 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1695 }
1696
1697 ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1698 (u32 *)thresholds, CS42L42_NUM_BIASES);
1699
1700 if (!ret) {
1701 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1702 if ((thresholds[i] >= CS42L42_HS_DET_LEVEL_MIN) &&
1703 (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX))
1704 cs42l42->bias_thresholds[i] = thresholds[i];
1705 else {
1706 dev_err(&i2c_client->dev,
1707 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1708 thresholds[i]);
1709 cs42l42->bias_thresholds[i] =
1710 threshold_defaults[i];
1711 }
1712 }
1713 } else {
1714 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1715 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1716 }
1717
1718 ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1719
1720 if (!ret) {
1721 switch (val) {
1722 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1723 cs42l42->hs_bias_ramp_rate = val;
1724 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1725 break;
1726 case CS42L42_HSBIAS_RAMP_FAST:
1727 cs42l42->hs_bias_ramp_rate = val;
1728 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1729 break;
1730 case CS42L42_HSBIAS_RAMP_SLOW:
1731 cs42l42->hs_bias_ramp_rate = val;
1732 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1733 break;
1734 case CS42L42_HSBIAS_RAMP_SLOWEST:
1735 cs42l42->hs_bias_ramp_rate = val;
1736 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1737 break;
1738 default:
1739 dev_err(&i2c_client->dev,
1740 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1741 val);
1742 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1743 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1744 }
1745 } else {
1746 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1747 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1748 }
1749
1750 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1751 CS42L42_HSBIAS_RAMP_MASK,
1752 (cs42l42->hs_bias_ramp_rate <<
1753 CS42L42_HSBIAS_RAMP_SHIFT));
1754
1755 return 0;
1756}
1757
1758static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1759 const struct i2c_device_id *id)
1760{
1761 struct cs42l42_private *cs42l42;
1762 int ret, i;
1763 unsigned int devid = 0;
1764 unsigned int reg;
1765
1766 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1767 GFP_KERNEL);
1768 if (!cs42l42)
1769 return -ENOMEM;
1770
1771 i2c_set_clientdata(i2c_client, cs42l42);
1772
1773 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1774 if (IS_ERR(cs42l42->regmap)) {
1775 ret = PTR_ERR(cs42l42->regmap);
1776 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1777 return ret;
1778 }
1779
1780 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1781 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1782
1783 ret = devm_regulator_bulk_get(&i2c_client->dev,
1784 ARRAY_SIZE(cs42l42->supplies),
1785 cs42l42->supplies);
1786 if (ret != 0) {
1787 dev_err(&i2c_client->dev,
1788 "Failed to request supplies: %d\n", ret);
1789 return ret;
1790 }
1791
1792 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1793 cs42l42->supplies);
1794 if (ret != 0) {
1795 dev_err(&i2c_client->dev,
1796 "Failed to enable supplies: %d\n", ret);
1797 return ret;
1798 }
1799
1800
1801 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1802 "reset", GPIOD_OUT_LOW);
1803 if (IS_ERR(cs42l42->reset_gpio))
1804 return PTR_ERR(cs42l42->reset_gpio);
1805
1806 if (cs42l42->reset_gpio) {
1807 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1808 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1809 }
1810 mdelay(3);
1811
1812
1813 ret = devm_request_threaded_irq(&i2c_client->dev,
1814 i2c_client->irq,
1815 NULL, cs42l42_irq_thread,
1816 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1817 "cs42l42", cs42l42);
1818
1819 if (ret != 0)
1820 dev_err(&i2c_client->dev,
1821 "Failed to request IRQ: %d\n", ret);
1822
1823
1824 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®);
1825 devid = (reg & 0xFF) << 12;
1826
1827 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®);
1828 devid |= (reg & 0xFF) << 4;
1829
1830 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®);
1831 devid |= (reg & 0xF0) >> 4;
1832
1833 if (devid != CS42L42_CHIP_ID) {
1834 ret = -ENODEV;
1835 dev_err(&i2c_client->dev,
1836 "CS42L42 Device ID (%X). Expected %X\n",
1837 devid, CS42L42_CHIP_ID);
1838 return ret;
1839 }
1840
1841 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
1842 if (ret < 0) {
1843 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1844 return ret;
1845 }
1846
1847 dev_info(&i2c_client->dev,
1848 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1849
1850
1851 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1852 CS42L42_ASP_DAO_PDN_MASK |
1853 CS42L42_ASP_DAI_PDN_MASK |
1854 CS42L42_MIXER_PDN_MASK |
1855 CS42L42_EQ_PDN_MASK |
1856 CS42L42_HP_PDN_MASK |
1857 CS42L42_ADC_PDN_MASK |
1858 CS42L42_PDN_ALL_MASK,
1859 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1860 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1861 (1 << CS42L42_MIXER_PDN_SHIFT) |
1862 (1 << CS42L42_EQ_PDN_SHIFT) |
1863 (1 << CS42L42_HP_PDN_SHIFT) |
1864 (1 << CS42L42_ADC_PDN_SHIFT) |
1865 (0 << CS42L42_PDN_ALL_SHIFT));
1866
1867 if (i2c_client->dev.of_node) {
1868 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1869 if (ret != 0)
1870 return ret;
1871 }
1872
1873
1874 cs42l42_setup_hs_type_detect(cs42l42);
1875
1876
1877 cs42l42_set_interrupt_masks(cs42l42);
1878
1879
1880 ret = devm_snd_soc_register_component(&i2c_client->dev,
1881 &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1882 if (ret < 0)
1883 goto err_disable;
1884 return 0;
1885
1886err_disable:
1887 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1888 cs42l42->supplies);
1889 return ret;
1890}
1891
1892static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1893{
1894 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1895
1896
1897 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1898
1899 return 0;
1900}
1901
1902#ifdef CONFIG_PM
1903static int cs42l42_runtime_suspend(struct device *dev)
1904{
1905 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1906
1907 regcache_cache_only(cs42l42->regmap, true);
1908 regcache_mark_dirty(cs42l42->regmap);
1909
1910
1911 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1912
1913
1914 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1915 cs42l42->supplies);
1916
1917 return 0;
1918}
1919
1920static int cs42l42_runtime_resume(struct device *dev)
1921{
1922 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1923 int ret;
1924
1925
1926 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1927 cs42l42->supplies);
1928 if (ret != 0) {
1929 dev_err(dev, "Failed to enable supplies: %d\n",
1930 ret);
1931 return ret;
1932 }
1933
1934 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1935
1936 regcache_cache_only(cs42l42->regmap, false);
1937 regcache_sync(cs42l42->regmap);
1938
1939 return 0;
1940}
1941#endif
1942
1943static const struct dev_pm_ops cs42l42_runtime_pm = {
1944 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1945 NULL)
1946};
1947
1948static const struct of_device_id cs42l42_of_match[] = {
1949 { .compatible = "cirrus,cs42l42", },
1950 {},
1951};
1952MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1953
1954
1955static const struct i2c_device_id cs42l42_id[] = {
1956 {"cs42l42", 0},
1957 {}
1958};
1959
1960MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1961
1962static struct i2c_driver cs42l42_i2c_driver = {
1963 .driver = {
1964 .name = "cs42l42",
1965 .pm = &cs42l42_runtime_pm,
1966 .of_match_table = cs42l42_of_match,
1967 },
1968 .id_table = cs42l42_id,
1969 .probe = cs42l42_i2c_probe,
1970 .remove = cs42l42_i2c_remove,
1971};
1972
1973module_i2c_driver(cs42l42_i2c_driver);
1974
1975MODULE_DESCRIPTION("ASoC CS42L42 driver");
1976MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1977MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1978MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1979MODULE_LICENSE("GPL");
1980
