1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/regmap.h>
20
21#include <linux/delay.h>
22
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/initval.h>
27#include <sound/soc.h>
28#include <sound/tlv.h>
29
30#define JZ4740_REG_CODEC_1 0x0
31#define JZ4740_REG_CODEC_2 0x4
32
33#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
34#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
35#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
36#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
37#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
38#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
39#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
40#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
41#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
42#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
43#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
44#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
45#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
46#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
47#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
48#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
49#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
50#define JZ4740_CODEC_1_SUSPEND BIT(1)
51#define JZ4740_CODEC_1_RESET BIT(0)
52
53#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
54#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
55#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
56#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
57#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
58#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
59#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
60#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
61
62#define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
63#define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
64#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
65#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
66
67#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
68#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
69#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
70#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
71
72static const struct reg_default jz4740_codec_reg_defaults[] = {
73 { JZ4740_REG_CODEC_1, 0x021b2302 },
74 { JZ4740_REG_CODEC_2, 0x00170803 },
75};
76
77struct jz4740_codec {
78 struct regmap *regmap;
79};
80
81static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv,
82 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
83 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0)
84);
85
86static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
87static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
88
89static const struct snd_kcontrol_new jz4740_codec_controls[] = {
90 SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
91 JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
92 jz4740_out_tlv),
93 SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
94 JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
95 jz4740_in_tlv),
96 SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
97 JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
98 SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
99 JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
100 jz4740_mic_tlv),
101};
102
103static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
104 SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
105 JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
106 SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
107 JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
108};
109
110static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
111 SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
112 JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
113 SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
114 JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
115};
116
117static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
118 SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
119 JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
120 SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
121 JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
122
123 SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
124 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
125 jz4740_codec_output_controls,
126 ARRAY_SIZE(jz4740_codec_output_controls)),
127
128 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
129 jz4740_codec_input_controls,
130 ARRAY_SIZE(jz4740_codec_input_controls)),
131 SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
132
133 SND_SOC_DAPM_OUTPUT("LOUT"),
134 SND_SOC_DAPM_OUTPUT("ROUT"),
135
136 SND_SOC_DAPM_INPUT("MIC"),
137 SND_SOC_DAPM_INPUT("LIN"),
138 SND_SOC_DAPM_INPUT("RIN"),
139};
140
141static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
142 {"Line Input", NULL, "LIN"},
143 {"Line Input", NULL, "RIN"},
144
145 {"Input Mixer", "Line Capture Switch", "Line Input"},
146 {"Input Mixer", "Mic Capture Switch", "MIC"},
147
148 {"ADC", NULL, "Input Mixer"},
149
150 {"Output Mixer", "Bypass Switch", "Input Mixer"},
151 {"Output Mixer", "DAC Switch", "DAC"},
152
153 {"LOUT", NULL, "Output Mixer"},
154 {"ROUT", NULL, "Output Mixer"},
155};
156
157static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
158 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
159{
160 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(dai->component);
161 uint32_t val;
162
163 switch (params_rate(params)) {
164 case 8000:
165 val = 0;
166 break;
167 case 11025:
168 val = 1;
169 break;
170 case 12000:
171 val = 2;
172 break;
173 case 16000:
174 val = 3;
175 break;
176 case 22050:
177 val = 4;
178 break;
179 case 24000:
180 val = 5;
181 break;
182 case 32000:
183 val = 6;
184 break;
185 case 44100:
186 val = 7;
187 break;
188 case 48000:
189 val = 8;
190 break;
191 default:
192 return -EINVAL;
193 }
194
195 val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
196
197 regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
198 JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
199
200 return 0;
201}
202
203static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
204 .hw_params = jz4740_codec_hw_params,
205};
206
207static struct snd_soc_dai_driver jz4740_codec_dai = {
208 .name = "jz4740-hifi",
209 .playback = {
210 .stream_name = "Playback",
211 .channels_min = 2,
212 .channels_max = 2,
213 .rates = SNDRV_PCM_RATE_8000_48000,
214 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
215 },
216 .capture = {
217 .stream_name = "Capture",
218 .channels_min = 2,
219 .channels_max = 2,
220 .rates = SNDRV_PCM_RATE_8000_48000,
221 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
222 },
223 .ops = &jz4740_codec_dai_ops,
224 .symmetric_rates = 1,
225};
226
227static void jz4740_codec_wakeup(struct regmap *regmap)
228{
229 regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
230 JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
231 udelay(2);
232
233 regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
234 JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
235
236 regcache_sync(regmap);
237}
238
239static int jz4740_codec_set_bias_level(struct snd_soc_component *component,
240 enum snd_soc_bias_level level)
241{
242 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
243 struct regmap *regmap = jz4740_codec->regmap;
244 unsigned int mask;
245 unsigned int value;
246
247 switch (level) {
248 case SND_SOC_BIAS_ON:
249 break;
250 case SND_SOC_BIAS_PREPARE:
251 mask = JZ4740_CODEC_1_VREF_DISABLE |
252 JZ4740_CODEC_1_VREF_AMP_DISABLE |
253 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
254 value = 0;
255
256 regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
257 break;
258 case SND_SOC_BIAS_STANDBY:
259
260 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
261 jz4740_codec_wakeup(regmap);
262
263 mask = JZ4740_CODEC_1_VREF_DISABLE |
264 JZ4740_CODEC_1_VREF_AMP_DISABLE |
265 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
266 value = JZ4740_CODEC_1_VREF_DISABLE |
267 JZ4740_CODEC_1_VREF_AMP_DISABLE |
268 JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
269
270 regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
271 break;
272 case SND_SOC_BIAS_OFF:
273 mask = JZ4740_CODEC_1_SUSPEND;
274 value = JZ4740_CODEC_1_SUSPEND;
275
276 regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
277 regcache_mark_dirty(regmap);
278 break;
279 default:
280 break;
281 }
282
283 return 0;
284}
285
286static int jz4740_codec_dev_probe(struct snd_soc_component *component)
287{
288 struct jz4740_codec *jz4740_codec = snd_soc_component_get_drvdata(component);
289
290 regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
291 JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
292
293 return 0;
294}
295
296static const struct snd_soc_component_driver soc_codec_dev_jz4740_codec = {
297 .probe = jz4740_codec_dev_probe,
298 .set_bias_level = jz4740_codec_set_bias_level,
299 .controls = jz4740_codec_controls,
300 .num_controls = ARRAY_SIZE(jz4740_codec_controls),
301 .dapm_widgets = jz4740_codec_dapm_widgets,
302 .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
303 .dapm_routes = jz4740_codec_dapm_routes,
304 .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
305 .suspend_bias_off = 1,
306 .idle_bias_on = 1,
307 .use_pmdown_time = 1,
308 .endianness = 1,
309 .non_legacy_dai_naming = 1,
310
311};
312
313static const struct regmap_config jz4740_codec_regmap_config = {
314 .reg_bits = 32,
315 .reg_stride = 4,
316 .val_bits = 32,
317 .max_register = JZ4740_REG_CODEC_2,
318
319 .reg_defaults = jz4740_codec_reg_defaults,
320 .num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
321 .cache_type = REGCACHE_RBTREE,
322};
323
324static int jz4740_codec_probe(struct platform_device *pdev)
325{
326 int ret;
327 struct jz4740_codec *jz4740_codec;
328 struct resource *mem;
329 void __iomem *base;
330
331 jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
332 GFP_KERNEL);
333 if (!jz4740_codec)
334 return -ENOMEM;
335
336 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
337 base = devm_ioremap_resource(&pdev->dev, mem);
338 if (IS_ERR(base))
339 return PTR_ERR(base);
340
341 jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
342 &jz4740_codec_regmap_config);
343 if (IS_ERR(jz4740_codec->regmap))
344 return PTR_ERR(jz4740_codec->regmap);
345
346 platform_set_drvdata(pdev, jz4740_codec);
347
348 ret = devm_snd_soc_register_component(&pdev->dev,
349 &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
350 if (ret)
351 dev_err(&pdev->dev, "Failed to register codec\n");
352
353 return ret;
354}
355
356static struct platform_driver jz4740_codec_driver = {
357 .probe = jz4740_codec_probe,
358 .driver = {
359 .name = "jz4740-codec",
360 },
361};
362
363module_platform_driver(jz4740_codec_driver);
364
365MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
366MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
367MODULE_LICENSE("GPL v2");
368MODULE_ALIAS("platform:jz4740-codec");
369
