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13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
18
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include <sound/tlv.h>
22
23#include "pcm3168a.h"
24
25#define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
26 SNDRV_PCM_FMTBIT_S24_3LE | \
27 SNDRV_PCM_FMTBIT_S24_LE | \
28 SNDRV_PCM_FMTBIT_S32_LE)
29
30#define PCM3168A_FMT_I2S 0x0
31#define PCM3168A_FMT_LEFT_J 0x1
32#define PCM3168A_FMT_RIGHT_J 0x2
33#define PCM3168A_FMT_RIGHT_J_16 0x3
34#define PCM3168A_FMT_DSP_A 0x4
35#define PCM3168A_FMT_DSP_B 0x5
36#define PCM3168A_FMT_I2S_TDM 0x6
37#define PCM3168A_FMT_LEFT_J_TDM 0x7
38#define PCM3168A_FMT_DSP_MASK 0x4
39
40#define PCM3168A_NUM_SUPPLIES 6
41static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = {
42 "VDD1",
43 "VDD2",
44 "VCCAD1",
45 "VCCAD2",
46 "VCCDA1",
47 "VCCDA2"
48};
49
50struct pcm3168a_priv {
51 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES];
52 struct regmap *regmap;
53 struct clk *scki;
54 bool adc_master_mode;
55 bool dac_master_mode;
56 unsigned long sysclk;
57 unsigned int adc_fmt;
58 unsigned int dac_fmt;
59};
60
61static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
62
63static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
64 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
65static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
66 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
67static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
68 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
69static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
70 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
71
72static const char *const pcm3168a_volume_type[] = {
73 "Individual", "Master + Individual" };
74
75static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
76 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
77
78static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
79
80static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
81 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
82
83static const char *const pcm3168a_demp[] = {
84 "Disabled", "48khz", "44.1khz", "32khz" };
85
86static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
87 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
88
89static const char *const pcm3168a_zf_func[] = {
90 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
91 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
92
93static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
94 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
95
96static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
97
98static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
99 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
100
101static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
102
103static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
104 0, 1, pcm3168a_con);
105static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
106 2, 3, pcm3168a_con);
107static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
108 4, 5, pcm3168a_con);
109
110static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
111 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
112
113static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
114 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
115
116static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
117 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
118
119
120static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
121
122
123static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
124
125static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
126 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
127 PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
128 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
129 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
130 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
131 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
132 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
133 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
134 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
135 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
136 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
137 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
138 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
139 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
140 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
141 SOC_SINGLE_RANGE_TLV("Master Playback Volume",
142 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
143 pcm3168a_dac_tlv),
144 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
145 PCM3168A_DAC_VOL_CHAN_START,
146 PCM3168A_DAC_VOL_CHAN_START + 1,
147 0, 54, 255, 0, pcm3168a_dac_tlv),
148 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
149 PCM3168A_DAC_VOL_CHAN_START + 2,
150 PCM3168A_DAC_VOL_CHAN_START + 3,
151 0, 54, 255, 0, pcm3168a_dac_tlv),
152 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
153 PCM3168A_DAC_VOL_CHAN_START + 4,
154 PCM3168A_DAC_VOL_CHAN_START + 5,
155 0, 54, 255, 0, pcm3168a_dac_tlv),
156 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
157 PCM3168A_DAC_VOL_CHAN_START + 6,
158 PCM3168A_DAC_VOL_CHAN_START + 7,
159 0, 54, 255, 0, pcm3168a_dac_tlv),
160 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
161 PCM3168A_ADC_BYP_SHIFT, 1, 1),
162 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
163 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
164 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
165 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
166 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
167 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
168 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
169 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
170 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
171 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
172 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
173 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
174 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
175 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
176 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
177 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
178 SOC_SINGLE_RANGE_TLV("Master Capture Volume",
179 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
180 pcm3168a_adc_tlv),
181 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
182 PCM3168A_ADC_VOL_CHAN_START,
183 PCM3168A_ADC_VOL_CHAN_START + 1,
184 0, 14, 255, 0, pcm3168a_adc_tlv),
185 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
186 PCM3168A_ADC_VOL_CHAN_START + 2,
187 PCM3168A_ADC_VOL_CHAN_START + 3,
188 0, 14, 255, 0, pcm3168a_adc_tlv),
189 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
190 PCM3168A_ADC_VOL_CHAN_START + 4,
191 PCM3168A_ADC_VOL_CHAN_START + 5,
192 0, 14, 255, 0, pcm3168a_adc_tlv)
193};
194
195static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
196 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
197 PCM3168A_DAC_OPEDA_SHIFT, 1),
198 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
199 PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
200 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
201 PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
202 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
203 PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
204
205 SND_SOC_DAPM_OUTPUT("AOUT1L"),
206 SND_SOC_DAPM_OUTPUT("AOUT1R"),
207 SND_SOC_DAPM_OUTPUT("AOUT2L"),
208 SND_SOC_DAPM_OUTPUT("AOUT2R"),
209 SND_SOC_DAPM_OUTPUT("AOUT3L"),
210 SND_SOC_DAPM_OUTPUT("AOUT3R"),
211 SND_SOC_DAPM_OUTPUT("AOUT4L"),
212 SND_SOC_DAPM_OUTPUT("AOUT4R"),
213
214 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
215 PCM3168A_ADC_PSVAD_SHIFT, 1),
216 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
217 PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
218 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
219 PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
220
221 SND_SOC_DAPM_INPUT("AIN1L"),
222 SND_SOC_DAPM_INPUT("AIN1R"),
223 SND_SOC_DAPM_INPUT("AIN2L"),
224 SND_SOC_DAPM_INPUT("AIN2R"),
225 SND_SOC_DAPM_INPUT("AIN3L"),
226 SND_SOC_DAPM_INPUT("AIN3R")
227};
228
229static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
230
231 { "AOUT1L", NULL, "DAC1" },
232 { "AOUT1R", NULL, "DAC1" },
233
234 { "AOUT2L", NULL, "DAC2" },
235 { "AOUT2R", NULL, "DAC2" },
236
237 { "AOUT3L", NULL, "DAC3" },
238 { "AOUT3R", NULL, "DAC3" },
239
240 { "AOUT4L", NULL, "DAC4" },
241 { "AOUT4R", NULL, "DAC4" },
242
243
244 { "ADC1", NULL, "AIN1L" },
245 { "ADC1", NULL, "AIN1R" },
246
247 { "ADC2", NULL, "AIN2L" },
248 { "ADC2", NULL, "AIN2R" },
249
250 { "ADC3", NULL, "AIN3L" },
251 { "ADC3", NULL, "AIN3R" }
252};
253
254static unsigned int pcm3168a_scki_ratios[] = {
255 768,
256 512,
257 384,
258 256,
259 192,
260 128
261};
262
263#define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
264#define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
265
266#define PCM1368A_MAX_SYSCLK 36864000
267
268static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
269{
270 int ret;
271
272 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
273 if (ret)
274 return ret;
275
276
277 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
278
279 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
280 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
281}
282
283static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute)
284{
285 struct snd_soc_component *component = dai->component;
286 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
287
288 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
289
290 return 0;
291}
292
293static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
294 int clk_id, unsigned int freq, int dir)
295{
296 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
297 int ret;
298
299 if (freq > PCM1368A_MAX_SYSCLK)
300 return -EINVAL;
301
302 ret = clk_set_rate(pcm3168a->scki, freq);
303 if (ret)
304 return ret;
305
306 pcm3168a->sysclk = freq;
307
308 return 0;
309}
310
311static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai,
312 unsigned int format, bool dac)
313{
314 struct snd_soc_component *component = dai->component;
315 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
316 u32 fmt, reg, mask, shift;
317 bool master_mode;
318
319 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
320 case SND_SOC_DAIFMT_LEFT_J:
321 fmt = PCM3168A_FMT_LEFT_J;
322 break;
323 case SND_SOC_DAIFMT_I2S:
324 fmt = PCM3168A_FMT_I2S;
325 break;
326 case SND_SOC_DAIFMT_RIGHT_J:
327 fmt = PCM3168A_FMT_RIGHT_J;
328 break;
329 case SND_SOC_DAIFMT_DSP_A:
330 fmt = PCM3168A_FMT_DSP_A;
331 break;
332 case SND_SOC_DAIFMT_DSP_B:
333 fmt = PCM3168A_FMT_DSP_B;
334 break;
335 default:
336 dev_err(component->dev, "unsupported dai format\n");
337 return -EINVAL;
338 }
339
340 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
341 case SND_SOC_DAIFMT_CBS_CFS:
342 master_mode = false;
343 break;
344 case SND_SOC_DAIFMT_CBM_CFM:
345 master_mode = true;
346 break;
347 default:
348 dev_err(component->dev, "unsupported master/slave mode\n");
349 return -EINVAL;
350 }
351
352 switch (format & SND_SOC_DAIFMT_INV_MASK) {
353 case SND_SOC_DAIFMT_NB_NF:
354 break;
355 default:
356 return -EINVAL;
357 }
358
359 if (dac) {
360 reg = PCM3168A_DAC_PWR_MST_FMT;
361 mask = PCM3168A_DAC_FMT_MASK;
362 shift = PCM3168A_DAC_FMT_SHIFT;
363 pcm3168a->dac_master_mode = master_mode;
364 pcm3168a->dac_fmt = fmt;
365 } else {
366 reg = PCM3168A_ADC_MST_FMT;
367 mask = PCM3168A_ADC_FMTAD_MASK;
368 shift = PCM3168A_ADC_FMTAD_SHIFT;
369 pcm3168a->adc_master_mode = master_mode;
370 pcm3168a->adc_fmt = fmt;
371 }
372
373 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
374
375 return 0;
376}
377
378static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai,
379 unsigned int format)
380{
381 return pcm3168a_set_dai_fmt(dai, format, true);
382}
383
384static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai,
385 unsigned int format)
386{
387 return pcm3168a_set_dai_fmt(dai, format, false);
388}
389
390static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
391 struct snd_pcm_hw_params *params,
392 struct snd_soc_dai *dai)
393{
394 struct snd_soc_component *component = dai->component;
395 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
396 bool tx, master_mode;
397 u32 val, mask, shift, reg;
398 unsigned int rate, fmt, ratio, max_ratio;
399 unsigned int chan;
400 int i, min_frame_size;
401
402 rate = params_rate(params);
403 chan = params_channels(params);
404
405 ratio = pcm3168a->sysclk / rate;
406
407 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
408 if (tx) {
409 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC;
410 reg = PCM3168A_DAC_PWR_MST_FMT;
411 mask = PCM3168A_DAC_MSDA_MASK;
412 shift = PCM3168A_DAC_MSDA_SHIFT;
413 master_mode = pcm3168a->dac_master_mode;
414 fmt = pcm3168a->dac_fmt;
415 } else {
416 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC;
417 reg = PCM3168A_ADC_MST_FMT;
418 mask = PCM3168A_ADC_MSAD_MASK;
419 shift = PCM3168A_ADC_MSAD_SHIFT;
420 master_mode = pcm3168a->adc_master_mode;
421 fmt = pcm3168a->adc_fmt;
422 }
423
424 for (i = 0; i < max_ratio; i++) {
425 if (pcm3168a_scki_ratios[i] == ratio)
426 break;
427 }
428
429 if (i == max_ratio) {
430 dev_err(component->dev, "unsupported sysclk ratio\n");
431 return -EINVAL;
432 }
433
434 min_frame_size = params_width(params) * 2;
435 switch (min_frame_size) {
436 case 32:
437 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) {
438 dev_err(component->dev, "32-bit frames are supported only for slave mode using right justified\n");
439 return -EINVAL;
440 }
441 fmt = PCM3168A_FMT_RIGHT_J_16;
442 break;
443 case 48:
444 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) {
445 dev_err(component->dev, "48-bit frames not supported in master mode, or slave mode using DSP\n");
446 return -EINVAL;
447 }
448 break;
449 case 64:
450 break;
451 default:
452 dev_err(component->dev, "unsupported frame size: %d\n", min_frame_size);
453 return -EINVAL;
454 }
455
456
457 if (chan > 2) {
458 switch (fmt) {
459 case PCM3168A_FMT_I2S:
460 fmt = PCM3168A_FMT_I2S_TDM;
461 break;
462 case PCM3168A_FMT_LEFT_J:
463 fmt = PCM3168A_FMT_LEFT_J_TDM;
464 break;
465 default:
466 dev_err(component->dev, "TDM is supported under I2S/Left_J only\n");
467 return -EINVAL;
468 }
469 }
470
471 if (master_mode)
472 val = ((i + 1) << shift);
473 else
474 val = 0;
475
476 regmap_update_bits(pcm3168a->regmap, reg, mask, val);
477
478 if (tx) {
479 mask = PCM3168A_DAC_FMT_MASK;
480 shift = PCM3168A_DAC_FMT_SHIFT;
481 } else {
482 mask = PCM3168A_ADC_FMTAD_MASK;
483 shift = PCM3168A_ADC_FMTAD_SHIFT;
484 }
485
486 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
487
488 return 0;
489}
490
491static int pcm3168a_startup(struct snd_pcm_substream *substream,
492 struct snd_soc_dai *dai)
493{
494 struct snd_soc_component *component = dai->component;
495 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
496 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
497 unsigned int fmt;
498 unsigned int sample_min;
499 unsigned int channel_max;
500 unsigned int channel_maxs[] = {
501 6,
502 8
503 };
504
505 if (tx)
506 fmt = pcm3168a->dac_fmt;
507 else
508 fmt = pcm3168a->adc_fmt;
509
510
511
512
513
514
515
516
517
518
519
520
521
522 switch (fmt) {
523 case PCM3168A_FMT_RIGHT_J:
524 sample_min = 16;
525 channel_max = 2;
526 break;
527 case PCM3168A_FMT_LEFT_J:
528 case PCM3168A_FMT_I2S:
529 sample_min = 24;
530 channel_max = channel_maxs[tx];
531 break;
532 default:
533 sample_min = 24;
534 channel_max = 2;
535 }
536
537 snd_pcm_hw_constraint_minmax(substream->runtime,
538 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
539 sample_min, 32);
540
541 snd_pcm_hw_constraint_minmax(substream->runtime,
542 SNDRV_PCM_HW_PARAM_CHANNELS,
543 2, channel_max);
544
545 return 0;
546}
547static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = {
548 .startup = pcm3168a_startup,
549 .set_fmt = pcm3168a_set_dai_fmt_dac,
550 .set_sysclk = pcm3168a_set_dai_sysclk,
551 .hw_params = pcm3168a_hw_params,
552 .digital_mute = pcm3168a_digital_mute
553};
554
555static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = {
556 .startup = pcm3168a_startup,
557 .set_fmt = pcm3168a_set_dai_fmt_adc,
558 .set_sysclk = pcm3168a_set_dai_sysclk,
559 .hw_params = pcm3168a_hw_params
560};
561
562static struct snd_soc_dai_driver pcm3168a_dais[] = {
563 {
564 .name = "pcm3168a-dac",
565 .playback = {
566 .stream_name = "Playback",
567 .channels_min = 1,
568 .channels_max = 8,
569 .rates = SNDRV_PCM_RATE_8000_192000,
570 .formats = PCM3168A_FORMATS
571 },
572 .ops = &pcm3168a_dac_dai_ops
573 },
574 {
575 .name = "pcm3168a-adc",
576 .capture = {
577 .stream_name = "Capture",
578 .channels_min = 1,
579 .channels_max = 6,
580 .rates = SNDRV_PCM_RATE_8000_96000,
581 .formats = PCM3168A_FORMATS
582 },
583 .ops = &pcm3168a_adc_dai_ops
584 },
585};
586
587static const struct reg_default pcm3168a_reg_default[] = {
588 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
589 { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
590 { PCM3168A_DAC_OP_FLT, 0x00 },
591 { PCM3168A_DAC_INV, 0x00 },
592 { PCM3168A_DAC_MUTE, 0x00 },
593 { PCM3168A_DAC_ZERO, 0x00 },
594 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
595 { PCM3168A_DAC_VOL_MASTER, 0xff },
596 { PCM3168A_DAC_VOL_CHAN_START, 0xff },
597 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
598 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
599 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
600 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
601 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
602 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
603 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
604 { PCM3168A_ADC_SMODE, 0x00 },
605 { PCM3168A_ADC_MST_FMT, 0x00 },
606 { PCM3168A_ADC_PWR_HPFB, 0x00 },
607 { PCM3168A_ADC_SEAD, 0x00 },
608 { PCM3168A_ADC_INV, 0x00 },
609 { PCM3168A_ADC_MUTE, 0x00 },
610 { PCM3168A_ADC_OV, 0x00 },
611 { PCM3168A_ADC_ATT_OVF, 0x00 },
612 { PCM3168A_ADC_VOL_MASTER, 0xd3 },
613 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
614 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
615 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
616 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
617 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
618 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
619};
620
621static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
622{
623 if (reg >= PCM3168A_RST_SMODE)
624 return true;
625 else
626 return false;
627}
628
629static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
630{
631 switch (reg) {
632 case PCM3168A_DAC_ZERO:
633 case PCM3168A_ADC_OV:
634 return true;
635 default:
636 return false;
637 }
638}
639
640static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
641{
642 if (reg < PCM3168A_RST_SMODE)
643 return false;
644
645 switch (reg) {
646 case PCM3168A_DAC_ZERO:
647 case PCM3168A_ADC_OV:
648 return false;
649 default:
650 return true;
651 }
652}
653
654const struct regmap_config pcm3168a_regmap = {
655 .reg_bits = 8,
656 .val_bits = 8,
657
658 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
659 .reg_defaults = pcm3168a_reg_default,
660 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
661 .readable_reg = pcm3168a_readable_register,
662 .volatile_reg = pcm3168a_volatile_register,
663 .writeable_reg = pcm3168a_writeable_register,
664 .cache_type = REGCACHE_FLAT
665};
666EXPORT_SYMBOL_GPL(pcm3168a_regmap);
667
668static const struct snd_soc_component_driver pcm3168a_driver = {
669 .controls = pcm3168a_snd_controls,
670 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
671 .dapm_widgets = pcm3168a_dapm_widgets,
672 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
673 .dapm_routes = pcm3168a_dapm_routes,
674 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes),
675 .use_pmdown_time = 1,
676 .endianness = 1,
677 .non_legacy_dai_naming = 1,
678};
679
680int pcm3168a_probe(struct device *dev, struct regmap *regmap)
681{
682 struct pcm3168a_priv *pcm3168a;
683 int ret, i;
684
685 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
686 if (pcm3168a == NULL)
687 return -ENOMEM;
688
689 dev_set_drvdata(dev, pcm3168a);
690
691 pcm3168a->scki = devm_clk_get(dev, "scki");
692 if (IS_ERR(pcm3168a->scki)) {
693 ret = PTR_ERR(pcm3168a->scki);
694 if (ret != -EPROBE_DEFER)
695 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret);
696 return ret;
697 }
698
699 ret = clk_prepare_enable(pcm3168a->scki);
700 if (ret) {
701 dev_err(dev, "Failed to enable mclk: %d\n", ret);
702 return ret;
703 }
704
705 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
706
707 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
708 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
709
710 ret = devm_regulator_bulk_get(dev,
711 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
712 if (ret) {
713 if (ret != -EPROBE_DEFER)
714 dev_err(dev, "failed to request supplies: %d\n", ret);
715 goto err_clk;
716 }
717
718 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
719 pcm3168a->supplies);
720 if (ret) {
721 dev_err(dev, "failed to enable supplies: %d\n", ret);
722 goto err_clk;
723 }
724
725 pcm3168a->regmap = regmap;
726 if (IS_ERR(pcm3168a->regmap)) {
727 ret = PTR_ERR(pcm3168a->regmap);
728 dev_err(dev, "failed to allocate regmap: %d\n", ret);
729 goto err_regulator;
730 }
731
732 ret = pcm3168a_reset(pcm3168a);
733 if (ret) {
734 dev_err(dev, "Failed to reset device: %d\n", ret);
735 goto err_regulator;
736 }
737
738 pm_runtime_set_active(dev);
739 pm_runtime_enable(dev);
740 pm_runtime_idle(dev);
741
742 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais,
743 ARRAY_SIZE(pcm3168a_dais));
744 if (ret) {
745 dev_err(dev, "failed to register component: %d\n", ret);
746 goto err_regulator;
747 }
748
749 return 0;
750
751err_regulator:
752 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
753 pcm3168a->supplies);
754err_clk:
755 clk_disable_unprepare(pcm3168a->scki);
756
757 return ret;
758}
759EXPORT_SYMBOL_GPL(pcm3168a_probe);
760
761static void pcm3168a_disable(struct device *dev)
762{
763 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
764
765 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
766 pcm3168a->supplies);
767 clk_disable_unprepare(pcm3168a->scki);
768}
769
770void pcm3168a_remove(struct device *dev)
771{
772 pm_runtime_disable(dev);
773#ifndef CONFIG_PM
774 pcm3168a_disable(dev);
775#endif
776}
777EXPORT_SYMBOL_GPL(pcm3168a_remove);
778
779#ifdef CONFIG_PM
780static int pcm3168a_rt_resume(struct device *dev)
781{
782 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
783 int ret;
784
785 ret = clk_prepare_enable(pcm3168a->scki);
786 if (ret) {
787 dev_err(dev, "Failed to enable mclk: %d\n", ret);
788 return ret;
789 }
790
791 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
792 pcm3168a->supplies);
793 if (ret) {
794 dev_err(dev, "Failed to enable supplies: %d\n", ret);
795 goto err_clk;
796 }
797
798 ret = pcm3168a_reset(pcm3168a);
799 if (ret) {
800 dev_err(dev, "Failed to reset device: %d\n", ret);
801 goto err_regulator;
802 }
803
804 regcache_cache_only(pcm3168a->regmap, false);
805
806 regcache_mark_dirty(pcm3168a->regmap);
807
808 ret = regcache_sync(pcm3168a->regmap);
809 if (ret) {
810 dev_err(dev, "Failed to sync regmap: %d\n", ret);
811 goto err_regulator;
812 }
813
814 return 0;
815
816err_regulator:
817 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
818 pcm3168a->supplies);
819err_clk:
820 clk_disable_unprepare(pcm3168a->scki);
821
822 return ret;
823}
824
825static int pcm3168a_rt_suspend(struct device *dev)
826{
827 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
828
829 regcache_cache_only(pcm3168a->regmap, true);
830
831 pcm3168a_disable(dev);
832
833 return 0;
834}
835#endif
836
837const struct dev_pm_ops pcm3168a_pm_ops = {
838 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
839};
840EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
841
842MODULE_DESCRIPTION("PCM3168A codec driver");
843MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
844MODULE_LICENSE("GPL v2");
845
