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18#include <linux/module.h>
19#include <linux/delay.h>
20#include <linux/firmware.h>
21#include <linux/device.h>
22
23#include "../common/sst-dsp.h"
24#include "../common/sst-dsp-priv.h"
25#include "skl-sst-ipc.h"
26
27#define BXT_BASEFW_TIMEOUT 3000
28#define BXT_INIT_TIMEOUT 300
29#define BXT_ROM_INIT_TIMEOUT 70
30#define BXT_IPC_PURGE_FW 0x01004000
31
32#define BXT_ROM_INIT 0x5
33#define BXT_ADSP_SRAM0_BASE 0x80000
34
35
36#define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
37#define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
38
39#define BXT_ADSP_SRAM1_BASE 0xA0000
40
41#define BXT_INSTANCE_ID 0
42#define BXT_BASE_FW_MODULE_ID 0
43
44#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
45
46
47#define BXT_D0I3_DELAY 5000
48
49#define BXT_FW_ROM_INIT_RETRY 3
50
51static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
52{
53 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
54}
55
56static int
57bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
58{
59 struct snd_dma_buffer dmab;
60 struct skl_sst *skl = ctx->thread_context;
61 struct firmware stripped_fw;
62 int ret = 0, i, dma_id, stream_tag;
63
64
65 for (i = 1; i < lib_count; i++) {
66 ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
67 BXT_ADSP_FW_BIN_HDR_OFFSET, i);
68 if (ret < 0)
69 goto load_library_failed;
70
71 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
72 stripped_fw.size, &dmab);
73 if (stream_tag <= 0) {
74 dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
75 stream_tag);
76 ret = stream_tag;
77 goto load_library_failed;
78 }
79
80 dma_id = stream_tag - 1;
81 memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
82
83 ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
84 ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
85 if (ret < 0)
86 dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
87 linfo[i].name, ret);
88
89 ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
90 ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
91 }
92
93 return ret;
94
95load_library_failed:
96 skl_release_library(linfo, lib_count);
97 return ret;
98}
99
100
101
102
103
104
105static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
106 const void *fwdata, u32 fwsize)
107{
108 int stream_tag, ret;
109
110 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
111 if (stream_tag <= 0) {
112 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
113 stream_tag);
114 return stream_tag;
115 }
116
117 ctx->dsp_ops.stream_tag = stream_tag;
118 memcpy(ctx->dmab.area, fwdata, fwsize);
119
120
121 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
122 SKL_DSP_CORE_MASK(1));
123 if (ret < 0) {
124 dev_err(ctx->dev, "dsp core0/1 power up failed\n");
125 goto base_fw_load_failed;
126 }
127
128
129 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
130 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
131
132
133 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
134 if (ret < 0) {
135 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
136 ret = -EIO;
137 goto base_fw_load_failed;
138 }
139
140
141 ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
142 SKL_ADSP_REG_HIPCIE_DONE,
143 SKL_ADSP_REG_HIPCIE_DONE,
144 BXT_INIT_TIMEOUT, "HIPCIE Done");
145 if (ret < 0) {
146 dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
147 goto base_fw_load_failed;
148 }
149
150
151 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
152 if (ret < 0) {
153 dev_err(ctx->dev, "dsp core1 power down failed\n");
154 goto base_fw_load_failed;
155 }
156
157
158 skl_ipc_int_enable(ctx);
159 skl_ipc_op_int_enable(ctx);
160
161
162 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
163 SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
164 if (ret < 0) {
165 dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
166 goto base_fw_load_failed;
167 }
168
169 return ret;
170
171base_fw_load_failed:
172 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
173 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
174 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
175 return ret;
176}
177
178static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
179{
180 int ret;
181
182 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
183 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
184 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
185
186 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
187 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
188
189 return ret;
190}
191
192static int bxt_load_base_firmware(struct sst_dsp *ctx)
193{
194 struct firmware stripped_fw;
195 struct skl_sst *skl = ctx->thread_context;
196 int ret, i;
197
198 if (ctx->fw == NULL) {
199 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
200 if (ret < 0) {
201 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
202 return ret;
203 }
204 }
205
206
207 if (skl->is_first_boot) {
208 ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
209 if (ret < 0)
210 goto sst_load_base_firmware_failed;
211 }
212
213 stripped_fw.data = ctx->fw->data;
214 stripped_fw.size = ctx->fw->size;
215 skl_dsp_strip_extended_manifest(&stripped_fw);
216
217
218 for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
219 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
220 if (ret == 0)
221 break;
222 }
223
224 if (ret < 0) {
225 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
226 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
227 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
228
229 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
230 goto sst_load_base_firmware_failed;
231 }
232
233 ret = sst_transfer_fw_host_dma(ctx);
234 if (ret < 0) {
235 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
236 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
237 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
238 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
239
240 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
241 } else {
242 dev_dbg(ctx->dev, "Firmware download successful\n");
243 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
244 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
245 if (ret == 0) {
246 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
247 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
248 ret = -EIO;
249 } else {
250 ret = 0;
251 skl->fw_loaded = true;
252 }
253 }
254
255 return ret;
256
257sst_load_base_firmware_failed:
258 release_firmware(ctx->fw);
259 ctx->fw = NULL;
260 return ret;
261}
262
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273
274
275
276
277static int bxt_d0i3_target_state(struct sst_dsp *ctx)
278{
279 struct skl_sst *skl = ctx->thread_context;
280 struct skl_d0i3_data *d0i3 = &skl->d0i3;
281
282 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
283 return SKL_DSP_D0I3_NONE;
284
285 if (d0i3->non_d0i3)
286 return SKL_DSP_D0I3_NONE;
287 else if (d0i3->streaming)
288 return SKL_DSP_D0I3_STREAMING;
289 else if (d0i3->non_streaming)
290 return SKL_DSP_D0I3_NON_STREAMING;
291 else
292 return SKL_DSP_D0I3_NONE;
293}
294
295static void bxt_set_dsp_D0i3(struct work_struct *work)
296{
297 int ret;
298 struct skl_ipc_d0ix_msg msg;
299 struct skl_sst *skl = container_of(work,
300 struct skl_sst, d0i3.work.work);
301 struct sst_dsp *ctx = skl->dsp;
302 struct skl_d0i3_data *d0i3 = &skl->d0i3;
303 int target_state;
304
305 dev_dbg(ctx->dev, "In %s:\n", __func__);
306
307
308 if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
309 dev_warn(ctx->dev,
310 "D0i3 allowed when only core0 running:Exit\n");
311 return;
312 }
313
314 target_state = bxt_d0i3_target_state(ctx);
315 if (target_state == SKL_DSP_D0I3_NONE)
316 return;
317
318 msg.instance_id = 0;
319 msg.module_id = 0;
320 msg.wake = 1;
321 msg.streaming = 0;
322 if (target_state == SKL_DSP_D0I3_STREAMING)
323 msg.streaming = 1;
324
325 ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
326
327 if (ret < 0) {
328 dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
329 return;
330 }
331
332
333 if (skl->update_d0i3c)
334 skl->update_d0i3c(skl->dev, true);
335
336 d0i3->state = target_state;
337 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
338}
339
340static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
341{
342 struct skl_sst *skl = ctx->thread_context;
343 struct skl_d0i3_data *d0i3 = &skl->d0i3;
344
345
346 if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
347
348 dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
349
350 schedule_delayed_work(&d0i3->work,
351 msecs_to_jiffies(BXT_D0I3_DELAY));
352 }
353
354 return 0;
355}
356
357static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
358{
359 int ret;
360 struct skl_ipc_d0ix_msg msg;
361 struct skl_sst *skl = ctx->thread_context;
362
363 dev_dbg(ctx->dev, "In %s:\n", __func__);
364
365
366 cancel_delayed_work_sync(&skl->d0i3.work);
367
368
369 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
370 return 0;
371
372 dev_dbg(ctx->dev, "Set DSP to D0i0\n");
373
374 msg.instance_id = 0;
375 msg.module_id = 0;
376 msg.streaming = 0;
377 msg.wake = 0;
378
379 if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
380 msg.streaming = 1;
381
382
383 if (skl->update_d0i3c)
384 skl->update_d0i3c(skl->dev, false);
385
386 ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
387 if (ret < 0) {
388 dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
389 return ret;
390 }
391
392 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
393 skl->d0i3.state = SKL_DSP_D0I3_NONE;
394
395 return 0;
396}
397
398static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
399{
400 struct skl_sst *skl = ctx->thread_context;
401 int ret;
402 struct skl_ipc_dxstate_info dx;
403 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
404
405 if (skl->fw_loaded == false) {
406 skl->boot_complete = false;
407 ret = bxt_load_base_firmware(ctx);
408 if (ret < 0) {
409 dev_err(ctx->dev, "reload fw failed: %d\n", ret);
410 return ret;
411 }
412
413 if (skl->lib_count > 1) {
414 ret = bxt_load_library(ctx, skl->lib_info,
415 skl->lib_count);
416 if (ret < 0) {
417 dev_err(ctx->dev, "reload libs failed: %d\n", ret);
418 return ret;
419 }
420 }
421 skl->cores.state[core_id] = SKL_DSP_RUNNING;
422 return ret;
423 }
424
425
426 if (core_id == SKL_DSP_CORE0_ID)
427 ret = skl_dsp_core_power_up(ctx, core_mask |
428 SKL_DSP_CORE_MASK(1));
429 else
430 ret = skl_dsp_core_power_up(ctx, core_mask);
431
432 if (ret < 0)
433 goto err;
434
435 if (core_id == SKL_DSP_CORE0_ID) {
436
437
438
439
440
441 skl_ipc_int_enable(ctx);
442 skl_ipc_op_int_enable(ctx);
443 skl->boot_complete = false;
444 }
445
446 ret = skl_dsp_start_core(ctx, core_mask);
447 if (ret < 0)
448 goto err;
449
450 if (core_id == SKL_DSP_CORE0_ID) {
451 ret = wait_event_timeout(skl->boot_wait,
452 skl->boot_complete,
453 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
454
455
456 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
457 if (ret == 0) {
458 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
459 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
460 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
461 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
462 dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
463 ret = -EIO;
464 goto err;
465 }
466 }
467
468
469
470 if (core_id != SKL_DSP_CORE0_ID) {
471 dx.core_mask = core_mask;
472 dx.dx_mask = core_mask;
473
474 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
475 BXT_BASE_FW_MODULE_ID, &dx);
476 if (ret < 0) {
477 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
478 core_id, ret);
479 goto err;
480 }
481 }
482
483 skl->cores.state[core_id] = SKL_DSP_RUNNING;
484 return 0;
485err:
486 if (core_id == SKL_DSP_CORE0_ID)
487 core_mask |= SKL_DSP_CORE_MASK(1);
488 skl_dsp_disable_core(ctx, core_mask);
489
490 return ret;
491}
492
493static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
494{
495 int ret;
496 struct skl_ipc_dxstate_info dx;
497 struct skl_sst *skl = ctx->thread_context;
498 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
499
500 dx.core_mask = core_mask;
501 dx.dx_mask = SKL_IPC_D3_MASK;
502
503 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
504 dx.core_mask, dx.dx_mask);
505
506 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
507 BXT_BASE_FW_MODULE_ID, &dx);
508 if (ret < 0) {
509 dev_err(ctx->dev,
510 "Failed to set DSP to D3:core id = %d;Continue reset\n",
511 core_id);
512
513
514
515
516 skl->fw_loaded = false;
517 }
518
519 if (core_id == SKL_DSP_CORE0_ID) {
520
521 skl_ipc_op_int_disable(ctx);
522 skl_ipc_int_disable(ctx);
523 }
524 ret = skl_dsp_disable_core(ctx, core_mask);
525 if (ret < 0) {
526 dev_err(ctx->dev, "Failed to disable core %d\n", ret);
527 return ret;
528 }
529 skl->cores.state[core_id] = SKL_DSP_RESET;
530 return 0;
531}
532
533static const struct skl_dsp_fw_ops bxt_fw_ops = {
534 .set_state_D0 = bxt_set_dsp_D0,
535 .set_state_D3 = bxt_set_dsp_D3,
536 .set_state_D0i3 = bxt_schedule_dsp_D0i3,
537 .set_state_D0i0 = bxt_set_dsp_D0i0,
538 .load_fw = bxt_load_base_firmware,
539 .get_fw_errcode = bxt_get_errorcode,
540 .load_library = bxt_load_library,
541};
542
543static struct sst_ops skl_ops = {
544 .irq_handler = skl_dsp_sst_interrupt,
545 .write = sst_shim32_write,
546 .read = sst_shim32_read,
547 .ram_read = sst_memcpy_fromio_32,
548 .ram_write = sst_memcpy_toio_32,
549 .free = skl_dsp_free,
550};
551
552static struct sst_dsp_device skl_dev = {
553 .thread = skl_dsp_irq_thread_handler,
554 .ops = &skl_ops,
555};
556
557int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
558 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
559 struct skl_sst **dsp)
560{
561 struct skl_sst *skl;
562 struct sst_dsp *sst;
563 int ret;
564
565 ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
566 if (ret < 0) {
567 dev_err(dev, "%s: no device\n", __func__);
568 return ret;
569 }
570
571 skl = *dsp;
572 sst = skl->dsp;
573 sst->fw_ops = bxt_fw_ops;
574 sst->addr.lpe = mmio_base;
575 sst->addr.shim = mmio_base;
576 sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
577 sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
578 sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
579 sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
580
581 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
582 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
583
584 ret = skl_ipc_init(dev, skl);
585 if (ret) {
586 skl_dsp_free(sst);
587 return ret;
588 }
589
590
591 skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
592
593 skl->boot_complete = false;
594 init_waitqueue_head(&skl->boot_wait);
595 INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
596 skl->d0i3.state = SKL_DSP_D0I3_NONE;
597
598 return skl_dsp_acquire_irq(sst);
599}
600EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
601
602int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx)
603{
604 int ret;
605 struct sst_dsp *sst = ctx->dsp;
606
607 ret = sst->fw_ops.load_fw(sst);
608 if (ret < 0) {
609 dev_err(dev, "Load base fw failed: %x\n", ret);
610 return ret;
611 }
612
613 skl_dsp_init_core_state(sst);
614
615 if (ctx->lib_count > 1) {
616 ret = sst->fw_ops.load_library(sst, ctx->lib_info,
617 ctx->lib_count);
618 if (ret < 0) {
619 dev_err(dev, "Load Library failed : %x\n", ret);
620 return ret;
621 }
622 }
623 ctx->is_first_boot = false;
624
625 return 0;
626}
627EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
628
629void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
630{
631
632 skl_release_library(ctx->lib_info, ctx->lib_count);
633 if (ctx->dsp->fw)
634 release_firmware(ctx->dsp->fw);
635 skl_freeup_uuid_list(ctx);
636 skl_ipc_free(&ctx->ipc);
637 ctx->dsp->ops->free(ctx->dsp);
638}
639EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
640
641MODULE_LICENSE("GPL v2");
642MODULE_DESCRIPTION("Intel Broxton IPC driver");
643
