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15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/of_gpio.h>
18#include <linux/clk.h>
19#include <linux/pm_runtime.h>
20#include <linux/mfd/syscon.h>
21#include <linux/regmap.h>
22#include <sound/pcm_params.h>
23#include <sound/dmaengine_pcm.h>
24
25#include "rockchip_spdif.h"
26
27enum rk_spdif_type {
28 RK_SPDIF_RK3066,
29 RK_SPDIF_RK3188,
30 RK_SPDIF_RK3288,
31 RK_SPDIF_RK3366,
32};
33
34#define RK3288_GRF_SOC_CON2 0x24c
35
36struct rk_spdif_dev {
37 struct device *dev;
38
39 struct clk *mclk;
40 struct clk *hclk;
41
42 struct snd_dmaengine_dai_dma_data playback_dma_data;
43
44 struct regmap *regmap;
45};
46
47static const struct of_device_id rk_spdif_match[] = {
48 { .compatible = "rockchip,rk3066-spdif",
49 .data = (void *)RK_SPDIF_RK3066 },
50 { .compatible = "rockchip,rk3188-spdif",
51 .data = (void *)RK_SPDIF_RK3188 },
52 { .compatible = "rockchip,rk3228-spdif",
53 .data = (void *)RK_SPDIF_RK3366 },
54 { .compatible = "rockchip,rk3288-spdif",
55 .data = (void *)RK_SPDIF_RK3288 },
56 { .compatible = "rockchip,rk3328-spdif",
57 .data = (void *)RK_SPDIF_RK3366 },
58 { .compatible = "rockchip,rk3366-spdif",
59 .data = (void *)RK_SPDIF_RK3366 },
60 { .compatible = "rockchip,rk3368-spdif",
61 .data = (void *)RK_SPDIF_RK3366 },
62 { .compatible = "rockchip,rk3399-spdif",
63 .data = (void *)RK_SPDIF_RK3366 },
64 {},
65};
66MODULE_DEVICE_TABLE(of, rk_spdif_match);
67
68static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
69{
70 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
71
72 regcache_cache_only(spdif->regmap, true);
73 clk_disable_unprepare(spdif->mclk);
74 clk_disable_unprepare(spdif->hclk);
75
76 return 0;
77}
78
79static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
80{
81 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
82 int ret;
83
84 ret = clk_prepare_enable(spdif->mclk);
85 if (ret) {
86 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
87 return ret;
88 }
89
90 ret = clk_prepare_enable(spdif->hclk);
91 if (ret) {
92 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
93 return ret;
94 }
95
96 regcache_cache_only(spdif->regmap, false);
97 regcache_mark_dirty(spdif->regmap);
98
99 ret = regcache_sync(spdif->regmap);
100 if (ret) {
101 clk_disable_unprepare(spdif->mclk);
102 clk_disable_unprepare(spdif->hclk);
103 }
104
105 return ret;
106}
107
108static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
109 struct snd_pcm_hw_params *params,
110 struct snd_soc_dai *dai)
111{
112 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
113 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
114 int srate, mclk;
115 int ret;
116
117 srate = params_rate(params);
118 mclk = srate * 128;
119
120 switch (params_format(params)) {
121 case SNDRV_PCM_FORMAT_S16_LE:
122 val |= SPDIF_CFGR_VDW_16;
123 break;
124 case SNDRV_PCM_FORMAT_S20_3LE:
125 val |= SPDIF_CFGR_VDW_20;
126 break;
127 case SNDRV_PCM_FORMAT_S24_LE:
128 val |= SPDIF_CFGR_VDW_24;
129 break;
130 default:
131 return -EINVAL;
132 }
133
134
135 ret = clk_set_rate(spdif->mclk, mclk);
136 if (ret != 0) {
137 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
138 ret);
139 return ret;
140 }
141
142 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
143 SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
144 SDPIF_CFGR_VDW_MASK,
145 val);
146
147 return ret;
148}
149
150static int rk_spdif_trigger(struct snd_pcm_substream *substream,
151 int cmd, struct snd_soc_dai *dai)
152{
153 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
154 int ret;
155
156 switch (cmd) {
157 case SNDRV_PCM_TRIGGER_START:
158 case SNDRV_PCM_TRIGGER_RESUME:
159 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
160 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
161 SPDIF_DMACR_TDE_ENABLE |
162 SPDIF_DMACR_TDL_MASK,
163 SPDIF_DMACR_TDE_ENABLE |
164 SPDIF_DMACR_TDL(16));
165
166 if (ret != 0)
167 return ret;
168
169 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
170 SPDIF_XFER_TXS_START,
171 SPDIF_XFER_TXS_START);
172 break;
173 case SNDRV_PCM_TRIGGER_SUSPEND:
174 case SNDRV_PCM_TRIGGER_STOP:
175 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
176 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
177 SPDIF_DMACR_TDE_ENABLE,
178 SPDIF_DMACR_TDE_DISABLE);
179
180 if (ret != 0)
181 return ret;
182
183 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
184 SPDIF_XFER_TXS_START,
185 SPDIF_XFER_TXS_STOP);
186 break;
187 default:
188 ret = -EINVAL;
189 break;
190 }
191
192 return ret;
193}
194
195static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
196{
197 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
198
199 dai->playback_dma_data = &spdif->playback_dma_data;
200
201 return 0;
202}
203
204static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
205 .hw_params = rk_spdif_hw_params,
206 .trigger = rk_spdif_trigger,
207};
208
209static struct snd_soc_dai_driver rk_spdif_dai = {
210 .probe = rk_spdif_dai_probe,
211 .playback = {
212 .stream_name = "Playback",
213 .channels_min = 2,
214 .channels_max = 2,
215 .rates = (SNDRV_PCM_RATE_32000 |
216 SNDRV_PCM_RATE_44100 |
217 SNDRV_PCM_RATE_48000 |
218 SNDRV_PCM_RATE_96000 |
219 SNDRV_PCM_RATE_192000),
220 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
221 SNDRV_PCM_FMTBIT_S20_3LE |
222 SNDRV_PCM_FMTBIT_S24_LE),
223 },
224 .ops = &rk_spdif_dai_ops,
225};
226
227static const struct snd_soc_component_driver rk_spdif_component = {
228 .name = "rockchip-spdif",
229};
230
231static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
232{
233 switch (reg) {
234 case SPDIF_CFGR:
235 case SPDIF_DMACR:
236 case SPDIF_INTCR:
237 case SPDIF_XFER:
238 case SPDIF_SMPDR:
239 return true;
240 default:
241 return false;
242 }
243}
244
245static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
246{
247 switch (reg) {
248 case SPDIF_CFGR:
249 case SPDIF_SDBLR:
250 case SPDIF_INTCR:
251 case SPDIF_INTSR:
252 case SPDIF_XFER:
253 return true;
254 default:
255 return false;
256 }
257}
258
259static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
260{
261 switch (reg) {
262 case SPDIF_INTSR:
263 case SPDIF_SDBLR:
264 return true;
265 default:
266 return false;
267 }
268}
269
270static const struct regmap_config rk_spdif_regmap_config = {
271 .reg_bits = 32,
272 .reg_stride = 4,
273 .val_bits = 32,
274 .max_register = SPDIF_SMPDR,
275 .writeable_reg = rk_spdif_wr_reg,
276 .readable_reg = rk_spdif_rd_reg,
277 .volatile_reg = rk_spdif_volatile_reg,
278 .cache_type = REGCACHE_FLAT,
279};
280
281static int rk_spdif_probe(struct platform_device *pdev)
282{
283 struct device_node *np = pdev->dev.of_node;
284 struct rk_spdif_dev *spdif;
285 const struct of_device_id *match;
286 struct resource *res;
287 void __iomem *regs;
288 int ret;
289
290 match = of_match_node(rk_spdif_match, np);
291 if (match->data == (void *)RK_SPDIF_RK3288) {
292 struct regmap *grf;
293
294 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
295 if (IS_ERR(grf)) {
296 dev_err(&pdev->dev,
297 "rockchip_spdif missing 'rockchip,grf' \n");
298 return PTR_ERR(grf);
299 }
300
301
302
303
304 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
305 }
306
307 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
308 if (!spdif)
309 return -ENOMEM;
310
311 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
312 if (IS_ERR(spdif->hclk)) {
313 dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
314 return PTR_ERR(spdif->hclk);
315 }
316 ret = clk_prepare_enable(spdif->hclk);
317 if (ret) {
318 dev_err(spdif->dev, "hclock enable failed %d\n", ret);
319 return ret;
320 }
321
322 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
323 if (IS_ERR(spdif->mclk)) {
324 dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
325 ret = PTR_ERR(spdif->mclk);
326 goto err_disable_hclk;
327 }
328
329 ret = clk_prepare_enable(spdif->mclk);
330 if (ret) {
331 dev_err(spdif->dev, "clock enable failed %d\n", ret);
332 goto err_disable_clocks;
333 }
334
335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 regs = devm_ioremap_resource(&pdev->dev, res);
337 if (IS_ERR(regs)) {
338 ret = PTR_ERR(regs);
339 goto err_disable_clocks;
340 }
341
342 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
343 &rk_spdif_regmap_config);
344 if (IS_ERR(spdif->regmap)) {
345 dev_err(&pdev->dev,
346 "Failed to initialise managed register map\n");
347 ret = PTR_ERR(spdif->regmap);
348 goto err_disable_clocks;
349 }
350
351 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
352 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
353 spdif->playback_dma_data.maxburst = 4;
354
355 spdif->dev = &pdev->dev;
356 dev_set_drvdata(&pdev->dev, spdif);
357
358 pm_runtime_set_active(&pdev->dev);
359 pm_runtime_enable(&pdev->dev);
360 pm_request_idle(&pdev->dev);
361
362 ret = devm_snd_soc_register_component(&pdev->dev,
363 &rk_spdif_component,
364 &rk_spdif_dai, 1);
365 if (ret) {
366 dev_err(&pdev->dev, "Could not register DAI\n");
367 goto err_pm_runtime;
368 }
369
370 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
371 if (ret) {
372 dev_err(&pdev->dev, "Could not register PCM\n");
373 goto err_pm_runtime;
374 }
375
376 return 0;
377
378err_pm_runtime:
379 pm_runtime_disable(&pdev->dev);
380err_disable_clocks:
381 clk_disable_unprepare(spdif->mclk);
382err_disable_hclk:
383 clk_disable_unprepare(spdif->hclk);
384
385 return ret;
386}
387
388static int rk_spdif_remove(struct platform_device *pdev)
389{
390 struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
391
392 pm_runtime_disable(&pdev->dev);
393 if (!pm_runtime_status_suspended(&pdev->dev))
394 rk_spdif_runtime_suspend(&pdev->dev);
395
396 clk_disable_unprepare(spdif->mclk);
397 clk_disable_unprepare(spdif->hclk);
398
399 return 0;
400}
401
402static const struct dev_pm_ops rk_spdif_pm_ops = {
403 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
404 NULL)
405};
406
407static struct platform_driver rk_spdif_driver = {
408 .probe = rk_spdif_probe,
409 .remove = rk_spdif_remove,
410 .driver = {
411 .name = "rockchip-spdif",
412 .of_match_table = of_match_ptr(rk_spdif_match),
413 .pm = &rk_spdif_pm_ops,
414 },
415};
416module_platform_driver(rk_spdif_driver);
417
418MODULE_ALIAS("platform:rockchip-spdif");
419MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
420MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
421MODULE_LICENSE("GPL v2");
422
