1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65
66
67
68
69enum i915_mocs_table_index {
70
71
72
73
74 I915_MOCS_UNCACHED,
75
76
77
78
79
80 I915_MOCS_PTE,
81
82
83
84
85
86 I915_MOCS_CACHED,
87};
88
89
90
91
92
93
94
95
96enum drm_i915_gem_engine_class {
97 I915_ENGINE_CLASS_RENDER = 0,
98 I915_ENGINE_CLASS_COPY = 1,
99 I915_ENGINE_CLASS_VIDEO = 2,
100 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
101
102 I915_ENGINE_CLASS_INVALID = -1
103};
104
105
106
107
108
109
110enum drm_i915_pmu_engine_sample {
111 I915_SAMPLE_BUSY = 0,
112 I915_SAMPLE_WAIT = 1,
113 I915_SAMPLE_SEMA = 2
114};
115
116#define I915_PMU_SAMPLE_BITS (4)
117#define I915_PMU_SAMPLE_MASK (0xf)
118#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
119#define I915_PMU_CLASS_SHIFT \
120 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
121
122#define __I915_PMU_ENGINE(class, instance, sample) \
123 ((class) << I915_PMU_CLASS_SHIFT | \
124 (instance) << I915_PMU_SAMPLE_BITS | \
125 (sample))
126
127#define I915_PMU_ENGINE_BUSY(class, instance) \
128 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
129
130#define I915_PMU_ENGINE_WAIT(class, instance) \
131 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
132
133#define I915_PMU_ENGINE_SEMA(class, instance) \
134 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
135
136#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
137
138#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
139#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
140#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
141#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
142
143#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
144
145
146
147#define I915_NR_TEX_REGIONS 255
148
149#define I915_LOG_MIN_TEX_REGION_SIZE 14
150
151typedef struct _drm_i915_init {
152 enum {
153 I915_INIT_DMA = 0x01,
154 I915_CLEANUP_DMA = 0x02,
155 I915_RESUME_DMA = 0x03
156 } func;
157 unsigned int mmio_offset;
158 int sarea_priv_offset;
159 unsigned int ring_start;
160 unsigned int ring_end;
161 unsigned int ring_size;
162 unsigned int front_offset;
163 unsigned int back_offset;
164 unsigned int depth_offset;
165 unsigned int w;
166 unsigned int h;
167 unsigned int pitch;
168 unsigned int pitch_bits;
169 unsigned int back_pitch;
170 unsigned int depth_pitch;
171 unsigned int cpp;
172 unsigned int chipset;
173} drm_i915_init_t;
174
175typedef struct _drm_i915_sarea {
176 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
177 int last_upload;
178 int last_enqueue;
179 int last_dispatch;
180 int ctxOwner;
181 int texAge;
182 int pf_enabled;
183 int pf_active;
184 int pf_current_page;
185 int perf_boxes;
186 int width, height;
187
188 drm_handle_t front_handle;
189 int front_offset;
190 int front_size;
191
192 drm_handle_t back_handle;
193 int back_offset;
194 int back_size;
195
196 drm_handle_t depth_handle;
197 int depth_offset;
198 int depth_size;
199
200 drm_handle_t tex_handle;
201 int tex_offset;
202 int tex_size;
203 int log_tex_granularity;
204 int pitch;
205 int rotation;
206 int rotated_offset;
207 int rotated_size;
208 int rotated_pitch;
209 int virtualX, virtualY;
210
211 unsigned int front_tiled;
212 unsigned int back_tiled;
213 unsigned int depth_tiled;
214 unsigned int rotated_tiled;
215 unsigned int rotated2_tiled;
216
217 int pipeA_x;
218 int pipeA_y;
219 int pipeA_w;
220 int pipeA_h;
221 int pipeB_x;
222 int pipeB_y;
223 int pipeB_w;
224 int pipeB_h;
225
226
227 drm_handle_t unused_handle;
228 __u32 unused1, unused2, unused3;
229
230
231
232
233 __u32 front_bo_handle;
234 __u32 back_bo_handle;
235 __u32 unused_bo_handle;
236 __u32 depth_bo_handle;
237
238} drm_i915_sarea_t;
239
240
241#define planeA_x pipeA_x
242#define planeA_y pipeA_y
243#define planeA_w pipeA_w
244#define planeA_h pipeA_h
245#define planeB_x pipeB_x
246#define planeB_y pipeB_y
247#define planeB_w pipeB_w
248#define planeB_h pipeB_h
249
250
251
252#define I915_BOX_RING_EMPTY 0x1
253#define I915_BOX_FLIP 0x2
254#define I915_BOX_WAIT 0x4
255#define I915_BOX_TEXTURE_LOAD 0x8
256#define I915_BOX_LOST_CONTEXT 0x10
257
258
259
260
261
262
263
264
265#define DRM_I915_INIT 0x00
266#define DRM_I915_FLUSH 0x01
267#define DRM_I915_FLIP 0x02
268#define DRM_I915_BATCHBUFFER 0x03
269#define DRM_I915_IRQ_EMIT 0x04
270#define DRM_I915_IRQ_WAIT 0x05
271#define DRM_I915_GETPARAM 0x06
272#define DRM_I915_SETPARAM 0x07
273#define DRM_I915_ALLOC 0x08
274#define DRM_I915_FREE 0x09
275#define DRM_I915_INIT_HEAP 0x0a
276#define DRM_I915_CMDBUFFER 0x0b
277#define DRM_I915_DESTROY_HEAP 0x0c
278#define DRM_I915_SET_VBLANK_PIPE 0x0d
279#define DRM_I915_GET_VBLANK_PIPE 0x0e
280#define DRM_I915_VBLANK_SWAP 0x0f
281#define DRM_I915_HWS_ADDR 0x11
282#define DRM_I915_GEM_INIT 0x13
283#define DRM_I915_GEM_EXECBUFFER 0x14
284#define DRM_I915_GEM_PIN 0x15
285#define DRM_I915_GEM_UNPIN 0x16
286#define DRM_I915_GEM_BUSY 0x17
287#define DRM_I915_GEM_THROTTLE 0x18
288#define DRM_I915_GEM_ENTERVT 0x19
289#define DRM_I915_GEM_LEAVEVT 0x1a
290#define DRM_I915_GEM_CREATE 0x1b
291#define DRM_I915_GEM_PREAD 0x1c
292#define DRM_I915_GEM_PWRITE 0x1d
293#define DRM_I915_GEM_MMAP 0x1e
294#define DRM_I915_GEM_SET_DOMAIN 0x1f
295#define DRM_I915_GEM_SW_FINISH 0x20
296#define DRM_I915_GEM_SET_TILING 0x21
297#define DRM_I915_GEM_GET_TILING 0x22
298#define DRM_I915_GEM_GET_APERTURE 0x23
299#define DRM_I915_GEM_MMAP_GTT 0x24
300#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
301#define DRM_I915_GEM_MADVISE 0x26
302#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
303#define DRM_I915_OVERLAY_ATTRS 0x28
304#define DRM_I915_GEM_EXECBUFFER2 0x29
305#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
306#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
307#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
308#define DRM_I915_GEM_WAIT 0x2c
309#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
310#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
311#define DRM_I915_GEM_SET_CACHING 0x2f
312#define DRM_I915_GEM_GET_CACHING 0x30
313#define DRM_I915_REG_READ 0x31
314#define DRM_I915_GET_RESET_STATS 0x32
315#define DRM_I915_GEM_USERPTR 0x33
316#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
317#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
318#define DRM_I915_PERF_OPEN 0x36
319#define DRM_I915_PERF_ADD_CONFIG 0x37
320#define DRM_I915_PERF_REMOVE_CONFIG 0x38
321#define DRM_I915_QUERY 0x39
322
323#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
324#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
325#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
326#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
327#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
328#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
329#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
330#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
331#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
332#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
333#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
334#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
335#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
336#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
337#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
338#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
339#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
340#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
341#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
342#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
343#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
344#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
345#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
346#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
347#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
348#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
349#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
350#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
351#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
352#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
353#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
354#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
355#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
356#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
357#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
358#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
359#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
360#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
361#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
362#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
363#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
364#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
365#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
366#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
367#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
368#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
369#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
370#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
371#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
372#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
373#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
374#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
375#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
376#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
377#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
378#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
379#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
380
381
382
383
384typedef struct drm_i915_batchbuffer {
385 int start;
386 int used;
387 int DR1;
388 int DR4;
389 int num_cliprects;
390 struct drm_clip_rect __user *cliprects;
391} drm_i915_batchbuffer_t;
392
393
394
395
396typedef struct _drm_i915_cmdbuffer {
397 char __user *buf;
398 int sz;
399 int DR1;
400 int DR4;
401 int num_cliprects;
402 struct drm_clip_rect __user *cliprects;
403} drm_i915_cmdbuffer_t;
404
405
406
407typedef struct drm_i915_irq_emit {
408 int __user *irq_seq;
409} drm_i915_irq_emit_t;
410
411typedef struct drm_i915_irq_wait {
412 int irq_seq;
413} drm_i915_irq_wait_t;
414
415
416
417
418
419#define I915_GEM_PPGTT_NONE 0
420#define I915_GEM_PPGTT_ALIASING 1
421#define I915_GEM_PPGTT_FULL 2
422
423
424
425#define I915_PARAM_IRQ_ACTIVE 1
426#define I915_PARAM_ALLOW_BATCHBUFFER 2
427#define I915_PARAM_LAST_DISPATCH 3
428#define I915_PARAM_CHIPSET_ID 4
429#define I915_PARAM_HAS_GEM 5
430#define I915_PARAM_NUM_FENCES_AVAIL 6
431#define I915_PARAM_HAS_OVERLAY 7
432#define I915_PARAM_HAS_PAGEFLIPPING 8
433#define I915_PARAM_HAS_EXECBUF2 9
434#define I915_PARAM_HAS_BSD 10
435#define I915_PARAM_HAS_BLT 11
436#define I915_PARAM_HAS_RELAXED_FENCING 12
437#define I915_PARAM_HAS_COHERENT_RINGS 13
438#define I915_PARAM_HAS_EXEC_CONSTANTS 14
439#define I915_PARAM_HAS_RELAXED_DELTA 15
440#define I915_PARAM_HAS_GEN7_SOL_RESET 16
441#define I915_PARAM_HAS_LLC 17
442#define I915_PARAM_HAS_ALIASING_PPGTT 18
443#define I915_PARAM_HAS_WAIT_TIMEOUT 19
444#define I915_PARAM_HAS_SEMAPHORES 20
445#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
446#define I915_PARAM_HAS_VEBOX 22
447#define I915_PARAM_HAS_SECURE_BATCHES 23
448#define I915_PARAM_HAS_PINNED_BATCHES 24
449#define I915_PARAM_HAS_EXEC_NO_RELOC 25
450#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
451#define I915_PARAM_HAS_WT 27
452#define I915_PARAM_CMD_PARSER_VERSION 28
453#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
454#define I915_PARAM_MMAP_VERSION 30
455#define I915_PARAM_HAS_BSD2 31
456#define I915_PARAM_REVISION 32
457#define I915_PARAM_SUBSLICE_TOTAL 33
458#define I915_PARAM_EU_TOTAL 34
459#define I915_PARAM_HAS_GPU_RESET 35
460#define I915_PARAM_HAS_RESOURCE_STREAMER 36
461#define I915_PARAM_HAS_EXEC_SOFTPIN 37
462#define I915_PARAM_HAS_POOLED_EU 38
463#define I915_PARAM_MIN_EU_IN_POOL 39
464#define I915_PARAM_MMAP_GTT_VERSION 40
465
466
467
468
469
470
471
472
473
474
475#define I915_PARAM_HAS_SCHEDULER 41
476#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
477#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
478#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
479
480#define I915_PARAM_HUC_STATUS 42
481
482
483
484
485
486#define I915_PARAM_HAS_EXEC_ASYNC 43
487
488
489
490
491
492
493#define I915_PARAM_HAS_EXEC_FENCE 44
494
495
496
497
498
499#define I915_PARAM_HAS_EXEC_CAPTURE 45
500
501#define I915_PARAM_SLICE_MASK 46
502
503
504
505
506#define I915_PARAM_SUBSLICE_MASK 47
507
508
509
510
511
512#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
513
514
515
516
517#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
533
534
535
536
537
538#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560#define I915_PARAM_MMAP_GTT_COHERENT 52
561
562typedef struct drm_i915_getparam {
563 __s32 param;
564
565
566
567
568 int __user *value;
569} drm_i915_getparam_t;
570
571
572
573#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
574#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
575#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
576#define I915_SETPARAM_NUM_USED_FENCES 4
577
578typedef struct drm_i915_setparam {
579 int param;
580 int value;
581} drm_i915_setparam_t;
582
583
584
585#define I915_MEM_REGION_AGP 1
586
587typedef struct drm_i915_mem_alloc {
588 int region;
589 int alignment;
590 int size;
591 int __user *region_offset;
592} drm_i915_mem_alloc_t;
593
594typedef struct drm_i915_mem_free {
595 int region;
596 int region_offset;
597} drm_i915_mem_free_t;
598
599typedef struct drm_i915_mem_init_heap {
600 int region;
601 int size;
602 int start;
603} drm_i915_mem_init_heap_t;
604
605
606
607
608typedef struct drm_i915_mem_destroy_heap {
609 int region;
610} drm_i915_mem_destroy_heap_t;
611
612
613
614#define DRM_I915_VBLANK_PIPE_A 1
615#define DRM_I915_VBLANK_PIPE_B 2
616
617typedef struct drm_i915_vblank_pipe {
618 int pipe;
619} drm_i915_vblank_pipe_t;
620
621
622
623typedef struct drm_i915_vblank_swap {
624 drm_drawable_t drawable;
625 enum drm_vblank_seq_type seqtype;
626 unsigned int sequence;
627} drm_i915_vblank_swap_t;
628
629typedef struct drm_i915_hws_addr {
630 __u64 addr;
631} drm_i915_hws_addr_t;
632
633struct drm_i915_gem_init {
634
635
636
637
638 __u64 gtt_start;
639
640
641
642
643 __u64 gtt_end;
644};
645
646struct drm_i915_gem_create {
647
648
649
650
651
652 __u64 size;
653
654
655
656
657
658 __u32 handle;
659 __u32 pad;
660};
661
662struct drm_i915_gem_pread {
663
664 __u32 handle;
665 __u32 pad;
666
667 __u64 offset;
668
669 __u64 size;
670
671
672
673
674
675 __u64 data_ptr;
676};
677
678struct drm_i915_gem_pwrite {
679
680 __u32 handle;
681 __u32 pad;
682
683 __u64 offset;
684
685 __u64 size;
686
687
688
689
690
691 __u64 data_ptr;
692};
693
694struct drm_i915_gem_mmap {
695
696 __u32 handle;
697 __u32 pad;
698
699 __u64 offset;
700
701
702
703
704
705 __u64 size;
706
707
708
709
710
711 __u64 addr_ptr;
712
713
714
715
716
717
718 __u64 flags;
719#define I915_MMAP_WC 0x1
720};
721
722struct drm_i915_gem_mmap_gtt {
723
724 __u32 handle;
725 __u32 pad;
726
727
728
729
730
731 __u64 offset;
732};
733
734struct drm_i915_gem_set_domain {
735
736 __u32 handle;
737
738
739 __u32 read_domains;
740
741
742 __u32 write_domain;
743};
744
745struct drm_i915_gem_sw_finish {
746
747 __u32 handle;
748};
749
750struct drm_i915_gem_relocation_entry {
751
752
753
754
755
756
757
758
759 __u32 target_handle;
760
761
762
763
764
765 __u32 delta;
766
767
768 __u64 offset;
769
770
771
772
773
774
775
776
777
778 __u64 presumed_offset;
779
780
781
782
783 __u32 read_domains;
784
785
786
787
788
789
790
791
792 __u32 write_domain;
793};
794
795
796
797
798
799
800
801
802
803#define I915_GEM_DOMAIN_CPU 0x00000001
804
805#define I915_GEM_DOMAIN_RENDER 0x00000002
806
807#define I915_GEM_DOMAIN_SAMPLER 0x00000004
808
809#define I915_GEM_DOMAIN_COMMAND 0x00000008
810
811#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
812
813#define I915_GEM_DOMAIN_VERTEX 0x00000020
814
815#define I915_GEM_DOMAIN_GTT 0x00000040
816
817#define I915_GEM_DOMAIN_WC 0x00000080
818
819
820struct drm_i915_gem_exec_object {
821
822
823
824
825 __u32 handle;
826
827
828 __u32 relocation_count;
829
830
831
832
833 __u64 relocs_ptr;
834
835
836 __u64 alignment;
837
838
839
840
841
842 __u64 offset;
843};
844
845struct drm_i915_gem_execbuffer {
846
847
848
849
850
851
852
853
854
855
856 __u64 buffers_ptr;
857 __u32 buffer_count;
858
859
860 __u32 batch_start_offset;
861
862 __u32 batch_len;
863 __u32 DR1;
864 __u32 DR4;
865 __u32 num_cliprects;
866
867 __u64 cliprects_ptr;
868};
869
870struct drm_i915_gem_exec_object2 {
871
872
873
874
875 __u32 handle;
876
877
878 __u32 relocation_count;
879
880
881
882
883 __u64 relocs_ptr;
884
885
886 __u64 alignment;
887
888
889
890
891
892
893
894
895
896 __u64 offset;
897
898#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
899#define EXEC_OBJECT_NEEDS_GTT (1<<1)
900#define EXEC_OBJECT_WRITE (1<<2)
901#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
902#define EXEC_OBJECT_PINNED (1<<4)
903#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924#define EXEC_OBJECT_ASYNC (1<<6)
925
926
927
928
929
930
931#define EXEC_OBJECT_CAPTURE (1<<7)
932
933#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
934 __u64 flags;
935
936 union {
937 __u64 rsvd1;
938 __u64 pad_to_size;
939 };
940 __u64 rsvd2;
941};
942
943struct drm_i915_gem_exec_fence {
944
945
946
947 __u32 handle;
948
949#define I915_EXEC_FENCE_WAIT (1<<0)
950#define I915_EXEC_FENCE_SIGNAL (1<<1)
951#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
952 __u32 flags;
953};
954
955struct drm_i915_gem_execbuffer2 {
956
957
958
959 __u64 buffers_ptr;
960 __u32 buffer_count;
961
962
963 __u32 batch_start_offset;
964
965 __u32 batch_len;
966 __u32 DR1;
967 __u32 DR4;
968 __u32 num_cliprects;
969
970
971
972
973
974 __u64 cliprects_ptr;
975#define I915_EXEC_RING_MASK (7<<0)
976#define I915_EXEC_DEFAULT (0<<0)
977#define I915_EXEC_RENDER (1<<0)
978#define I915_EXEC_BSD (2<<0)
979#define I915_EXEC_BLT (3<<0)
980#define I915_EXEC_VEBOX (4<<0)
981
982
983
984
985
986
987
988#define I915_EXEC_CONSTANTS_MASK (3<<6)
989#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)
990#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
991#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)
992 __u64 flags;
993 __u64 rsvd1;
994 __u64 rsvd2;
995};
996
997
998#define I915_EXEC_GEN7_SOL_RESET (1<<8)
999
1000
1001
1002
1003#define I915_EXEC_SECURE (1<<9)
1004
1005
1006
1007
1008
1009
1010
1011
1012#define I915_EXEC_IS_PINNED (1<<10)
1013
1014
1015
1016
1017
1018
1019#define I915_EXEC_NO_RELOC (1<<11)
1020
1021
1022
1023
1024#define I915_EXEC_HANDLE_LUT (1<<12)
1025
1026
1027#define I915_EXEC_BSD_SHIFT (13)
1028#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1029
1030#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1031#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1032#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1033
1034
1035
1036
1037#define I915_EXEC_RESOURCE_STREAMER (1<<15)
1038
1039
1040
1041
1042
1043
1044
1045#define I915_EXEC_FENCE_IN (1<<16)
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062#define I915_EXEC_FENCE_OUT (1<<17)
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073#define I915_EXEC_BATCH_FIRST (1<<18)
1074
1075
1076
1077
1078
1079#define I915_EXEC_FENCE_ARRAY (1<<19)
1080
1081#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
1082
1083#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1084#define i915_execbuffer2_set_context_id(eb2, context) \
1085 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1086#define i915_execbuffer2_get_context_id(eb2) \
1087 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1088
1089struct drm_i915_gem_pin {
1090
1091 __u32 handle;
1092 __u32 pad;
1093
1094
1095 __u64 alignment;
1096
1097
1098 __u64 offset;
1099};
1100
1101struct drm_i915_gem_unpin {
1102
1103 __u32 handle;
1104 __u32 pad;
1105};
1106
1107struct drm_i915_gem_busy {
1108
1109 __u32 handle;
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155 __u32 busy;
1156};
1157
1158
1159
1160
1161
1162
1163
1164#define I915_CACHING_NONE 0
1165
1166
1167
1168
1169
1170
1171
1172#define I915_CACHING_CACHED 1
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183#define I915_CACHING_DISPLAY 2
1184
1185struct drm_i915_gem_caching {
1186
1187
1188 __u32 handle;
1189
1190
1191
1192
1193
1194
1195
1196 __u32 caching;
1197};
1198
1199#define I915_TILING_NONE 0
1200#define I915_TILING_X 1
1201#define I915_TILING_Y 2
1202#define I915_TILING_LAST I915_TILING_Y
1203
1204#define I915_BIT_6_SWIZZLE_NONE 0
1205#define I915_BIT_6_SWIZZLE_9 1
1206#define I915_BIT_6_SWIZZLE_9_10 2
1207#define I915_BIT_6_SWIZZLE_9_11 3
1208#define I915_BIT_6_SWIZZLE_9_10_11 4
1209
1210#define I915_BIT_6_SWIZZLE_UNKNOWN 5
1211
1212#define I915_BIT_6_SWIZZLE_9_17 6
1213#define I915_BIT_6_SWIZZLE_9_10_17 7
1214
1215struct drm_i915_gem_set_tiling {
1216
1217 __u32 handle;
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231 __u32 tiling_mode;
1232
1233
1234
1235
1236
1237 __u32 stride;
1238
1239
1240
1241
1242
1243 __u32 swizzle_mode;
1244};
1245
1246struct drm_i915_gem_get_tiling {
1247
1248 __u32 handle;
1249
1250
1251
1252
1253
1254 __u32 tiling_mode;
1255
1256
1257
1258
1259
1260 __u32 swizzle_mode;
1261
1262
1263
1264
1265
1266 __u32 phys_swizzle_mode;
1267};
1268
1269struct drm_i915_gem_get_aperture {
1270
1271 __u64 aper_size;
1272
1273
1274
1275
1276
1277 __u64 aper_available_size;
1278};
1279
1280struct drm_i915_get_pipe_from_crtc_id {
1281
1282 __u32 crtc_id;
1283
1284
1285 __u32 pipe;
1286};
1287
1288#define I915_MADV_WILLNEED 0
1289#define I915_MADV_DONTNEED 1
1290#define __I915_MADV_PURGED 2
1291
1292struct drm_i915_gem_madvise {
1293
1294 __u32 handle;
1295
1296
1297
1298
1299 __u32 madv;
1300
1301
1302 __u32 retained;
1303};
1304
1305
1306#define I915_OVERLAY_TYPE_MASK 0xff
1307#define I915_OVERLAY_YUV_PLANAR 0x01
1308#define I915_OVERLAY_YUV_PACKED 0x02
1309#define I915_OVERLAY_RGB 0x03
1310
1311#define I915_OVERLAY_DEPTH_MASK 0xff00
1312#define I915_OVERLAY_RGB24 0x1000
1313#define I915_OVERLAY_RGB16 0x2000
1314#define I915_OVERLAY_RGB15 0x3000
1315#define I915_OVERLAY_YUV422 0x0100
1316#define I915_OVERLAY_YUV411 0x0200
1317#define I915_OVERLAY_YUV420 0x0300
1318#define I915_OVERLAY_YUV410 0x0400
1319
1320#define I915_OVERLAY_SWAP_MASK 0xff0000
1321#define I915_OVERLAY_NO_SWAP 0x000000
1322#define I915_OVERLAY_UV_SWAP 0x010000
1323#define I915_OVERLAY_Y_SWAP 0x020000
1324#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1325
1326#define I915_OVERLAY_FLAGS_MASK 0xff000000
1327#define I915_OVERLAY_ENABLE 0x01000000
1328
1329struct drm_intel_overlay_put_image {
1330
1331 __u32 flags;
1332
1333 __u32 bo_handle;
1334
1335 __u16 stride_Y;
1336 __u16 stride_UV;
1337 __u32 offset_Y;
1338 __u32 offset_U;
1339 __u32 offset_V;
1340
1341 __u16 src_width;
1342 __u16 src_height;
1343
1344 __u16 src_scan_width;
1345 __u16 src_scan_height;
1346
1347 __u32 crtc_id;
1348 __u16 dst_x;
1349 __u16 dst_y;
1350 __u16 dst_width;
1351 __u16 dst_height;
1352};
1353
1354
1355#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1356#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1357#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1358struct drm_intel_overlay_attrs {
1359 __u32 flags;
1360 __u32 color_key;
1361 __s32 brightness;
1362 __u32 contrast;
1363 __u32 saturation;
1364 __u32 gamma0;
1365 __u32 gamma1;
1366 __u32 gamma2;
1367 __u32 gamma3;
1368 __u32 gamma4;
1369 __u32 gamma5;
1370};
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393#define I915_SET_COLORKEY_NONE (1<<0)
1394
1395
1396#define I915_SET_COLORKEY_DESTINATION (1<<1)
1397#define I915_SET_COLORKEY_SOURCE (1<<2)
1398struct drm_intel_sprite_colorkey {
1399 __u32 plane_id;
1400 __u32 min_value;
1401 __u32 channel_mask;
1402 __u32 max_value;
1403 __u32 flags;
1404};
1405
1406struct drm_i915_gem_wait {
1407
1408 __u32 bo_handle;
1409 __u32 flags;
1410
1411 __s64 timeout_ns;
1412};
1413
1414struct drm_i915_gem_context_create {
1415
1416 __u32 ctx_id;
1417 __u32 pad;
1418};
1419
1420struct drm_i915_gem_context_destroy {
1421 __u32 ctx_id;
1422 __u32 pad;
1423};
1424
1425struct drm_i915_reg_read {
1426
1427
1428
1429
1430
1431
1432 __u64 offset;
1433#define I915_REG_READ_8B_WA (1ul << 0)
1434
1435 __u64 val;
1436};
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446struct drm_i915_reset_stats {
1447 __u32 ctx_id;
1448 __u32 flags;
1449
1450
1451 __u32 reset_count;
1452
1453
1454 __u32 batch_active;
1455
1456
1457 __u32 batch_pending;
1458
1459 __u32 pad;
1460};
1461
1462struct drm_i915_gem_userptr {
1463 __u64 user_ptr;
1464 __u64 user_size;
1465 __u32 flags;
1466#define I915_USERPTR_READ_ONLY 0x1
1467#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1468
1469
1470
1471
1472
1473 __u32 handle;
1474};
1475
1476struct drm_i915_gem_context_param {
1477 __u32 ctx_id;
1478 __u32 size;
1479 __u64 param;
1480#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1481#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1482#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1483#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1484#define I915_CONTEXT_PARAM_BANNABLE 0x5
1485#define I915_CONTEXT_PARAM_PRIORITY 0x6
1486#define I915_CONTEXT_MAX_USER_PRIORITY 1023
1487#define I915_CONTEXT_DEFAULT_PRIORITY 0
1488#define I915_CONTEXT_MIN_USER_PRIORITY -1023
1489 __u64 value;
1490};
1491
1492enum drm_i915_oa_format {
1493 I915_OA_FORMAT_A13 = 1,
1494 I915_OA_FORMAT_A29,
1495 I915_OA_FORMAT_A13_B8_C8,
1496 I915_OA_FORMAT_B4_C8,
1497 I915_OA_FORMAT_A45_B8_C8,
1498 I915_OA_FORMAT_B4_C8_A16,
1499 I915_OA_FORMAT_C4_B8,
1500
1501
1502 I915_OA_FORMAT_A12,
1503 I915_OA_FORMAT_A12_B8_C8,
1504 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1505
1506 I915_OA_FORMAT_MAX
1507};
1508
1509enum drm_i915_perf_property_id {
1510
1511
1512
1513
1514
1515 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1516
1517
1518
1519
1520
1521 DRM_I915_PERF_PROP_SAMPLE_OA,
1522
1523
1524
1525
1526
1527 DRM_I915_PERF_PROP_OA_METRICS_SET,
1528
1529
1530
1531
1532 DRM_I915_PERF_PROP_OA_FORMAT,
1533
1534
1535
1536
1537
1538
1539
1540
1541 DRM_I915_PERF_PROP_OA_EXPONENT,
1542
1543 DRM_I915_PERF_PROP_MAX
1544};
1545
1546struct drm_i915_perf_open_param {
1547 __u32 flags;
1548#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1549#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1550#define I915_PERF_FLAG_DISABLED (1<<2)
1551
1552
1553 __u32 num_properties;
1554
1555
1556
1557
1558
1559 __u64 properties_ptr;
1560};
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1573
1574
1575
1576
1577
1578
1579#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1580
1581
1582
1583
1584struct drm_i915_perf_record_header {
1585 __u32 type;
1586 __u16 pad;
1587 __u16 size;
1588};
1589
1590enum drm_i915_perf_record_type {
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611 DRM_I915_PERF_RECORD_SAMPLE = 1,
1612
1613
1614
1615
1616
1617
1618
1619 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1620
1621
1622
1623
1624 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1625
1626 DRM_I915_PERF_RECORD_MAX
1627};
1628
1629
1630
1631
1632struct drm_i915_perf_oa_config {
1633
1634 char uuid[36];
1635
1636 __u32 n_mux_regs;
1637 __u32 n_boolean_regs;
1638 __u32 n_flex_regs;
1639
1640
1641
1642
1643
1644
1645 __u64 mux_regs_ptr;
1646 __u64 boolean_regs_ptr;
1647 __u64 flex_regs_ptr;
1648};
1649
1650struct drm_i915_query_item {
1651 __u64 query_id;
1652#define DRM_I915_QUERY_TOPOLOGY_INFO 1
1653
1654
1655
1656
1657
1658
1659
1660 __s32 length;
1661
1662
1663
1664
1665 __u32 flags;
1666
1667
1668
1669
1670
1671
1672 __u64 data_ptr;
1673};
1674
1675struct drm_i915_query {
1676 __u32 num_items;
1677
1678
1679
1680
1681 __u32 flags;
1682
1683
1684
1685
1686 __u64 items_ptr;
1687};
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716struct drm_i915_query_topology_info {
1717
1718
1719
1720 __u16 flags;
1721
1722 __u16 max_slices;
1723 __u16 max_subslices;
1724 __u16 max_eus_per_subslice;
1725
1726
1727
1728
1729 __u16 subslice_offset;
1730
1731
1732
1733
1734
1735 __u16 subslice_stride;
1736
1737
1738
1739
1740 __u16 eu_offset;
1741
1742
1743
1744
1745 __u16 eu_stride;
1746
1747 __u8 data[];
1748};
1749
1750#if defined(__cplusplus)
1751}
1752#endif
1753
1754#endif
1755