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13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20#include <asm/war.h>
21
22
23
24
25
26#ifndef __STR
27#define __STR(x) #x
28#endif
29#ifndef STR
30#define STR(x) __STR(x)
31#endif
32
33
34
35
36#ifdef __ASSEMBLY__
37#define _ULCAST_
38#define _U64CAST_
39#else
40#define _ULCAST_ (unsigned long)
41#define _U64CAST_ (u64)
42#endif
43
44
45
46
47#define CP0_INDEX $0
48#define CP0_RANDOM $1
49#define CP0_ENTRYLO0 $2
50#define CP0_ENTRYLO1 $3
51#define CP0_CONF $3
52#define CP0_GLOBALNUMBER $3, 1
53#define CP0_CONTEXT $4
54#define CP0_PAGEMASK $5
55#define CP0_PAGEGRAIN $5, 1
56#define CP0_SEGCTL0 $5, 2
57#define CP0_SEGCTL1 $5, 3
58#define CP0_SEGCTL2 $5, 4
59#define CP0_WIRED $6
60#define CP0_INFO $7
61#define CP0_HWRENA $7
62#define CP0_BADVADDR $8
63#define CP0_BADINSTR $8, 1
64#define CP0_COUNT $9
65#define CP0_ENTRYHI $10
66#define CP0_GUESTCTL1 $10, 4
67#define CP0_GUESTCTL2 $10, 5
68#define CP0_GUESTCTL3 $10, 6
69#define CP0_COMPARE $11
70#define CP0_GUESTCTL0EXT $11, 4
71#define CP0_STATUS $12
72#define CP0_GUESTCTL0 $12, 6
73#define CP0_GTOFFSET $12, 7
74#define CP0_CAUSE $13
75#define CP0_EPC $14
76#define CP0_PRID $15
77#define CP0_EBASE $15, 1
78#define CP0_CMGCRBASE $15, 3
79#define CP0_CONFIG $16
80#define CP0_CONFIG3 $16, 3
81#define CP0_CONFIG5 $16, 5
82#define CP0_CONFIG6 $16, 6
83#define CP0_LLADDR $17
84#define CP0_WATCHLO $18
85#define CP0_WATCHHI $19
86#define CP0_XCONTEXT $20
87#define CP0_FRAMEMASK $21
88#define CP0_DIAGNOSTIC $22
89#define CP0_DEBUG $23
90#define CP0_DEPC $24
91#define CP0_PERFORMANCE $25
92#define CP0_ECC $26
93#define CP0_CACHEERR $27
94#define CP0_TAGLO $28
95#define CP0_TAGHI $29
96#define CP0_ERROREPC $30
97#define CP0_DESAVE $31
98
99
100
101
102
103
104
105#define CP0_IBASE $0
106#define CP0_IBOUND $1
107#define CP0_DBASE $2
108#define CP0_DBOUND $3
109#define CP0_CALG $17
110#define CP0_IWATCH $18
111#define CP0_DWATCH $19
112
113
114
115
116#define CP0_S1_DERRADDR0 $26
117#define CP0_S1_DERRADDR1 $27
118#define CP0_S1_INTCONTROL $20
119
120
121
122
123#define CP0_S2_SRSCTL $12
124
125
126
127
128#define CP0_S3_SRSMAP $12
129
130
131
132
133#define CP0_TX39_CACHE $7
134
135
136
137#define ENTRYLO_G (_ULCAST_(1) << 0)
138#define ENTRYLO_V (_ULCAST_(1) << 1)
139#define ENTRYLO_D (_ULCAST_(1) << 2)
140#define ENTRYLO_C_SHIFT 3
141#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
142
143
144#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
148
149
150#define MIPS_ENTRYLO_PFN_SHIFT 6
151#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
153
154
155
156
157#define MIPS_GLOBALNUMBER_VP_SHF 0
158#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159#define MIPS_GLOBALNUMBER_CORE_SHF 8
160#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
162#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
163
164
165
166
167#ifdef CONFIG_CPU_VR41XX
168
169
170
171#define PM_1K 0x00000000
172#define PM_4K 0x00001800
173#define PM_16K 0x00007800
174#define PM_64K 0x0001f800
175#define PM_256K 0x0007f800
176
177#else
178
179#define PM_4K 0x00000000
180#define PM_8K 0x00002000
181#define PM_16K 0x00006000
182#define PM_32K 0x0000e000
183#define PM_64K 0x0001e000
184#define PM_128K 0x0003e000
185#define PM_256K 0x0007e000
186#define PM_512K 0x000fe000
187#define PM_1M 0x001fe000
188#define PM_2M 0x003fe000
189#define PM_4M 0x007fe000
190#define PM_8M 0x00ffe000
191#define PM_16M 0x01ffe000
192#define PM_32M 0x03ffe000
193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000
196
197#endif
198
199
200
201
202#ifdef CONFIG_PAGE_SIZE_4KB
203#define PM_DEFAULT_MASK PM_4K
204#elif defined(CONFIG_PAGE_SIZE_8KB)
205#define PM_DEFAULT_MASK PM_8K
206#elif defined(CONFIG_PAGE_SIZE_16KB)
207#define PM_DEFAULT_MASK PM_16K
208#elif defined(CONFIG_PAGE_SIZE_32KB)
209#define PM_DEFAULT_MASK PM_32K
210#elif defined(CONFIG_PAGE_SIZE_64KB)
211#define PM_DEFAULT_MASK PM_64K
212#else
213#error Bad page size configuration!
214#endif
215
216
217
218
219#ifdef CONFIG_PAGE_SIZE_4KB
220#define PM_HUGE_MASK PM_1M
221#elif defined(CONFIG_PAGE_SIZE_8KB)
222#define PM_HUGE_MASK PM_4M
223#elif defined(CONFIG_PAGE_SIZE_16KB)
224#define PM_HUGE_MASK PM_16M
225#elif defined(CONFIG_PAGE_SIZE_32KB)
226#define PM_HUGE_MASK PM_64M
227#elif defined(CONFIG_PAGE_SIZE_64KB)
228#define PM_HUGE_MASK PM_256M
229#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
230#error Bad page size configuration for hugetlbfs!
231#endif
232
233
234
235
236#define MIPSR6_WIRED_LIMIT_SHIFT 16
237#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
238#define MIPSR6_WIRED_WIRED_SHIFT 0
239#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
240
241
242
243
244#define PL_4K 12
245#define PL_16K 14
246#define PL_64K 16
247#define PL_256K 18
248#define PL_1M 20
249#define PL_4M 22
250#define PL_16M 24
251#define PL_64M 26
252#define PL_256M 28
253
254
255
256
257#define PG_RIE (_ULCAST_(1) << 31)
258#define PG_XIE (_ULCAST_(1) << 30)
259#define PG_ELPA (_ULCAST_(1) << 29)
260#define PG_ESP (_ULCAST_(1) << 28)
261#define PG_IEC (_ULCAST_(1) << 27)
262
263
264#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
265#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
266#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
267
268
269
270
271#define IE_SW0 (_ULCAST_(1) << 8)
272#define IE_SW1 (_ULCAST_(1) << 9)
273#define IE_IRQ0 (_ULCAST_(1) << 10)
274#define IE_IRQ1 (_ULCAST_(1) << 11)
275#define IE_IRQ2 (_ULCAST_(1) << 12)
276#define IE_IRQ3 (_ULCAST_(1) << 13)
277#define IE_IRQ4 (_ULCAST_(1) << 14)
278#define IE_IRQ5 (_ULCAST_(1) << 15)
279
280
281
282
283#define C_SW0 (_ULCAST_(1) << 8)
284#define C_SW1 (_ULCAST_(1) << 9)
285#define C_IRQ0 (_ULCAST_(1) << 10)
286#define C_IRQ1 (_ULCAST_(1) << 11)
287#define C_IRQ2 (_ULCAST_(1) << 12)
288#define C_IRQ3 (_ULCAST_(1) << 13)
289#define C_IRQ4 (_ULCAST_(1) << 14)
290#define C_IRQ5 (_ULCAST_(1) << 15)
291
292
293
294
295#define ST0_IE 0x00000001
296#define ST0_EXL 0x00000002
297#define ST0_ERL 0x00000004
298#define ST0_KSU 0x00000018
299# define KSU_USER 0x00000010
300# define KSU_SUPERVISOR 0x00000008
301# define KSU_KERNEL 0x00000000
302#define ST0_UX 0x00000020
303#define ST0_SX 0x00000040
304#define ST0_KX 0x00000080
305#define ST0_DE 0x00010000
306#define ST0_CE 0x00020000
307
308
309
310
311
312
313#define ST0_CO 0x08000000
314
315
316
317
318#define ST0_IEC 0x00000001
319#define ST0_KUC 0x00000002
320#define ST0_IEP 0x00000004
321#define ST0_KUP 0x00000008
322#define ST0_IEO 0x00000010
323#define ST0_KUO 0x00000020
324
325#define ST0_ISC 0x00010000
326#define ST0_SWC 0x00020000
327#define ST0_CM 0x00080000
328
329
330
331
332#define ST0_UM (_ULCAST_(1) << 4)
333#define ST0_IL (_ULCAST_(1) << 23)
334#define ST0_DL (_ULCAST_(1) << 24)
335
336
337
338
339#define ST0_MX 0x01000000
340
341
342
343
344#define ST0_IM 0x0000ff00
345#define STATUSB_IP0 8
346#define STATUSF_IP0 (_ULCAST_(1) << 8)
347#define STATUSB_IP1 9
348#define STATUSF_IP1 (_ULCAST_(1) << 9)
349#define STATUSB_IP2 10
350#define STATUSF_IP2 (_ULCAST_(1) << 10)
351#define STATUSB_IP3 11
352#define STATUSF_IP3 (_ULCAST_(1) << 11)
353#define STATUSB_IP4 12
354#define STATUSF_IP4 (_ULCAST_(1) << 12)
355#define STATUSB_IP5 13
356#define STATUSF_IP5 (_ULCAST_(1) << 13)
357#define STATUSB_IP6 14
358#define STATUSF_IP6 (_ULCAST_(1) << 14)
359#define STATUSB_IP7 15
360#define STATUSF_IP7 (_ULCAST_(1) << 15)
361#define STATUSB_IP8 0
362#define STATUSF_IP8 (_ULCAST_(1) << 0)
363#define STATUSB_IP9 1
364#define STATUSF_IP9 (_ULCAST_(1) << 1)
365#define STATUSB_IP10 2
366#define STATUSF_IP10 (_ULCAST_(1) << 2)
367#define STATUSB_IP11 3
368#define STATUSF_IP11 (_ULCAST_(1) << 3)
369#define STATUSB_IP12 4
370#define STATUSF_IP12 (_ULCAST_(1) << 4)
371#define STATUSB_IP13 5
372#define STATUSF_IP13 (_ULCAST_(1) << 5)
373#define STATUSB_IP14 6
374#define STATUSF_IP14 (_ULCAST_(1) << 6)
375#define STATUSB_IP15 7
376#define STATUSF_IP15 (_ULCAST_(1) << 7)
377#define ST0_CH 0x00040000
378#define ST0_NMI 0x00080000
379#define ST0_SR 0x00100000
380#define ST0_TS 0x00200000
381#define ST0_BEV 0x00400000
382#define ST0_RE 0x02000000
383#define ST0_FR 0x04000000
384#define ST0_CU 0xf0000000
385#define ST0_CU0 0x10000000
386#define ST0_CU1 0x20000000
387#define ST0_CU2 0x40000000
388#define ST0_CU3 0x80000000
389#define ST0_XX 0x80000000
390
391
392
393
394#define INTCTLB_IPFDC 23
395#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
396#define INTCTLB_IPPCI 26
397#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
398#define INTCTLB_IPTI 29
399#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
400
401
402
403
404
405
406#define CAUSEB_EXCCODE 2
407#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
408#define CAUSEB_IP 8
409#define CAUSEF_IP (_ULCAST_(255) << 8)
410#define CAUSEB_IP0 8
411#define CAUSEF_IP0 (_ULCAST_(1) << 8)
412#define CAUSEB_IP1 9
413#define CAUSEF_IP1 (_ULCAST_(1) << 9)
414#define CAUSEB_IP2 10
415#define CAUSEF_IP2 (_ULCAST_(1) << 10)
416#define CAUSEB_IP3 11
417#define CAUSEF_IP3 (_ULCAST_(1) << 11)
418#define CAUSEB_IP4 12
419#define CAUSEF_IP4 (_ULCAST_(1) << 12)
420#define CAUSEB_IP5 13
421#define CAUSEF_IP5 (_ULCAST_(1) << 13)
422#define CAUSEB_IP6 14
423#define CAUSEF_IP6 (_ULCAST_(1) << 14)
424#define CAUSEB_IP7 15
425#define CAUSEF_IP7 (_ULCAST_(1) << 15)
426#define CAUSEB_FDCI 21
427#define CAUSEF_FDCI (_ULCAST_(1) << 21)
428#define CAUSEB_WP 22
429#define CAUSEF_WP (_ULCAST_(1) << 22)
430#define CAUSEB_IV 23
431#define CAUSEF_IV (_ULCAST_(1) << 23)
432#define CAUSEB_PCI 26
433#define CAUSEF_PCI (_ULCAST_(1) << 26)
434#define CAUSEB_DC 27
435#define CAUSEF_DC (_ULCAST_(1) << 27)
436#define CAUSEB_CE 28
437#define CAUSEF_CE (_ULCAST_(3) << 28)
438#define CAUSEB_TI 30
439#define CAUSEF_TI (_ULCAST_(1) << 30)
440#define CAUSEB_BD 31
441#define CAUSEF_BD (_ULCAST_(1) << 31)
442
443
444
445
446#define EXCCODE_INT 0
447#define EXCCODE_MOD 1
448#define EXCCODE_TLBL 2
449#define EXCCODE_TLBS 3
450#define EXCCODE_ADEL 4
451#define EXCCODE_ADES 5
452#define EXCCODE_IBE 6
453#define EXCCODE_DBE 7
454#define EXCCODE_SYS 8
455#define EXCCODE_BP 9
456#define EXCCODE_RI 10
457#define EXCCODE_CPU 11
458#define EXCCODE_OV 12
459#define EXCCODE_TR 13
460#define EXCCODE_MSAFPE 14
461#define EXCCODE_FPE 15
462#define EXCCODE_TLBRI 19
463#define EXCCODE_TLBXI 20
464#define EXCCODE_MSADIS 21
465#define EXCCODE_MDMX 22
466#define EXCCODE_WATCH 23
467#define EXCCODE_MCHECK 24
468#define EXCCODE_THREAD 25
469#define EXCCODE_DSPDIS 26
470#define EXCCODE_GE 27
471
472
473#define MIPS_EXCCODE_TLBPAR 16
474
475
476
477
478
479#define CONF_CM_CACHABLE_NO_WA 0
480#define CONF_CM_CACHABLE_WA 1
481#define CONF_CM_UNCACHED 2
482#define CONF_CM_CACHABLE_NONCOHERENT 3
483#define CONF_CM_CACHABLE_CE 4
484#define CONF_CM_CACHABLE_COW 5
485#define CONF_CM_CACHABLE_CUW 6
486#define CONF_CM_CACHABLE_ACCELERATED 7
487#define CONF_CM_CMASK 7
488#define CONF_BE (_ULCAST_(1) << 15)
489
490
491#define CONF_CU (_ULCAST_(1) << 3)
492#define CONF_DB (_ULCAST_(1) << 4)
493#define CONF_IB (_ULCAST_(1) << 5)
494#define CONF_DC (_ULCAST_(7) << 6)
495#define CONF_IC (_ULCAST_(7) << 9)
496#define CONF_EB (_ULCAST_(1) << 13)
497#define CONF_EM (_ULCAST_(1) << 14)
498#define CONF_SM (_ULCAST_(1) << 16)
499#define CONF_SC (_ULCAST_(1) << 17)
500#define CONF_EW (_ULCAST_(3) << 18)
501#define CONF_EP (_ULCAST_(15)<< 24)
502#define CONF_EC (_ULCAST_(7) << 28)
503#define CONF_CM (_ULCAST_(1) << 31)
504
505
506#define R4K_CONF_SW (_ULCAST_(1) << 20)
507#define R4K_CONF_SS (_ULCAST_(1) << 21)
508#define R4K_CONF_SB (_ULCAST_(3) << 22)
509
510
511#define R5K_CONF_SE (_ULCAST_(1) << 12)
512#define R5K_CONF_SS (_ULCAST_(3) << 20)
513
514
515#define RM7K_CONF_SE (_ULCAST_(1) << 3)
516#define RM7K_CONF_TE (_ULCAST_(1) << 12)
517#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
518#define RM7K_CONF_TC (_ULCAST_(1) << 17)
519#define RM7K_CONF_SI (_ULCAST_(3) << 20)
520#define RM7K_CONF_SC (_ULCAST_(1) << 31)
521
522
523#define R10K_CONF_DN (_ULCAST_(3) << 3)
524#define R10K_CONF_CT (_ULCAST_(1) << 5)
525#define R10K_CONF_PE (_ULCAST_(1) << 6)
526#define R10K_CONF_PM (_ULCAST_(3) << 7)
527#define R10K_CONF_EC (_ULCAST_(15)<< 9)
528#define R10K_CONF_SB (_ULCAST_(1) << 13)
529#define R10K_CONF_SK (_ULCAST_(1) << 14)
530#define R10K_CONF_SS (_ULCAST_(7) << 16)
531#define R10K_CONF_SC (_ULCAST_(7) << 19)
532#define R10K_CONF_DC (_ULCAST_(7) << 26)
533#define R10K_CONF_IC (_ULCAST_(7) << 29)
534
535
536#define VR41_CONF_CS (_ULCAST_(1) << 12)
537#define VR41_CONF_P4K (_ULCAST_(1) << 13)
538#define VR41_CONF_BP (_ULCAST_(1) << 16)
539#define VR41_CONF_M16 (_ULCAST_(1) << 20)
540#define VR41_CONF_AD (_ULCAST_(1) << 23)
541
542
543#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
544#define R30XX_CONF_REV (_ULCAST_(1) << 22)
545#define R30XX_CONF_AC (_ULCAST_(1) << 23)
546#define R30XX_CONF_RF (_ULCAST_(1) << 24)
547#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
548#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
549#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
550#define R30XX_CONF_SB (_ULCAST_(1) << 30)
551#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
552
553
554#define TX49_CONF_DC (_ULCAST_(1) << 16)
555#define TX49_CONF_IC (_ULCAST_(1) << 17)
556#define TX49_CONF_HALT (_ULCAST_(1) << 18)
557#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
558
559
560#define MIPS_CONF_VI (_ULCAST_(1) << 3)
561#define MIPS_CONF_MT (_ULCAST_(7) << 7)
562#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
563#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
564#define MIPS_CONF_AR (_ULCAST_(7) << 10)
565#define MIPS_CONF_AT (_ULCAST_(3) << 13)
566#define MIPS_CONF_M (_ULCAST_(1) << 31)
567
568
569
570
571#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
572#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
573#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
574#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
575#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
576#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
577#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
578#define MIPS_CONF1_DA_SHF 7
579#define MIPS_CONF1_DA_SZ 3
580#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
581#define MIPS_CONF1_DL_SHF 10
582#define MIPS_CONF1_DL_SZ 3
583#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
584#define MIPS_CONF1_DS_SHF 13
585#define MIPS_CONF1_DS_SZ 3
586#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
587#define MIPS_CONF1_IA_SHF 16
588#define MIPS_CONF1_IA_SZ 3
589#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
590#define MIPS_CONF1_IL_SHF 19
591#define MIPS_CONF1_IL_SZ 3
592#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
593#define MIPS_CONF1_IS_SHF 22
594#define MIPS_CONF1_IS_SZ 3
595#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
596#define MIPS_CONF1_TLBS_SHIFT (25)
597#define MIPS_CONF1_TLBS_SIZE (6)
598#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
599
600#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
601#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
602#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
603#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
604#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
605#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
606#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
607#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
608
609#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
610#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
611#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
612#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
613#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
614#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
615#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
616#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
617#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
618#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
619#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
620#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
621#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
622#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
623#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
624#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
625#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
626#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
627#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
628#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
629#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
630#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
631#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
632#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
633#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
634#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
635#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
636
637#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
638#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
639#define MIPS_CONF4_FTLBSETS_SHIFT (0)
640#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
641#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
642#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
643#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
644
645#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
646
647#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
648#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
649#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
650#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
651#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
652#define MIPS_CONF4_KSCREXIST_SHIFT (16)
653#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
654#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
655#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
656#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
657#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
658#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
659
660#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
661#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
662#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
663#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
664#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
665#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
666#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
667#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
668#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
669#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
670#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
671#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
672#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
673#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
674#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
675#define MIPS_CONF5_K (_ULCAST_(1) << 30)
676
677#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
678
679#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
680
681#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
682
683#define MIPS_CONF6_FTLBP_SHIFT (16)
684
685#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
686
687#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
688
689#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
690#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
691
692
693
694
695#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
696
697
698#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
699
700
701#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
702#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
703#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
704#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
705#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
706#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
707#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
708#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
709#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
710#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
711#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
712#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
713#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
714
715
716#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
717#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
718#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
719#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
720#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
721#define MIPS_PERFCTRL_EVENT_S 5
722#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
723#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
724#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
725#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
726#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
727#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
728#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
729#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
730#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
731
732
733#define MIPS_PERFCTRL_VPEID_S 16
734#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
735#define MIPS_PERFCTRL_TCID_S 22
736#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
737#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
738#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
739#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
740#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
741
742
743#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
744
745
746#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
747
748
749#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
750#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
751#define MIPS_MAAR_ADDR_SHIFT 12
752#define MIPS_MAAR_S (_ULCAST_(1) << 1)
753#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
754
755
756#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
757
758
759#define MIPS_EBASE_CPUNUM_SHIFT 0
760#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
761#define MIPS_EBASE_WG_SHIFT 11
762#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
763#define MIPS_EBASE_BASE_SHIFT 12
764#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
765
766
767#define MIPS_CMGCRB_BASE 11
768#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
769
770
771#define MIPS_LLADDR_LLB_SHIFT 0
772#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
773
774
775
776
777#define MIPS_SEGCFG_PA_SHIFT 9
778#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
779#define MIPS_SEGCFG_AM_SHIFT 4
780#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
781#define MIPS_SEGCFG_EU_SHIFT 3
782#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
783#define MIPS_SEGCFG_C_SHIFT 0
784#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
785
786#define MIPS_SEGCFG_UUSK _ULCAST_(7)
787#define MIPS_SEGCFG_USK _ULCAST_(5)
788#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
789#define MIPS_SEGCFG_MUSK _ULCAST_(3)
790#define MIPS_SEGCFG_MSK _ULCAST_(2)
791#define MIPS_SEGCFG_MK _ULCAST_(1)
792#define MIPS_SEGCFG_UK _ULCAST_(0)
793
794#define MIPS_PWFIELD_GDI_SHIFT 24
795#define MIPS_PWFIELD_GDI_MASK 0x3f000000
796#define MIPS_PWFIELD_UDI_SHIFT 18
797#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
798#define MIPS_PWFIELD_MDI_SHIFT 12
799#define MIPS_PWFIELD_MDI_MASK 0x0003f000
800#define MIPS_PWFIELD_PTI_SHIFT 6
801#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
802#define MIPS_PWFIELD_PTEI_SHIFT 0
803#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
804
805#define MIPS_PWSIZE_PS_SHIFT 30
806#define MIPS_PWSIZE_PS_MASK 0x40000000
807#define MIPS_PWSIZE_GDW_SHIFT 24
808#define MIPS_PWSIZE_GDW_MASK 0x3f000000
809#define MIPS_PWSIZE_UDW_SHIFT 18
810#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
811#define MIPS_PWSIZE_MDW_SHIFT 12
812#define MIPS_PWSIZE_MDW_MASK 0x0003f000
813#define MIPS_PWSIZE_PTW_SHIFT 6
814#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
815#define MIPS_PWSIZE_PTEW_SHIFT 0
816#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
817
818#define MIPS_PWCTL_PWEN_SHIFT 31
819#define MIPS_PWCTL_PWEN_MASK 0x80000000
820#define MIPS_PWCTL_XK_SHIFT 28
821#define MIPS_PWCTL_XK_MASK 0x10000000
822#define MIPS_PWCTL_XS_SHIFT 27
823#define MIPS_PWCTL_XS_MASK 0x08000000
824#define MIPS_PWCTL_XU_SHIFT 26
825#define MIPS_PWCTL_XU_MASK 0x04000000
826#define MIPS_PWCTL_DPH_SHIFT 7
827#define MIPS_PWCTL_DPH_MASK 0x00000080
828#define MIPS_PWCTL_HUGEPG_SHIFT 6
829#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
830#define MIPS_PWCTL_PSN_SHIFT 0
831#define MIPS_PWCTL_PSN_MASK 0x0000003f
832
833
834#define MIPS_GCTL0_GM_SHIFT 31
835#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
836#define MIPS_GCTL0_RI_SHIFT 30
837#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
838#define MIPS_GCTL0_MC_SHIFT 29
839#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
840#define MIPS_GCTL0_CP0_SHIFT 28
841#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
842#define MIPS_GCTL0_AT_SHIFT 26
843#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
844#define MIPS_GCTL0_GT_SHIFT 25
845#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
846#define MIPS_GCTL0_CG_SHIFT 24
847#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
848#define MIPS_GCTL0_CF_SHIFT 23
849#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
850#define MIPS_GCTL0_G1_SHIFT 22
851#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
852#define MIPS_GCTL0_G0E_SHIFT 19
853#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
854#define MIPS_GCTL0_PT_SHIFT 18
855#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
856#define MIPS_GCTL0_RAD_SHIFT 9
857#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
858#define MIPS_GCTL0_DRG_SHIFT 8
859#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
860#define MIPS_GCTL0_G2_SHIFT 7
861#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
862#define MIPS_GCTL0_GEXC_SHIFT 2
863#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
864#define MIPS_GCTL0_SFC2_SHIFT 1
865#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
866#define MIPS_GCTL0_SFC1_SHIFT 0
867#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
868
869
870#define MIPS_GCTL0_AT_ROOT 1
871#define MIPS_GCTL0_AT_GUEST 3
872
873
874#define MIPS_GCTL0_GEXC_GPSI 0
875#define MIPS_GCTL0_GEXC_GSFC 1
876#define MIPS_GCTL0_GEXC_HC 2
877#define MIPS_GCTL0_GEXC_GRR 3
878#define MIPS_GCTL0_GEXC_GVA 8
879#define MIPS_GCTL0_GEXC_GHFC 9
880#define MIPS_GCTL0_GEXC_GPA 10
881
882
883#define MIPS_GCTL0EXT_RPW_SHIFT 8
884#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
885#define MIPS_GCTL0EXT_NCC_SHIFT 6
886#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
887#define MIPS_GCTL0EXT_CGI_SHIFT 4
888#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
889#define MIPS_GCTL0EXT_FCD_SHIFT 3
890#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
891#define MIPS_GCTL0EXT_OG_SHIFT 2
892#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
893#define MIPS_GCTL0EXT_BG_SHIFT 1
894#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
895#define MIPS_GCTL0EXT_MG_SHIFT 0
896#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
897
898
899#define MIPS_GCTL0EXT_RPW_BOTH 0
900#define MIPS_GCTL0EXT_RPW_GPA 2
901#define MIPS_GCTL0EXT_RPW_RVA 3
902
903
904#define MIPS_GCTL0EXT_NCC_IND 0
905#define MIPS_GCTL0EXT_NCC_MOD 1
906
907
908#define MIPS_GCTL1_ID_SHIFT 0
909#define MIPS_GCTL1_ID_WIDTH 8
910#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
911#define MIPS_GCTL1_RID_SHIFT 16
912#define MIPS_GCTL1_RID_WIDTH 8
913#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
914#define MIPS_GCTL1_EID_SHIFT 24
915#define MIPS_GCTL1_EID_WIDTH 8
916#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
917
918
919#define MIPS_GCTL1_ROOT_GUESTID 0
920
921
922#define MIPS_CDMMBASE_SIZE_SHIFT 0
923#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
924#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
925#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
926#define MIPS_CDMMBASE_ADDR_SHIFT 11
927#define MIPS_CDMMBASE_ADDR_START 15
928
929
930#define MIPS_HWR_CPUNUM 0
931#define MIPS_HWR_SYNCISTEP 1
932#define MIPS_HWR_CC 2
933#define MIPS_HWR_CCRES 3
934#define MIPS_HWR_ULR 29
935#define MIPS_HWR_IMPL1 30
936#define MIPS_HWR_IMPL2 31
937
938
939#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
940#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
941#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
942#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
943#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
944#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
945#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
946
947
948
949
950#define TX39_CONF_ICS_SHIFT 19
951#define TX39_CONF_ICS_MASK 0x00380000
952#define TX39_CONF_ICS_1KB 0x00000000
953#define TX39_CONF_ICS_2KB 0x00080000
954#define TX39_CONF_ICS_4KB 0x00100000
955#define TX39_CONF_ICS_8KB 0x00180000
956#define TX39_CONF_ICS_16KB 0x00200000
957
958#define TX39_CONF_DCS_SHIFT 16
959#define TX39_CONF_DCS_MASK 0x00070000
960#define TX39_CONF_DCS_1KB 0x00000000
961#define TX39_CONF_DCS_2KB 0x00010000
962#define TX39_CONF_DCS_4KB 0x00020000
963#define TX39_CONF_DCS_8KB 0x00030000
964#define TX39_CONF_DCS_16KB 0x00040000
965
966#define TX39_CONF_CWFON 0x00004000
967#define TX39_CONF_WBON 0x00002000
968#define TX39_CONF_RF_SHIFT 10
969#define TX39_CONF_RF_MASK 0x00000c00
970#define TX39_CONF_DOZE 0x00000200
971#define TX39_CONF_HALT 0x00000100
972#define TX39_CONF_LOCK 0x00000080
973#define TX39_CONF_ICE 0x00000020
974#define TX39_CONF_DCE 0x00000010
975#define TX39_CONF_IRSIZE_SHIFT 2
976#define TX39_CONF_IRSIZE_MASK 0x0000000c
977#define TX39_CONF_DRSIZE_SHIFT 0
978#define TX39_CONF_DRSIZE_MASK 0x00000003
979
980
981
982
983
984#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
985
986#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
987
988#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
989
990
991#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
992
993#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
994
995#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
996
997#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
998
999
1000#define CVMCTL_IPPCI_SHIFT 7
1001#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1002#define CVMCTL_IPTI_SHIFT 4
1003#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1004
1005
1006#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1007
1008
1009#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1010#define CVMVMCONF_MMUSIZEM1_S 12
1011#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1012#define CVMVMCONF_RMMUSIZEM1_S 0
1013#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1014
1015
1016
1017
1018#define CP1_REVISION $0
1019#define CP1_UFR $1
1020#define CP1_UNFR $4
1021#define CP1_FCCR $25
1022#define CP1_FEXR $26
1023#define CP1_FENR $28
1024#define CP1_STATUS $31
1025
1026
1027
1028
1029
1030#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1031#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1032#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1033#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1034#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1035#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1036#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1037#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1038#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1039#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1040
1041
1042
1043
1044#define MIPS_FCCR_CONDX_S 0
1045#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1046#define MIPS_FCCR_COND0_S 0
1047#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1048#define MIPS_FCCR_COND1_S 1
1049#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1050#define MIPS_FCCR_COND2_S 2
1051#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1052#define MIPS_FCCR_COND3_S 3
1053#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1054#define MIPS_FCCR_COND4_S 4
1055#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1056#define MIPS_FCCR_COND5_S 5
1057#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1058#define MIPS_FCCR_COND6_S 6
1059#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1060#define MIPS_FCCR_COND7_S 7
1061#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1062
1063
1064
1065
1066#define MIPS_FENR_FS_S 2
1067#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1068
1069
1070
1071
1072#define FPU_CSR_COND_S 23
1073#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1074
1075#define FPU_CSR_FS_S 24
1076#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1077
1078#define FPU_CSR_CONDX_S 25
1079#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1080#define FPU_CSR_COND1_S 25
1081#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1082#define FPU_CSR_COND2_S 26
1083#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1084#define FPU_CSR_COND3_S 27
1085#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1086#define FPU_CSR_COND4_S 28
1087#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1088#define FPU_CSR_COND5_S 29
1089#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1090#define FPU_CSR_COND6_S 30
1091#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1092#define FPU_CSR_COND7_S 31
1093#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1094
1095
1096
1097
1098
1099#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1100
1101#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1102#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1103
1104
1105
1106
1107
1108
1109#define FPU_CSR_ALL_X 0x0003f000
1110#define FPU_CSR_UNI_X 0x00020000
1111#define FPU_CSR_INV_X 0x00010000
1112#define FPU_CSR_DIV_X 0x00008000
1113#define FPU_CSR_OVF_X 0x00004000
1114#define FPU_CSR_UDF_X 0x00002000
1115#define FPU_CSR_INE_X 0x00001000
1116
1117#define FPU_CSR_ALL_E 0x00000f80
1118#define FPU_CSR_INV_E 0x00000800
1119#define FPU_CSR_DIV_E 0x00000400
1120#define FPU_CSR_OVF_E 0x00000200
1121#define FPU_CSR_UDF_E 0x00000100
1122#define FPU_CSR_INE_E 0x00000080
1123
1124#define FPU_CSR_ALL_S 0x0000007c
1125#define FPU_CSR_INV_S 0x00000040
1126#define FPU_CSR_DIV_S 0x00000020
1127#define FPU_CSR_OVF_S 0x00000010
1128#define FPU_CSR_UDF_S 0x00000008
1129#define FPU_CSR_INE_S 0x00000004
1130
1131
1132#define FPU_CSR_RM 0x00000003
1133#define FPU_CSR_RN 0x0
1134#define FPU_CSR_RZ 0x1
1135#define FPU_CSR_RU 0x2
1136#define FPU_CSR_RD 0x3
1137
1138
1139#ifndef __ASSEMBLY__
1140
1141
1142
1143
1144#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1145 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1146#define get_isa16_mode(x) ((x) & 0x1)
1147#define msk_isa16_mode(x) ((x) & ~0x1)
1148#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1149#else
1150#define get_isa16_mode(x) 0
1151#define msk_isa16_mode(x) (x)
1152#define set_isa16_mode(x) do { } while(0)
1153#endif
1154
1155
1156
1157
1158
1159static inline int mm_insn_16bit(u16 insn)
1160{
1161 u16 opcode = (insn >> 10) & 0x7;
1162
1163 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1164}
1165
1166
1167
1168
1169#ifdef CONFIG_CPU_MICROMIPS
1170#define _ASM_INSN16_IF_MM(_enc) \
1171 ".insn\n\t" \
1172 ".hword (" #_enc ")\n\t"
1173#define _ASM_INSN32_IF_MM(_enc) \
1174 ".insn\n\t" \
1175 ".hword ((" #_enc ") >> 16)\n\t" \
1176 ".hword ((" #_enc ") & 0xffff)\n\t"
1177#else
1178#define _ASM_INSN_IF_MIPS(_enc) \
1179 ".insn\n\t" \
1180 ".word (" #_enc ")\n\t"
1181#endif
1182
1183#ifndef _ASM_INSN16_IF_MM
1184#define _ASM_INSN16_IF_MM(_enc)
1185#endif
1186#ifndef _ASM_INSN32_IF_MM
1187#define _ASM_INSN32_IF_MM(_enc)
1188#endif
1189#ifndef _ASM_INSN_IF_MIPS
1190#define _ASM_INSN_IF_MIPS(_enc)
1191#endif
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215#define _IFC_REG(n) \
1216 ".ifc \\r, $" #n "\n\t" \
1217 "\\var = " #n "\n\t" \
1218 ".endif\n\t"
1219
1220__asm__(".macro parse_r var r\n\t"
1221 "\\var = -1\n\t"
1222 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1223 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1224 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1225 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1226 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1227 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1228 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1229 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1230 ".iflt \\var\n\t"
1231 ".error \"Unable to parse register name \\r\"\n\t"
1232 ".endif\n\t"
1233 ".endm");
1234
1235#undef _IFC_REG
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246#define _ASM_MACRO_0(OP, ENC) \
1247 __asm__(".macro " #OP "\n\t" \
1248 ENC \
1249 ".endm")
1250
1251
1252#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1253 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1254 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1255 ENC \
1256 ".endm")
1257
1258
1259#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1260 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1261 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1262 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1263 ENC \
1264 ".endm")
1265
1266
1267#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1268 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1269 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1270 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1271 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1272 ENC \
1273 ".endm")
1274
1275
1276#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1277 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1278 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1279 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1280 ENC \
1281 ".endm")
1282
1283
1284
1285
1286static inline void tlbinvf(void)
1287{
1288 __asm__ __volatile__(
1289 ".set push\n\t"
1290 ".set noreorder\n\t"
1291 "# tlbinvf\n\t"
1292 _ASM_INSN_IF_MIPS(0x42000004)
1293 _ASM_INSN32_IF_MM(0x0000537c)
1294 ".set pop");
1295}
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305#define read_r10k_perf_cntr(counter) \
1306({ \
1307 unsigned int __res; \
1308 __asm__ __volatile__( \
1309 "mfpc\t%0, %1" \
1310 : "=r" (__res) \
1311 : "i" (counter)); \
1312 \
1313 __res; \
1314})
1315
1316#define write_r10k_perf_cntr(counter,val) \
1317do { \
1318 __asm__ __volatile__( \
1319 "mtpc\t%0, %1" \
1320 : \
1321 : "r" (val), "i" (counter)); \
1322} while (0)
1323
1324#define read_r10k_perf_event(counter) \
1325({ \
1326 unsigned int __res; \
1327 __asm__ __volatile__( \
1328 "mfps\t%0, %1" \
1329 : "=r" (__res) \
1330 : "i" (counter)); \
1331 \
1332 __res; \
1333})
1334
1335#define write_r10k_perf_cntl(counter,val) \
1336do { \
1337 __asm__ __volatile__( \
1338 "mtps\t%0, %1" \
1339 : \
1340 : "r" (val), "i" (counter)); \
1341} while (0)
1342
1343
1344
1345
1346
1347
1348#define ___read_32bit_c0_register(source, sel, vol) \
1349({ unsigned int __res; \
1350 if (sel == 0) \
1351 __asm__ vol( \
1352 "mfc0\t%0, " #source "\n\t" \
1353 : "=r" (__res)); \
1354 else \
1355 __asm__ vol( \
1356 ".set\tpush\n\t" \
1357 ".set\tmips32\n\t" \
1358 "mfc0\t%0, " #source ", " #sel "\n\t" \
1359 ".set\tpop\n\t" \
1360 : "=r" (__res)); \
1361 __res; \
1362})
1363
1364#define ___read_64bit_c0_register(source, sel, vol) \
1365({ unsigned long long __res; \
1366 if (sizeof(unsigned long) == 4) \
1367 __res = __read_64bit_c0_split(source, sel, vol); \
1368 else if (sel == 0) \
1369 __asm__ vol( \
1370 ".set\tpush\n\t" \
1371 ".set\tmips3\n\t" \
1372 "dmfc0\t%0, " #source "\n\t" \
1373 ".set\tpop" \
1374 : "=r" (__res)); \
1375 else \
1376 __asm__ vol( \
1377 ".set\tpush\n\t" \
1378 ".set\tmips64\n\t" \
1379 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1380 ".set\tpop" \
1381 : "=r" (__res)); \
1382 __res; \
1383})
1384
1385#define __read_32bit_c0_register(source, sel) \
1386 ___read_32bit_c0_register(source, sel, __volatile__)
1387
1388#define __read_const_32bit_c0_register(source, sel) \
1389 ___read_32bit_c0_register(source, sel,)
1390
1391#define __read_64bit_c0_register(source, sel) \
1392 ___read_64bit_c0_register(source, sel, __volatile__)
1393
1394#define __read_const_64bit_c0_register(source, sel) \
1395 ___read_64bit_c0_register(source, sel,)
1396
1397#define __write_32bit_c0_register(register, sel, value) \
1398do { \
1399 if (sel == 0) \
1400 __asm__ __volatile__( \
1401 "mtc0\t%z0, " #register "\n\t" \
1402 : : "Jr" ((unsigned int)(value))); \
1403 else \
1404 __asm__ __volatile__( \
1405 ".set\tpush\n\t" \
1406 ".set\tmips32\n\t" \
1407 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1408 ".set\tpop" \
1409 : : "Jr" ((unsigned int)(value))); \
1410} while (0)
1411
1412#define __write_64bit_c0_register(register, sel, value) \
1413do { \
1414 if (sizeof(unsigned long) == 4) \
1415 __write_64bit_c0_split(register, sel, value); \
1416 else if (sel == 0) \
1417 __asm__ __volatile__( \
1418 ".set\tpush\n\t" \
1419 ".set\tmips3\n\t" \
1420 "dmtc0\t%z0, " #register "\n\t" \
1421 ".set\tpop" \
1422 : : "Jr" (value)); \
1423 else \
1424 __asm__ __volatile__( \
1425 ".set\tpush\n\t" \
1426 ".set\tmips64\n\t" \
1427 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1428 ".set\tpop" \
1429 : : "Jr" (value)); \
1430} while (0)
1431
1432#define __read_ulong_c0_register(reg, sel) \
1433 ((sizeof(unsigned long) == 4) ? \
1434 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1435 (unsigned long) __read_64bit_c0_register(reg, sel))
1436
1437#define __read_const_ulong_c0_register(reg, sel) \
1438 ((sizeof(unsigned long) == 4) ? \
1439 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1440 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1441
1442#define __write_ulong_c0_register(reg, sel, val) \
1443do { \
1444 if (sizeof(unsigned long) == 4) \
1445 __write_32bit_c0_register(reg, sel, val); \
1446 else \
1447 __write_64bit_c0_register(reg, sel, val); \
1448} while (0)
1449
1450
1451
1452
1453#define __read_32bit_c0_ctrl_register(source) \
1454({ unsigned int __res; \
1455 __asm__ __volatile__( \
1456 "cfc0\t%0, " #source "\n\t" \
1457 : "=r" (__res)); \
1458 __res; \
1459})
1460
1461#define __write_32bit_c0_ctrl_register(register, value) \
1462do { \
1463 __asm__ __volatile__( \
1464 "ctc0\t%z0, " #register "\n\t" \
1465 : : "Jr" ((unsigned int)(value))); \
1466} while (0)
1467
1468
1469
1470
1471
1472#define __read_64bit_c0_split(source, sel, vol) \
1473({ \
1474 unsigned long long __val; \
1475 unsigned long __flags; \
1476 \
1477 local_irq_save(__flags); \
1478 if (sel == 0) \
1479 __asm__ vol( \
1480 ".set\tpush\n\t" \
1481 ".set\tmips64\n\t" \
1482 "dmfc0\t%L0, " #source "\n\t" \
1483 "dsra\t%M0, %L0, 32\n\t" \
1484 "sll\t%L0, %L0, 0\n\t" \
1485 ".set\tpop" \
1486 : "=r" (__val)); \
1487 else \
1488 __asm__ vol( \
1489 ".set\tpush\n\t" \
1490 ".set\tmips64\n\t" \
1491 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1492 "dsra\t%M0, %L0, 32\n\t" \
1493 "sll\t%L0, %L0, 0\n\t" \
1494 ".set\tpop" \
1495 : "=r" (__val)); \
1496 local_irq_restore(__flags); \
1497 \
1498 __val; \
1499})
1500
1501#define __write_64bit_c0_split(source, sel, val) \
1502do { \
1503 unsigned long long __tmp = (val); \
1504 unsigned long __flags; \
1505 \
1506 local_irq_save(__flags); \
1507 if (MIPS_ISA_REV >= 2) \
1508 __asm__ __volatile__( \
1509 ".set\tpush\n\t" \
1510 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1511 "dins\t%L0, %M0, 32, 32\n\t" \
1512 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1513 ".set\tpop" \
1514 : "+r" (__tmp)); \
1515 else if (sel == 0) \
1516 __asm__ __volatile__( \
1517 ".set\tpush\n\t" \
1518 ".set\tmips64\n\t" \
1519 "dsll\t%L0, %L0, 32\n\t" \
1520 "dsrl\t%L0, %L0, 32\n\t" \
1521 "dsll\t%M0, %M0, 32\n\t" \
1522 "or\t%L0, %L0, %M0\n\t" \
1523 "dmtc0\t%L0, " #source "\n\t" \
1524 ".set\tpop" \
1525 : "+r" (__tmp)); \
1526 else \
1527 __asm__ __volatile__( \
1528 ".set\tpush\n\t" \
1529 ".set\tmips64\n\t" \
1530 "dsll\t%L0, %L0, 32\n\t" \
1531 "dsrl\t%L0, %L0, 32\n\t" \
1532 "dsll\t%M0, %M0, 32\n\t" \
1533 "or\t%L0, %L0, %M0\n\t" \
1534 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1535 ".set\tpop" \
1536 : "+r" (__tmp)); \
1537 local_irq_restore(__flags); \
1538} while (0)
1539
1540#ifndef TOOLCHAIN_SUPPORTS_XPA
1541_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1542 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1543 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1544_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1545 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1546 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1547#define _ASM_SET_XPA ""
1548#else
1549#define _ASM_SET_XPA ".set\txpa\n\t"
1550#endif
1551
1552#define __readx_32bit_c0_register(source, sel) \
1553({ \
1554 unsigned int __res; \
1555 \
1556 __asm__ __volatile__( \
1557 " .set push \n" \
1558 " .set mips32r2 \n" \
1559 _ASM_SET_XPA \
1560 " mfhc0 %0, " #source ", %1 \n" \
1561 " .set pop \n" \
1562 : "=r" (__res) \
1563 : "i" (sel)); \
1564 __res; \
1565})
1566
1567#define __writex_32bit_c0_register(register, sel, value) \
1568do { \
1569 __asm__ __volatile__( \
1570 " .set push \n" \
1571 " .set mips32r2 \n" \
1572 _ASM_SET_XPA \
1573 " mthc0 %z0, " #register ", %1 \n" \
1574 " .set pop \n" \
1575 : \
1576 : "Jr" (value), "i" (sel)); \
1577} while (0)
1578
1579#define read_c0_index() __read_32bit_c0_register($0, 0)
1580#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1581
1582#define read_c0_random() __read_32bit_c0_register($1, 0)
1583#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1584
1585#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1586#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1587
1588#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1589#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1590
1591#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1592#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1593
1594#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1595#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1596
1597#define read_c0_conf() __read_32bit_c0_register($3, 0)
1598#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1599
1600#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1601
1602#define read_c0_context() __read_ulong_c0_register($4, 0)
1603#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1604
1605#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1606#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1607
1608#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1609#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1610
1611#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1612#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1613
1614#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1615#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1616
1617#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1618#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1619
1620#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1621#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1622
1623#define read_c0_wired() __read_32bit_c0_register($6, 0)
1624#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1625
1626#define read_c0_info() __read_32bit_c0_register($7, 0)
1627
1628#define read_c0_cache() __read_32bit_c0_register($7, 0)
1629#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1630
1631#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1632#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1633
1634#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1635#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1636
1637#define read_c0_count() __read_32bit_c0_register($9, 0)
1638#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1639
1640#define read_c0_count2() __read_32bit_c0_register($9, 6)
1641#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1642
1643#define read_c0_count3() __read_32bit_c0_register($9, 7)
1644#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1645
1646#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1647#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1648
1649#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1650#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1651
1652#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1653#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1654
1655#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1656#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1657
1658#define read_c0_compare() __read_32bit_c0_register($11, 0)
1659#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1660
1661#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1662#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1663
1664#define read_c0_compare2() __read_32bit_c0_register($11, 6)
1665#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1666
1667#define read_c0_compare3() __read_32bit_c0_register($11, 7)
1668#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1669
1670#define read_c0_status() __read_32bit_c0_register($12, 0)
1671
1672#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1673
1674#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1675#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1676
1677#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1678#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1679
1680#define read_c0_cause() __read_32bit_c0_register($13, 0)
1681#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1682
1683#define read_c0_epc() __read_ulong_c0_register($14, 0)
1684#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1685
1686#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1687
1688#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1689
1690#define read_c0_config() __read_32bit_c0_register($16, 0)
1691#define read_c0_config1() __read_32bit_c0_register($16, 1)
1692#define read_c0_config2() __read_32bit_c0_register($16, 2)
1693#define read_c0_config3() __read_32bit_c0_register($16, 3)
1694#define read_c0_config4() __read_32bit_c0_register($16, 4)
1695#define read_c0_config5() __read_32bit_c0_register($16, 5)
1696#define read_c0_config6() __read_32bit_c0_register($16, 6)
1697#define read_c0_config7() __read_32bit_c0_register($16, 7)
1698#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1699#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1700#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1701#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1702#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1703#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1704#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1705#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1706
1707#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1708#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1709#define read_c0_maar() __read_ulong_c0_register($17, 1)
1710#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1711#define read_c0_maari() __read_32bit_c0_register($17, 2)
1712#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1713
1714
1715
1716
1717#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1718#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1719#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1720#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1721#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1722#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1723#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1724#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1725#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1726#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1727#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1728#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1729#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1730#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1731#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1732#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1733
1734
1735
1736
1737#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1738#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1739#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1740#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1741#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1742#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1743#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1744#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1745
1746#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1747#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1748#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1749#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1750#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1751#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1752#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1753#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1754
1755#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1756#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1757
1758#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1759#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1760
1761#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1762#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1763
1764#define read_c0_diag() __read_32bit_c0_register($22, 0)
1765#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1766
1767
1768#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1769#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1770
1771#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1772#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1773
1774#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1775#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1776
1777#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1778#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1779
1780#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1781#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1782
1783#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1784#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1785
1786#define read_c0_debug() __read_32bit_c0_register($23, 0)
1787#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1788
1789#define read_c0_depc() __read_ulong_c0_register($24, 0)
1790#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1791
1792
1793
1794
1795#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1796#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1797#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1798#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1799#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1800#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1801#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1802#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1803#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1804#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1805#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1806#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1807#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1808#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1809#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1810#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1811#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1812#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1813#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1814#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1815#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1816#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1817#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1818#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1819
1820#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1821#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1822
1823#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1824#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1825
1826#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1827
1828#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1829#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1830
1831#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1832#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1833
1834#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1835#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1836
1837#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1838#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1839
1840#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1841#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1842
1843#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1844#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1845
1846#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1847#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1848
1849
1850#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1851#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1852
1853#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1854#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1855
1856#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1857#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1858
1859#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1860#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1861
1862#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1863#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1864
1865#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1866#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1867
1868#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1869#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1870
1871
1872#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1873#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1874
1875#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1876#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1877
1878#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1879#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1880
1881
1882#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1883#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1884
1885#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1886#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1887
1888#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1889#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1890
1891#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1892#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1893
1894#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1895#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1896
1897#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1898#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1899
1900
1901#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1902#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1903
1904#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1905#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1906
1907#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1908#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1909
1910#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1911#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1912
1913#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1914#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1915
1916
1917
1918
1919
1920#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1921#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1922
1923#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1924#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1925
1926
1927#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1928#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1929
1930#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1931#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1932
1933#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1934#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1935
1936
1937#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1938#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1939
1940#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1941#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1942
1943#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1944#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1945
1946#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1947#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1948
1949#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1950#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1951
1952
1953#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1954#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1955
1956#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1957#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1958
1959#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1960#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1961
1962#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1963#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1964
1965#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1966#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1967
1968#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1969#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1970
1971
1972
1973
1974
1975#ifndef TOOLCHAIN_SUPPORTS_VIRT
1976_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1977 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1978 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1979_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1980 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1981 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1982_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1983 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1984 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1985_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1986 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1987 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1988_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
1989 _ASM_INSN32_IF_MM(0x0000017c));
1990_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
1991 _ASM_INSN32_IF_MM(0x0000117c));
1992_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
1993 _ASM_INSN32_IF_MM(0x0000217c));
1994_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
1995 _ASM_INSN32_IF_MM(0x0000317c));
1996_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1997 _ASM_INSN32_IF_MM(0x0000517c));
1998#define _ASM_SET_VIRT ""
1999#else
2000#define _ASM_SET_VIRT ".set\tvirt\n\t"
2001#endif
2002
2003#define __read_32bit_gc0_register(source, sel) \
2004({ int __res; \
2005 __asm__ __volatile__( \
2006 ".set\tpush\n\t" \
2007 ".set\tmips32r2\n\t" \
2008 _ASM_SET_VIRT \
2009 "mfgc0\t%0, " #source ", %1\n\t" \
2010 ".set\tpop" \
2011 : "=r" (__res) \
2012 : "i" (sel)); \
2013 __res; \
2014})
2015
2016#define __read_64bit_gc0_register(source, sel) \
2017({ unsigned long long __res; \
2018 __asm__ __volatile__( \
2019 ".set\tpush\n\t" \
2020 ".set\tmips64r2\n\t" \
2021 _ASM_SET_VIRT \
2022 "dmfgc0\t%0, " #source ", %1\n\t" \
2023 ".set\tpop" \
2024 : "=r" (__res) \
2025 : "i" (sel)); \
2026 __res; \
2027})
2028
2029#define __write_32bit_gc0_register(register, sel, value) \
2030do { \
2031 __asm__ __volatile__( \
2032 ".set\tpush\n\t" \
2033 ".set\tmips32r2\n\t" \
2034 _ASM_SET_VIRT \
2035 "mtgc0\t%z0, " #register ", %1\n\t" \
2036 ".set\tpop" \
2037 : : "Jr" ((unsigned int)(value)), \
2038 "i" (sel)); \
2039} while (0)
2040
2041#define __write_64bit_gc0_register(register, sel, value) \
2042do { \
2043 __asm__ __volatile__( \
2044 ".set\tpush\n\t" \
2045 ".set\tmips64r2\n\t" \
2046 _ASM_SET_VIRT \
2047 "dmtgc0\t%z0, " #register ", %1\n\t" \
2048 ".set\tpop" \
2049 : : "Jr" (value), \
2050 "i" (sel)); \
2051} while (0)
2052
2053#define __read_ulong_gc0_register(reg, sel) \
2054 ((sizeof(unsigned long) == 4) ? \
2055 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2056 (unsigned long) __read_64bit_gc0_register(reg, sel))
2057
2058#define __write_ulong_gc0_register(reg, sel, val) \
2059do { \
2060 if (sizeof(unsigned long) == 4) \
2061 __write_32bit_gc0_register(reg, sel, val); \
2062 else \
2063 __write_64bit_gc0_register(reg, sel, val); \
2064} while (0)
2065
2066#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2067#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2068
2069#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2070#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2071
2072#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2073#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2074
2075#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2076#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2077
2078#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2079#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2080
2081#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2082#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2083
2084#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2085#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2086
2087#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2088#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2089
2090#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2091#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2092
2093#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2094#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2095
2096#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2097#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2098
2099#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2100#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2101
2102#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2103#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2104
2105#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2106#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2107
2108#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2109#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2110
2111#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2112#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2113
2114#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2115#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2116
2117#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2118#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2119
2120#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2121#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2122
2123#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2124#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2125
2126#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2127#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2128
2129#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2130
2131#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2132#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2133
2134#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2135#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2136
2137#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2138#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2139
2140#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2141#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2142
2143#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2144#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2145
2146#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2147#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2148
2149#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2150
2151#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2152#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2153
2154#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2155#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2156
2157#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2158#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2159#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2160#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2161#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2162#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2163#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2164#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2165#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2166#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2167#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2168#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2169#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2170#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2171#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2172#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2173
2174#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2175#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2176
2177#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2178#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2179#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2180#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2181#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2182#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2183#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2184#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2185#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2186#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2187#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2188#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2189#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2190#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2191#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2192#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2193
2194#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2195#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2196#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2197#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2198#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2199#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2200#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2201#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2202#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2203#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2204#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2205#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2206#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2207#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2208#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2209#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2210
2211#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2212#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2213
2214#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2215#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2216#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2217#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2218#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2219#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2220#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2221#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2222#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2223#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2224#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2225#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2226#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2227#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2228#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2229#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2230#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2231#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2232#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2233#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2234#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2235#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2236#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2237#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2238
2239#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2240#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2241
2242#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2243#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2244#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2245#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2246#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2247#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2248#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2249#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2250#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2251#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2252#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2253#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2254
2255
2256#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2257#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2258
2259#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2260#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2261
2262#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2263#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2264
2265#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2266#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2267
2268
2269
2270
2271#define _read_32bit_cp1_register(source, gas_hardfloat) \
2272({ \
2273 unsigned int __res; \
2274 \
2275 __asm__ __volatile__( \
2276 " .set push \n" \
2277 " .set reorder \n" \
2278 " # gas fails to assemble cfc1 for some archs, \n" \
2279 " # like Octeon. \n" \
2280 " .set mips1 \n" \
2281 " "STR(gas_hardfloat)" \n" \
2282 " cfc1 %0,"STR(source)" \n" \
2283 " .set pop \n" \
2284 : "=r" (__res)); \
2285 __res; \
2286})
2287
2288#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2289do { \
2290 __asm__ __volatile__( \
2291 " .set push \n" \
2292 " .set reorder \n" \
2293 " "STR(gas_hardfloat)" \n" \
2294 " ctc1 %0,"STR(dest)" \n" \
2295 " .set pop \n" \
2296 : : "r" (val)); \
2297} while (0)
2298
2299#ifdef GAS_HAS_SET_HARDFLOAT
2300#define read_32bit_cp1_register(source) \
2301 _read_32bit_cp1_register(source, .set hardfloat)
2302#define write_32bit_cp1_register(dest, val) \
2303 _write_32bit_cp1_register(dest, val, .set hardfloat)
2304#else
2305#define read_32bit_cp1_register(source) \
2306 _read_32bit_cp1_register(source, )
2307#define write_32bit_cp1_register(dest, val) \
2308 _write_32bit_cp1_register(dest, val, )
2309#endif
2310
2311#ifdef TOOLCHAIN_SUPPORTS_DSP
2312#define rddsp(mask) \
2313({ \
2314 unsigned int __dspctl; \
2315 \
2316 __asm__ __volatile__( \
2317 " .set push \n" \
2318 " .set " MIPS_ISA_LEVEL " \n" \
2319 " .set dsp \n" \
2320 " rddsp %0, %x1 \n" \
2321 " .set pop \n" \
2322 : "=r" (__dspctl) \
2323 : "i" (mask)); \
2324 __dspctl; \
2325})
2326
2327#define wrdsp(val, mask) \
2328do { \
2329 __asm__ __volatile__( \
2330 " .set push \n" \
2331 " .set " MIPS_ISA_LEVEL " \n" \
2332 " .set dsp \n" \
2333 " wrdsp %0, %x1 \n" \
2334 " .set pop \n" \
2335 : \
2336 : "r" (val), "i" (mask)); \
2337} while (0)
2338
2339#define mflo0() \
2340({ \
2341 long mflo0; \
2342 __asm__( \
2343 " .set push \n" \
2344 " .set " MIPS_ISA_LEVEL " \n" \
2345 " .set dsp \n" \
2346 " mflo %0, $ac0 \n" \
2347 " .set pop \n" \
2348 : "=r" (mflo0)); \
2349 mflo0; \
2350})
2351
2352#define mflo1() \
2353({ \
2354 long mflo1; \
2355 __asm__( \
2356 " .set push \n" \
2357 " .set " MIPS_ISA_LEVEL " \n" \
2358 " .set dsp \n" \
2359 " mflo %0, $ac1 \n" \
2360 " .set pop \n" \
2361 : "=r" (mflo1)); \
2362 mflo1; \
2363})
2364
2365#define mflo2() \
2366({ \
2367 long mflo2; \
2368 __asm__( \
2369 " .set push \n" \
2370 " .set " MIPS_ISA_LEVEL " \n" \
2371 " .set dsp \n" \
2372 " mflo %0, $ac2 \n" \
2373 " .set pop \n" \
2374 : "=r" (mflo2)); \
2375 mflo2; \
2376})
2377
2378#define mflo3() \
2379({ \
2380 long mflo3; \
2381 __asm__( \
2382 " .set push \n" \
2383 " .set " MIPS_ISA_LEVEL " \n" \
2384 " .set dsp \n" \
2385 " mflo %0, $ac3 \n" \
2386 " .set pop \n" \
2387 : "=r" (mflo3)); \
2388 mflo3; \
2389})
2390
2391#define mfhi0() \
2392({ \
2393 long mfhi0; \
2394 __asm__( \
2395 " .set push \n" \
2396 " .set " MIPS_ISA_LEVEL " \n" \
2397 " .set dsp \n" \
2398 " mfhi %0, $ac0 \n" \
2399 " .set pop \n" \
2400 : "=r" (mfhi0)); \
2401 mfhi0; \
2402})
2403
2404#define mfhi1() \
2405({ \
2406 long mfhi1; \
2407 __asm__( \
2408 " .set push \n" \
2409 " .set " MIPS_ISA_LEVEL " \n" \
2410 " .set dsp \n" \
2411 " mfhi %0, $ac1 \n" \
2412 " .set pop \n" \
2413 : "=r" (mfhi1)); \
2414 mfhi1; \
2415})
2416
2417#define mfhi2() \
2418({ \
2419 long mfhi2; \
2420 __asm__( \
2421 " .set push \n" \
2422 " .set " MIPS_ISA_LEVEL " \n" \
2423 " .set dsp \n" \
2424 " mfhi %0, $ac2 \n" \
2425 " .set pop \n" \
2426 : "=r" (mfhi2)); \
2427 mfhi2; \
2428})
2429
2430#define mfhi3() \
2431({ \
2432 long mfhi3; \
2433 __asm__( \
2434 " .set push \n" \
2435 " .set " MIPS_ISA_LEVEL " \n" \
2436 " .set dsp \n" \
2437 " mfhi %0, $ac3 \n" \
2438 " .set pop \n" \
2439 : "=r" (mfhi3)); \
2440 mfhi3; \
2441})
2442
2443
2444#define mtlo0(x) \
2445({ \
2446 __asm__( \
2447 " .set push \n" \
2448 " .set " MIPS_ISA_LEVEL " \n" \
2449 " .set dsp \n" \
2450 " mtlo %0, $ac0 \n" \
2451 " .set pop \n" \
2452 : \
2453 : "r" (x)); \
2454})
2455
2456#define mtlo1(x) \
2457({ \
2458 __asm__( \
2459 " .set push \n" \
2460 " .set " MIPS_ISA_LEVEL " \n" \
2461 " .set dsp \n" \
2462 " mtlo %0, $ac1 \n" \
2463 " .set pop \n" \
2464 : \
2465 : "r" (x)); \
2466})
2467
2468#define mtlo2(x) \
2469({ \
2470 __asm__( \
2471 " .set push \n" \
2472 " .set " MIPS_ISA_LEVEL " \n" \
2473 " .set dsp \n" \
2474 " mtlo %0, $ac2 \n" \
2475 " .set pop \n" \
2476 : \
2477 : "r" (x)); \
2478})
2479
2480#define mtlo3(x) \
2481({ \
2482 __asm__( \
2483 " .set push \n" \
2484 " .set " MIPS_ISA_LEVEL " \n" \
2485 " .set dsp \n" \
2486 " mtlo %0, $ac3 \n" \
2487 " .set pop \n" \
2488 : \
2489 : "r" (x)); \
2490})
2491
2492#define mthi0(x) \
2493({ \
2494 __asm__( \
2495 " .set push \n" \
2496 " .set " MIPS_ISA_LEVEL " \n" \
2497 " .set dsp \n" \
2498 " mthi %0, $ac0 \n" \
2499 " .set pop \n" \
2500 : \
2501 : "r" (x)); \
2502})
2503
2504#define mthi1(x) \
2505({ \
2506 __asm__( \
2507 " .set push \n" \
2508 " .set " MIPS_ISA_LEVEL " \n" \
2509 " .set dsp \n" \
2510 " mthi %0, $ac1 \n" \
2511 " .set pop \n" \
2512 : \
2513 : "r" (x)); \
2514})
2515
2516#define mthi2(x) \
2517({ \
2518 __asm__( \
2519 " .set push \n" \
2520 " .set " MIPS_ISA_LEVEL " \n" \
2521 " .set dsp \n" \
2522 " mthi %0, $ac2 \n" \
2523 " .set pop \n" \
2524 : \
2525 : "r" (x)); \
2526})
2527
2528#define mthi3(x) \
2529({ \
2530 __asm__( \
2531 " .set push \n" \
2532 " .set " MIPS_ISA_LEVEL " \n" \
2533 " .set dsp \n" \
2534 " mthi %0, $ac3 \n" \
2535 " .set pop \n" \
2536 : \
2537 : "r" (x)); \
2538})
2539
2540#else
2541
2542#define rddsp(mask) \
2543({ \
2544 unsigned int __res; \
2545 \
2546 __asm__ __volatile__( \
2547 " .set push \n" \
2548 " .set noat \n" \
2549 " # rddsp $1, %x1 \n" \
2550 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2551 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2552 " move %0, $1 \n" \
2553 " .set pop \n" \
2554 : "=r" (__res) \
2555 : "i" (mask)); \
2556 __res; \
2557})
2558
2559#define wrdsp(val, mask) \
2560do { \
2561 __asm__ __volatile__( \
2562 " .set push \n" \
2563 " .set noat \n" \
2564 " move $1, %0 \n" \
2565 " # wrdsp $1, %x1 \n" \
2566 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2567 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2568 " .set pop \n" \
2569 : \
2570 : "r" (val), "i" (mask)); \
2571} while (0)
2572
2573#define _dsp_mfxxx(ins) \
2574({ \
2575 unsigned long __treg; \
2576 \
2577 __asm__ __volatile__( \
2578 " .set push \n" \
2579 " .set noat \n" \
2580 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2581 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2582 " move %0, $1 \n" \
2583 " .set pop \n" \
2584 : "=r" (__treg) \
2585 : "i" (ins)); \
2586 __treg; \
2587})
2588
2589#define _dsp_mtxxx(val, ins) \
2590do { \
2591 __asm__ __volatile__( \
2592 " .set push \n" \
2593 " .set noat \n" \
2594 " move $1, %0 \n" \
2595 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2596 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2597 " .set pop \n" \
2598 : \
2599 : "r" (val), "i" (ins)); \
2600} while (0)
2601
2602#ifdef CONFIG_CPU_MICROMIPS
2603
2604#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2605#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2606
2607#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2608#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2609
2610#else
2611
2612#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2613#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2614
2615#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2616#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2617
2618#endif
2619
2620#define mflo0() _dsp_mflo(0)
2621#define mflo1() _dsp_mflo(1)
2622#define mflo2() _dsp_mflo(2)
2623#define mflo3() _dsp_mflo(3)
2624
2625#define mfhi0() _dsp_mfhi(0)
2626#define mfhi1() _dsp_mfhi(1)
2627#define mfhi2() _dsp_mfhi(2)
2628#define mfhi3() _dsp_mfhi(3)
2629
2630#define mtlo0(x) _dsp_mtlo(x, 0)
2631#define mtlo1(x) _dsp_mtlo(x, 1)
2632#define mtlo2(x) _dsp_mtlo(x, 2)
2633#define mtlo3(x) _dsp_mtlo(x, 3)
2634
2635#define mthi0(x) _dsp_mthi(x, 0)
2636#define mthi1(x) _dsp_mthi(x, 1)
2637#define mthi2(x) _dsp_mthi(x, 2)
2638#define mthi3(x) _dsp_mthi(x, 3)
2639
2640#endif
2641
2642
2643
2644
2645
2646
2647static inline void tlb_probe(void)
2648{
2649 __asm__ __volatile__(
2650 ".set noreorder\n\t"
2651 "tlbp\n\t"
2652 ".set reorder");
2653}
2654
2655static inline void tlb_read(void)
2656{
2657#if MIPS34K_MISSED_ITLB_WAR
2658 int res = 0;
2659
2660 __asm__ __volatile__(
2661 " .set push \n"
2662 " .set noreorder \n"
2663 " .set noat \n"
2664 " .set mips32r2 \n"
2665 " .word 0x41610001 # dvpe $1 \n"
2666 " move %0, $1 \n"
2667 " ehb \n"
2668 " .set pop \n"
2669 : "=r" (res));
2670
2671 instruction_hazard();
2672#endif
2673
2674 __asm__ __volatile__(
2675 ".set noreorder\n\t"
2676 "tlbr\n\t"
2677 ".set reorder");
2678
2679#if MIPS34K_MISSED_ITLB_WAR
2680 if ((res & _ULCAST_(1)))
2681 __asm__ __volatile__(
2682 " .set push \n"
2683 " .set noreorder \n"
2684 " .set noat \n"
2685 " .set mips32r2 \n"
2686 " .word 0x41600021 # evpe \n"
2687 " ehb \n"
2688 " .set pop \n");
2689#endif
2690}
2691
2692static inline void tlb_write_indexed(void)
2693{
2694 __asm__ __volatile__(
2695 ".set noreorder\n\t"
2696 "tlbwi\n\t"
2697 ".set reorder");
2698}
2699
2700static inline void tlb_write_random(void)
2701{
2702 __asm__ __volatile__(
2703 ".set noreorder\n\t"
2704 "tlbwr\n\t"
2705 ".set reorder");
2706}
2707
2708
2709
2710
2711
2712
2713static inline void guest_tlb_probe(void)
2714{
2715 __asm__ __volatile__(
2716 ".set push\n\t"
2717 ".set noreorder\n\t"
2718 _ASM_SET_VIRT
2719 "tlbgp\n\t"
2720 ".set pop");
2721}
2722
2723static inline void guest_tlb_read(void)
2724{
2725 __asm__ __volatile__(
2726 ".set push\n\t"
2727 ".set noreorder\n\t"
2728 _ASM_SET_VIRT
2729 "tlbgr\n\t"
2730 ".set pop");
2731}
2732
2733static inline void guest_tlb_write_indexed(void)
2734{
2735 __asm__ __volatile__(
2736 ".set push\n\t"
2737 ".set noreorder\n\t"
2738 _ASM_SET_VIRT
2739 "tlbgwi\n\t"
2740 ".set pop");
2741}
2742
2743static inline void guest_tlb_write_random(void)
2744{
2745 __asm__ __volatile__(
2746 ".set push\n\t"
2747 ".set noreorder\n\t"
2748 _ASM_SET_VIRT
2749 "tlbgwr\n\t"
2750 ".set pop");
2751}
2752
2753
2754
2755
2756static inline void guest_tlbinvf(void)
2757{
2758 __asm__ __volatile__(
2759 ".set push\n\t"
2760 ".set noreorder\n\t"
2761 _ASM_SET_VIRT
2762 "tlbginvf\n\t"
2763 ".set pop");
2764}
2765
2766
2767
2768
2769#define __BUILD_SET_COMMON(name) \
2770static inline unsigned int \
2771set_##name(unsigned int set) \
2772{ \
2773 unsigned int res, new; \
2774 \
2775 res = read_##name(); \
2776 new = res | set; \
2777 write_##name(new); \
2778 \
2779 return res; \
2780} \
2781 \
2782static inline unsigned int \
2783clear_##name(unsigned int clear) \
2784{ \
2785 unsigned int res, new; \
2786 \
2787 res = read_##name(); \
2788 new = res & ~clear; \
2789 write_##name(new); \
2790 \
2791 return res; \
2792} \
2793 \
2794static inline unsigned int \
2795change_##name(unsigned int change, unsigned int val) \
2796{ \
2797 unsigned int res, new; \
2798 \
2799 res = read_##name(); \
2800 new = res & ~change; \
2801 new |= (val & change); \
2802 write_##name(new); \
2803 \
2804 return res; \
2805}
2806
2807
2808
2809
2810#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2811
2812__BUILD_SET_C0(status)
2813__BUILD_SET_C0(cause)
2814__BUILD_SET_C0(config)
2815__BUILD_SET_C0(config5)
2816__BUILD_SET_C0(intcontrol)
2817__BUILD_SET_C0(intctl)
2818__BUILD_SET_C0(srsmap)
2819__BUILD_SET_C0(pagegrain)
2820__BUILD_SET_C0(guestctl0)
2821__BUILD_SET_C0(guestctl0ext)
2822__BUILD_SET_C0(guestctl1)
2823__BUILD_SET_C0(guestctl2)
2824__BUILD_SET_C0(guestctl3)
2825__BUILD_SET_C0(brcm_config_0)
2826__BUILD_SET_C0(brcm_bus_pll)
2827__BUILD_SET_C0(brcm_reset)
2828__BUILD_SET_C0(brcm_cmt_intr)
2829__BUILD_SET_C0(brcm_cmt_ctrl)
2830__BUILD_SET_C0(brcm_config)
2831__BUILD_SET_C0(brcm_mode)
2832
2833
2834
2835
2836#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2837
2838__BUILD_SET_GC0(wired)
2839__BUILD_SET_GC0(status)
2840__BUILD_SET_GC0(cause)
2841__BUILD_SET_GC0(ebase)
2842__BUILD_SET_GC0(config1)
2843
2844
2845
2846
2847
2848static inline unsigned int get_ebase_cpunum(void)
2849{
2850 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2851}
2852
2853#endif
2854
2855#endif
2856