LXR linux/arch/mips/pci/pci-ar2315.c

   1/*
   2 * This program is free software; you can redistribute it and/or
   3 * modify it under the terms of the GNU General Public License
   4 * as published by the Free Software Foundation; either version 2
   5 * of the License, or (at your option) any later version.
   6 *
   7 * This program is distributed in the hope that it will be useful,
   8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10 * GNU General Public License for more details.
  11 *
  12 * You should have received a copy of the GNU General Public License
  13 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  14 */
  15
  16/**
  17 * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  18 * and interrupt. PCI interface supports MMIO access method, but does not
  19 * seem to support I/O ports.
  20 *
  21 * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  22 * a memory read/write command on the PCI bus. 30 LSBs of address on
  23 * the bus are taken from memory read/write request and 2 MSBs are
  24 * determined by PCI unit configuration.
  25 *
  26 * To work with the configuration space instead of memory is necessary set
  27 * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  28 *
  29 * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  30 * controller BARs are programmend as if an external device is programmed.
  31 * Which means that during configuration, IDSEL pin of the chip should be
  32 * asserted.
  33 *
  34 * We know (and support) only one board that uses the PCI interface -
  35 * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  36 * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  37 * and IDSEL pin of AR2315 is connected to AD[16] line.
  38 */
  39
  40#include <linux/types.h>
  41#include <linux/pci.h>
  42#include <linux/platform_device.h>
  43#include <linux/kernel.h>
  44#include <linux/init.h>
  45#include <linux/mm.h>
  46#include <linux/delay.h>
  47#include <linux/bitops.h>
  48#include <linux/irq.h>
  49#include <linux/irqdomain.h>
  50#include <linux/io.h>
  51#include <asm/paccess.h>
  52
  53/*
  54 * PCI Bus Interface Registers
  55 */
  56#define AR2315_PCI_1MS_REG              0x0008
  57
  58#define AR2315_PCI_1MS_MASK             0x3FFFF /* # of AHB clk cycles in 1ms */
  59
  60#define AR2315_PCI_MISC_CONFIG          0x000c
  61
  62#define AR2315_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
  63#define AR2315_PCIMISC_CFG_SEL  0x00000002      /* Mem or Config cycles */
  64#define AR2315_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
  65#define AR2315_PCIMISC_RST_MODE 0x00000030
  66#define AR2315_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
  67#define AR2315_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
  68#define AR2315_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
  69#define AR2315_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
  70#define AR2315_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
  71#define AR2315_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
  72#define AR2315_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
  73#define AR2315_PCICACHE_DIS     0x00001000      /* PCI external access cache
  74                                                 * disable */
  75
  76#define AR2315_PCI_OUT_TSTAMP           0x0010
  77
  78#define AR2315_PCI_UNCACHE_CFG          0x0014
  79
  80#define AR2315_PCI_IN_EN                0x0100
  81
  82#define AR2315_PCI_IN_EN0       0x01    /* Enable chain 0 */
  83#define AR2315_PCI_IN_EN1       0x02    /* Enable chain 1 */
  84#define AR2315_PCI_IN_EN2       0x04    /* Enable chain 2 */
  85#define AR2315_PCI_IN_EN3       0x08    /* Enable chain 3 */
  86
  87#define AR2315_PCI_IN_DIS               0x0104
  88
  89#define AR2315_PCI_IN_DIS0      0x01    /* Disable chain 0 */
  90#define AR2315_PCI_IN_DIS1      0x02    /* Disable chain 1 */
  91#define AR2315_PCI_IN_DIS2      0x04    /* Disable chain 2 */
  92#define AR2315_PCI_IN_DIS3      0x08    /* Disable chain 3 */
  93
  94#define AR2315_PCI_IN_PTR               0x0200
  95
  96#define AR2315_PCI_OUT_EN               0x0400
  97
  98#define AR2315_PCI_OUT_EN0      0x01    /* Enable chain 0 */
  99
 100#define AR2315_PCI_OUT_DIS              0x0404
 101
 102#define AR2315_PCI_OUT_DIS0     0x01    /* Disable chain 0 */
 103
 104#define AR2315_PCI_OUT_PTR              0x0408
 105
 106/* PCI interrupt status (write one to clear) */
 107#define AR2315_PCI_ISR                  0x0500
 108
 109#define AR2315_PCI_INT_TX       0x00000001      /* Desc In Completed */
 110#define AR2315_PCI_INT_TXOK     0x00000002      /* Desc In OK */
 111#define AR2315_PCI_INT_TXERR    0x00000004      /* Desc In ERR */
 112#define AR2315_PCI_INT_TXEOL    0x00000008      /* Desc In End-of-List */
 113#define AR2315_PCI_INT_RX       0x00000010      /* Desc Out Completed */
 114#define AR2315_PCI_INT_RXOK     0x00000020      /* Desc Out OK */
 115#define AR2315_PCI_INT_RXERR    0x00000040      /* Desc Out ERR */
 116#define AR2315_PCI_INT_RXEOL    0x00000080      /* Desc Out EOL */
 117#define AR2315_PCI_INT_TXOOD    0x00000200      /* Desc In Out-of-Desc */
 118#define AR2315_PCI_INT_DESCMASK 0x0000FFFF      /* Desc Mask */
 119#define AR2315_PCI_INT_EXT      0x02000000      /* Extern PCI INTA */
 120#define AR2315_PCI_INT_ABORT    0x04000000      /* PCI bus abort event */
 121
 122/* PCI interrupt mask */
 123#define AR2315_PCI_IMR                  0x0504
 124
 125/* Global PCI interrupt enable */
 126#define AR2315_PCI_IER                  0x0508
 127
 128#define AR2315_PCI_IER_DISABLE          0x00    /* disable pci interrupts */
 129#define AR2315_PCI_IER_ENABLE           0x01    /* enable pci interrupts */
 130
 131#define AR2315_PCI_HOST_IN_EN           0x0800
 132#define AR2315_PCI_HOST_IN_DIS          0x0804
 133#define AR2315_PCI_HOST_IN_PTR          0x0810
 134#define AR2315_PCI_HOST_OUT_EN          0x0900
 135#define AR2315_PCI_HOST_OUT_DIS         0x0904
 136#define AR2315_PCI_HOST_OUT_PTR         0x0908
 137
 138/*
 139 * PCI interrupts, which share IP5
 140 * Keep ordered according to AR2315_PCI_INT_XXX bits
 141 */
 142#define AR2315_PCI_IRQ_EXT              25
 143#define AR2315_PCI_IRQ_ABORT            26
 144#define AR2315_PCI_IRQ_COUNT            27
 145
 146/* Arbitrary size of memory region to access the configuration space */
 147#define AR2315_PCI_CFG_SIZE     0x00100000
 148
 149#define AR2315_PCI_HOST_SLOT    3
 150#define AR2315_PCI_HOST_DEVID   ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
 151
 152/*
 153 * We need some arbitrary non-zero value to be programmed to the BAR1 register
 154 * of PCI host controller to enable DMA. The same value should be used as the
 155 * offset to calculate the physical address of DMA buffer for PCI devices.
 156 */
 157#define AR2315_PCI_HOST_SDRAM_BASEADDR  0x20000000
 158
 159/* ??? access BAR */
 160#define AR2315_PCI_HOST_MBAR0           0x10000000
 161/* RAM access BAR */
 162#define AR2315_PCI_HOST_MBAR1           AR2315_PCI_HOST_SDRAM_BASEADDR
 163/* ??? access BAR */
 164#define AR2315_PCI_HOST_MBAR2           0x30000000
 165
 166struct ar2315_pci_ctrl {
 167        void __iomem *cfg_mem;
 168        void __iomem *mmr_mem;
 169        unsigned irq;
 170        unsigned irq_ext;
 171        struct irq_domain *domain;
 172        struct pci_controller pci_ctrl;
 173        struct resource mem_res;
 174        struct resource io_res;
 175};
 176
 177static inline dma_addr_t ar2315_dev_offset(struct device *dev)
 178{
 179        if (dev && dev_is_pci(dev))
 180                return AR2315_PCI_HOST_SDRAM_BASEADDR;
 181        return 0;
 182}
 183
 184dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 185{
 186        return paddr + ar2315_dev_offset(dev);
 187}
 188
 189phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
 190{
 191        return dma_addr - ar2315_dev_offset(dev);
 192}
 193
 194static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
 195{
 196        struct pci_controller *hose = bus->sysdata;
 197
 198        return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
 199}
 200
 201static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
 202{
 203        return __raw_readl(apc->mmr_mem + reg);
 204}
 205
 206static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
 207                                        u32 val)
 208{
 209        __raw_writel(val, apc->mmr_mem + reg);
 210}
 211
 212static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
 213                                       u32 mask, u32 val)
 214{
 215        u32 ret = ar2315_pci_reg_read(apc, reg);
 216
 217        ret &= ~mask;
 218        ret |= val;
 219        ar2315_pci_reg_write(apc, reg, ret);
 220}
 221
 222static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
 223                                 int where, int size, u32 *ptr, bool write)
 224{
 225        int func = PCI_FUNC(devfn);
 226        int dev = PCI_SLOT(devfn);
 227        u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
 228        u32 mask = 0xffffffff >> 8 * (4 - size);
 229        u32 sh = (where & 3) * 8;
 230        u32 value, isr;
 231
 232        /* Prevent access past the remapped area */
 233        if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
 234                return PCIBIOS_DEVICE_NOT_FOUND;
 235
 236        /* Clear pending errors */
 237        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 238        /* Select Configuration access */
 239        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
 240                            AR2315_PCIMISC_CFG_SEL);
 241
 242        mb();   /* PCI must see space change before we begin */
 243
 244        value = __raw_readl(apc->cfg_mem + addr);
 245
 246        isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 247
 248        if (isr & AR2315_PCI_INT_ABORT)
 249                goto exit_err;
 250
 251        if (write) {
 252                value = (value & ~(mask << sh)) | *ptr << sh;
 253                __raw_writel(value, apc->cfg_mem + addr);
 254                isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 255                if (isr & AR2315_PCI_INT_ABORT)
 256                        goto exit_err;
 257        } else {
 258                *ptr = (value >> sh) & mask;
 259        }
 260
 261        goto exit;
 262
 263exit_err:
 264        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 265        if (!write)
 266                *ptr = 0xffffffff;
 267
 268exit:
 269        /* Select Memory access */
 270        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
 271                            0);
 272
 273        return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 274                                            PCIBIOS_SUCCESSFUL;
 275}
 276
 277static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
 278                                          unsigned devfn, int where, u32 *val)
 279{
 280        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
 281                                     false);
 282}
 283
 284static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
 285                                          unsigned devfn, int where, u32 val)
 286{
 287        return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
 288                                     true);
 289}
 290
 291static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
 292                               int size, u32 *value)
 293{
 294        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 295
 296        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 297                return PCIBIOS_DEVICE_NOT_FOUND;
 298
 299        return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
 300}
 301
 302static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
 303                                int size, u32 value)
 304{
 305        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 306
 307        if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 308                return PCIBIOS_DEVICE_NOT_FOUND;
 309
 310        return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
 311}
 312
 313static struct pci_ops ar2315_pci_ops = {
 314        .read   = ar2315_pci_cfg_read,
 315        .write  = ar2315_pci_cfg_write,
 316};
 317
 318static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
 319{
 320        unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 321        int res;
 322        u32 id;
 323
 324        res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
 325        if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 326                return -ENODEV;
 327
 328        /* Program MBARs */
 329        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
 330                                AR2315_PCI_HOST_MBAR0);
 331        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
 332                                AR2315_PCI_HOST_MBAR1);
 333        ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
 334                                AR2315_PCI_HOST_MBAR2);
 335
 336        /* Run */
 337        ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 338                                PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 339                                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 340                                PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 341
 342        return 0;
 343}
 344
 345static void ar2315_pci_irq_handler(struct irq_desc *desc)
 346{
 347        struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
 348        u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
 349                      ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
 350        unsigned pci_irq = 0;
 351
 352        if (pending)
 353                pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
 354
 355        if (pci_irq)
 356                generic_handle_irq(pci_irq);
 357        else
 358                spurious_interrupt();
 359}
 360
 361static void ar2315_pci_irq_mask(struct irq_data *d)
 362{
 363        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 364
 365        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
 366}
 367
 368static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 369{
 370        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 371        u32 m = BIT(d->hwirq);
 372
 373        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
 374        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
 375}
 376
 377static void ar2315_pci_irq_unmask(struct irq_data *d)
 378{
 379        struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 380
 381        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
 382}
 383
 384static struct irq_chip ar2315_pci_irq_chip = {
 385        .name = "AR2315-PCI",
 386        .irq_mask = ar2315_pci_irq_mask,
 387        .irq_mask_ack = ar2315_pci_irq_mask_ack,
 388        .irq_unmask = ar2315_pci_irq_unmask,
 389};
 390
 391static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
 392                              irq_hw_number_t hw)
 393{
 394        irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
 395        irq_set_chip_data(irq, d->host_data);
 396        return 0;
 397}
 398
 399static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
 400        .map = ar2315_pci_irq_map,
 401};
 402
 403static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
 404{
 405        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 406        ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 407                            AR2315_PCI_INT_EXT), 0);
 408
 409        apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
 410
 411        irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
 412                                         apc);
 413
 414        /* Clear any pending Abort or external Interrupts
 415         * and enable interrupt processing */
 416        ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
 417                                                  AR2315_PCI_INT_EXT);
 418        ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 419}
 420
 421static int ar2315_pci_probe(struct platform_device *pdev)
 422{
 423        struct ar2315_pci_ctrl *apc;
 424        struct device *dev = &pdev->dev;
 425        struct resource *res;
 426        int irq, err;
 427
 428        apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
 429        if (!apc)
 430                return -ENOMEM;
 431
 432        irq = platform_get_irq(pdev, 0);
 433        if (irq < 0)
 434                return -EINVAL;
 435        apc->irq = irq;
 436
 437        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 438                                           "ar2315-pci-ctrl");
 439        apc->mmr_mem = devm_ioremap_resource(dev, res);
 440        if (IS_ERR(apc->mmr_mem))
 441                return PTR_ERR(apc->mmr_mem);
 442
 443        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 444                                           "ar2315-pci-ext");
 445        if (!res)
 446                return -EINVAL;
 447
 448        apc->mem_res.name = "AR2315 PCI mem space";
 449        apc->mem_res.parent = res;
 450        apc->mem_res.start = res->start;
 451        apc->mem_res.end = res->end;
 452        apc->mem_res.flags = IORESOURCE_MEM;
 453
 454        /* Remap PCI config space */
 455        apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
 456                                            AR2315_PCI_CFG_SIZE);
 457        if (!apc->cfg_mem) {
 458                dev_err(dev, "failed to remap PCI config space\n");
 459                return -ENOMEM;
 460        }
 461
 462        /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 463        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 464                            AR2315_PCIMISC_RST_MODE,
 465                            AR2315_PCIRST_LOW);
 466        msleep(100);
 467
 468        /* Bring the PCI out of reset */
 469        ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 470                            AR2315_PCIMISC_RST_MODE,
 471                            AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 472
 473        ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
 474                             0x1E | /* 1GB uncached */
 475                             (1 << 5) | /* Enable uncached */
 476                             (0x2 << 30) /* Base: 0x80000000 */);
 477        ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
 478
 479        msleep(500);
 480
 481        err = ar2315_pci_host_setup(apc);
 482        if (err)
 483                return err;
 484
 485        apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
 486                                            &ar2315_pci_irq_domain_ops, apc);
 487        if (!apc->domain) {
 488                dev_err(dev, "failed to add IRQ domain\n");
 489                return -ENOMEM;
 490        }
 491
 492        ar2315_pci_irq_init(apc);
 493
 494        /* PCI controller does not support I/O ports */
 495        apc->io_res.name = "AR2315 IO space";
 496        apc->io_res.start = 0;
 497        apc->io_res.end = 0;
 498        apc->io_res.flags = IORESOURCE_IO,
 499
 500        apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
 501        apc->pci_ctrl.mem_resource = &apc->mem_res,
 502        apc->pci_ctrl.io_resource = &apc->io_res,
 503
 504        register_pci_controller(&apc->pci_ctrl);
 505
 506        dev_info(dev, "register PCI controller\n");
 507
 508        return 0;
 509}
 510
 511static struct platform_driver ar2315_pci_driver = {
 512        .probe = ar2315_pci_probe,
 513        .driver = {
 514                .name = "ar2315-pci",
 515        },
 516};
 517
 518static int __init ar2315_pci_init(void)
 519{
 520        return platform_driver_register(&ar2315_pci_driver);
 521}
 522arch_initcall(ar2315_pci_init);
 523
 524int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 525{
 526        struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
 527
 528        return slot ? 0 : apc->irq_ext;
 529}
 530
 531int pcibios_plat_dev_init(struct pci_dev *dev)
 532{
 533        return 0;
 534}
 535