LXR linux/arch/mips/pci/pci-ar724x.c

   1/*
   2 *  Atheros AR724X PCI host controller driver
   3 *
   4 *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
   5 *  Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   6 *
   7 *  This program is free software; you can redistribute it and/or modify it
   8 *  under the terms of the GNU General Public License version 2 as published
   9 *  by the Free Software Foundation.
  10 */
  11
  12#include <linux/irq.h>
  13#include <linux/pci.h>
  14#include <linux/init.h>
  15#include <linux/delay.h>
  16#include <linux/platform_device.h>
  17#include <asm/mach-ath79/ath79.h>
  18#include <asm/mach-ath79/ar71xx_regs.h>
  19
  20#define AR724X_PCI_REG_APP              0x00
  21#define AR724X_PCI_REG_RESET            0x18
  22#define AR724X_PCI_REG_INT_STATUS       0x4c
  23#define AR724X_PCI_REG_INT_MASK         0x50
  24
  25#define AR724X_PCI_APP_LTSSM_ENABLE     BIT(0)
  26
  27#define AR724X_PCI_RESET_LINK_UP        BIT(0)
  28
  29#define AR724X_PCI_INT_DEV0             BIT(14)
  30
  31#define AR724X_PCI_IRQ_COUNT            1
  32
  33#define AR7240_BAR0_WAR_VALUE   0xffff
  34
  35#define AR724X_PCI_CMD_INIT     (PCI_COMMAND_MEMORY |           \
  36                                 PCI_COMMAND_MASTER |           \
  37                                 PCI_COMMAND_INVALIDATE |       \
  38                                 PCI_COMMAND_PARITY |           \
  39                                 PCI_COMMAND_SERR |             \
  40                                 PCI_COMMAND_FAST_BACK)
  41
  42struct ar724x_pci_controller {
  43        void __iomem *devcfg_base;
  44        void __iomem *ctrl_base;
  45        void __iomem *crp_base;
  46
  47        int irq;
  48        int irq_base;
  49
  50        bool link_up;
  51        bool bar0_is_cached;
  52        u32  bar0_value;
  53
  54        struct pci_controller pci_controller;
  55        struct resource io_res;
  56        struct resource mem_res;
  57};
  58
  59static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
  60{
  61        u32 reset;
  62
  63        reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
  64        return reset & AR724X_PCI_RESET_LINK_UP;
  65}
  66
  67static inline struct ar724x_pci_controller *
  68pci_bus_to_ar724x_controller(struct pci_bus *bus)
  69{
  70        struct pci_controller *hose;
  71
  72        hose = (struct pci_controller *) bus->sysdata;
  73        return container_of(hose, struct ar724x_pci_controller, pci_controller);
  74}
  75
  76static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
  77                                  int where, int size, u32 value)
  78{
  79        void __iomem *base;
  80        u32 data;
  81        int s;
  82
  83        WARN_ON(where & (size - 1));
  84
  85        if (!apc->link_up)
  86                return PCIBIOS_DEVICE_NOT_FOUND;
  87
  88        base = apc->crp_base;
  89        data = __raw_readl(base + (where & ~3));
  90
  91        switch (size) {
  92        case 1:
  93                s = ((where & 3) * 8);
  94                data &= ~(0xff << s);
  95                data |= ((value & 0xff) << s);
  96                break;
  97        case 2:
  98                s = ((where & 2) * 8);
  99                data &= ~(0xffff << s);
 100                data |= ((value & 0xffff) << s);
 101                break;
 102        case 4:
 103                data = value;
 104                break;
 105        default:
 106                return PCIBIOS_BAD_REGISTER_NUMBER;
 107        }
 108
 109        __raw_writel(data, base + (where & ~3));
 110        /* flush write */
 111        __raw_readl(base + (where & ~3));
 112
 113        return PCIBIOS_SUCCESSFUL;
 114}
 115
 116static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 117                            int size, uint32_t *value)
 118{
 119        struct ar724x_pci_controller *apc;
 120        void __iomem *base;
 121        u32 data;
 122
 123        apc = pci_bus_to_ar724x_controller(bus);
 124        if (!apc->link_up)
 125                return PCIBIOS_DEVICE_NOT_FOUND;
 126
 127        if (devfn)
 128                return PCIBIOS_DEVICE_NOT_FOUND;
 129
 130        base = apc->devcfg_base;
 131        data = __raw_readl(base + (where & ~3));
 132
 133        switch (size) {
 134        case 1:
 135                if (where & 1)
 136                        data >>= 8;
 137                if (where & 2)
 138                        data >>= 16;
 139                data &= 0xff;
 140                break;
 141        case 2:
 142                if (where & 2)
 143                        data >>= 16;
 144                data &= 0xffff;
 145                break;
 146        case 4:
 147                break;
 148        default:
 149                return PCIBIOS_BAD_REGISTER_NUMBER;
 150        }
 151
 152        if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
 153            apc->bar0_is_cached) {
 154                /* use the cached value */
 155                *value = apc->bar0_value;
 156        } else {
 157                *value = data;
 158        }
 159
 160        return PCIBIOS_SUCCESSFUL;
 161}
 162
 163static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 164                             int size, uint32_t value)
 165{
 166        struct ar724x_pci_controller *apc;
 167        void __iomem *base;
 168        u32 data;
 169        int s;
 170
 171        apc = pci_bus_to_ar724x_controller(bus);
 172        if (!apc->link_up)
 173                return PCIBIOS_DEVICE_NOT_FOUND;
 174
 175        if (devfn)
 176                return PCIBIOS_DEVICE_NOT_FOUND;
 177
 178        if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
 179                if (value != 0xffffffff) {
 180                        /*
 181                         * WAR for a hw issue. If the BAR0 register of the
 182                         * device is set to the proper base address, the
 183                         * memory space of the device is not accessible.
 184                         *
 185                         * Cache the intended value so it can be read back,
 186                         * and write a SoC specific constant value to the
 187                         * BAR0 register in order to make the device memory
 188                         * accessible.
 189                         */
 190                        apc->bar0_is_cached = true;
 191                        apc->bar0_value = value;
 192
 193                        value = AR7240_BAR0_WAR_VALUE;
 194                } else {
 195                        apc->bar0_is_cached = false;
 196                }
 197        }
 198
 199        base = apc->devcfg_base;
 200        data = __raw_readl(base + (where & ~3));
 201
 202        switch (size) {
 203        case 1:
 204                s = ((where & 3) * 8);
 205                data &= ~(0xff << s);
 206                data |= ((value & 0xff) << s);
 207                break;
 208        case 2:
 209                s = ((where & 2) * 8);
 210                data &= ~(0xffff << s);
 211                data |= ((value & 0xffff) << s);
 212                break;
 213        case 4:
 214                data = value;
 215                break;
 216        default:
 217                return PCIBIOS_BAD_REGISTER_NUMBER;
 218        }
 219
 220        __raw_writel(data, base + (where & ~3));
 221        /* flush write */
 222        __raw_readl(base + (where & ~3));
 223
 224        return PCIBIOS_SUCCESSFUL;
 225}
 226
 227static struct pci_ops ar724x_pci_ops = {
 228        .read   = ar724x_pci_read,
 229        .write  = ar724x_pci_write,
 230};
 231
 232static void ar724x_pci_irq_handler(struct irq_desc *desc)
 233{
 234        struct ar724x_pci_controller *apc;
 235        void __iomem *base;
 236        u32 pending;
 237
 238        apc = irq_desc_get_handler_data(desc);
 239        base = apc->ctrl_base;
 240
 241        pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
 242                  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 243
 244        if (pending & AR724X_PCI_INT_DEV0)
 245                generic_handle_irq(apc->irq_base + 0);
 246
 247        else
 248                spurious_interrupt();
 249}
 250
 251static void ar724x_pci_irq_unmask(struct irq_data *d)
 252{
 253        struct ar724x_pci_controller *apc;
 254        void __iomem *base;
 255        int offset;
 256        u32 t;
 257
 258        apc = irq_data_get_irq_chip_data(d);
 259        base = apc->ctrl_base;
 260        offset = apc->irq_base - d->irq;
 261
 262        switch (offset) {
 263        case 0:
 264                t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 265                __raw_writel(t | AR724X_PCI_INT_DEV0,
 266                             base + AR724X_PCI_REG_INT_MASK);
 267                /* flush write */
 268                __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 269        }
 270}
 271
 272static void ar724x_pci_irq_mask(struct irq_data *d)
 273{
 274        struct ar724x_pci_controller *apc;
 275        void __iomem *base;
 276        int offset;
 277        u32 t;
 278
 279        apc = irq_data_get_irq_chip_data(d);
 280        base = apc->ctrl_base;
 281        offset = apc->irq_base - d->irq;
 282
 283        switch (offset) {
 284        case 0:
 285                t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 286                __raw_writel(t & ~AR724X_PCI_INT_DEV0,
 287                             base + AR724X_PCI_REG_INT_MASK);
 288
 289                /* flush write */
 290                __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 291
 292                t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
 293                __raw_writel(t | AR724X_PCI_INT_DEV0,
 294                             base + AR724X_PCI_REG_INT_STATUS);
 295
 296                /* flush write */
 297                __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
 298        }
 299}
 300
 301static struct irq_chip ar724x_pci_irq_chip = {
 302        .name           = "AR724X PCI ",
 303        .irq_mask       = ar724x_pci_irq_mask,
 304        .irq_unmask     = ar724x_pci_irq_unmask,
 305        .irq_mask_ack   = ar724x_pci_irq_mask,
 306};
 307
 308static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
 309                                int id)
 310{
 311        void __iomem *base;
 312        int i;
 313
 314        base = apc->ctrl_base;
 315
 316        __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
 317        __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
 318
 319        apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
 320
 321        for (i = apc->irq_base;
 322             i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
 323                irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
 324                                         handle_level_irq);
 325                irq_set_chip_data(i, apc);
 326        }
 327
 328        irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
 329                                         apc);
 330}
 331
 332static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
 333{
 334        u32 ppl, app;
 335        int wait = 0;
 336
 337        /* deassert PCIe host controller and PCIe PHY reset */
 338        ath79_device_reset_clear(AR724X_RESET_PCIE);
 339        ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
 340
 341        /* remove the reset of the PCIE PLL */
 342        ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
 343        ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
 344        ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
 345
 346        /* deassert bypass for the PCIE PLL */
 347        ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
 348        ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
 349        ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
 350
 351        /* set PCIE Application Control to ready */
 352        app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
 353        app |= AR724X_PCI_APP_LTSSM_ENABLE;
 354        __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
 355
 356        /* wait up to 100ms for PHY link up */
 357        do {
 358                mdelay(10);
 359                wait++;
 360        } while (wait < 10 && !ar724x_pci_check_link(apc));
 361}
 362
 363static int ar724x_pci_probe(struct platform_device *pdev)
 364{
 365        struct ar724x_pci_controller *apc;
 366        struct resource *res;
 367        int id;
 368
 369        id = pdev->id;
 370        if (id == -1)
 371                id = 0;
 372
 373        apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
 374                            GFP_KERNEL);
 375        if (!apc)
 376                return -ENOMEM;
 377
 378        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
 379        apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 380        if (IS_ERR(apc->ctrl_base))
 381                return PTR_ERR(apc->ctrl_base);
 382
 383        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
 384        apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res);
 385        if (IS_ERR(apc->devcfg_base))
 386                return PTR_ERR(apc->devcfg_base);
 387
 388        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
 389        apc->crp_base = devm_ioremap_resource(&pdev->dev, res);
 390        if (IS_ERR(apc->crp_base))
 391                return PTR_ERR(apc->crp_base);
 392
 393        apc->irq = platform_get_irq(pdev, 0);
 394        if (apc->irq < 0)
 395                return -EINVAL;
 396
 397        res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 398        if (!res)
 399                return -EINVAL;
 400
 401        apc->io_res.parent = res;
 402        apc->io_res.name = "PCI IO space";
 403        apc->io_res.start = res->start;
 404        apc->io_res.end = res->end;
 405        apc->io_res.flags = IORESOURCE_IO;
 406
 407        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 408        if (!res)
 409                return -EINVAL;
 410
 411        apc->mem_res.parent = res;
 412        apc->mem_res.name = "PCI memory space";
 413        apc->mem_res.start = res->start;
 414        apc->mem_res.end = res->end;
 415        apc->mem_res.flags = IORESOURCE_MEM;
 416
 417        apc->pci_controller.pci_ops = &ar724x_pci_ops;
 418        apc->pci_controller.io_resource = &apc->io_res;
 419        apc->pci_controller.mem_resource = &apc->mem_res;
 420
 421        /*
 422         * Do the full PCIE Root Complex Initialization Sequence if the PCIe
 423         * host controller is in reset.
 424         */
 425        if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
 426                ar724x_pci_hw_init(apc);
 427
 428        apc->link_up = ar724x_pci_check_link(apc);
 429        if (!apc->link_up)
 430                dev_warn(&pdev->dev, "PCIe link is down\n");
 431
 432        ar724x_pci_irq_init(apc, id);
 433
 434        ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
 435
 436        register_pci_controller(&apc->pci_controller);
 437
 438        return 0;
 439}
 440
 441static struct platform_driver ar724x_pci_driver = {
 442        .probe = ar724x_pci_probe,
 443        .driver = {
 444                .name = "ar724x-pci",
 445        },
 446};
 447
 448static int __init ar724x_pci_init(void)
 449{
 450        return platform_driver_register(&ar724x_pci_driver);
 451}
 452
 453postcore_initcall(ar724x_pci_init);
 454