1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_BOOK3S_32_HASH_H 3#define _ASM_POWERPC_BOOK3S_32_HASH_H 4#ifdef __KERNEL__ 5 6/* 7 * The "classic" 32-bit implementation of the PowerPC MMU uses a hash 8 * table containing PTEs, together with a set of 16 segment registers, 9 * to define the virtual to physical address mapping. 10 * 11 * We use the hash table as an extended TLB, i.e. a cache of currently 12 * active mappings. We maintain a two-level page table tree, much 13 * like that used by the i386, for the sake of the Linux memory 14 * management code. Low-level assembler code in hash_low_32.S 15 * (procedure hash_page) is responsible for extracting ptes from the 16 * tree and putting them into the hash table when necessary, and 17 * updating the accessed and modified bits in the page table tree. 18 */ 19 20#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ 21#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ 22#define _PAGE_USER 0x004 /* usermode access allowed */ 23#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ 24#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ 25#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ 26#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ 27#define _PAGE_DIRTY 0x080 /* C: page changed */ 28#define _PAGE_ACCESSED 0x100 /* R: page referenced */ 29#define _PAGE_EXEC 0x200 /* software: exec allowed */ 30#define _PAGE_RW 0x400 /* software: user write access allowed */ 31#define _PAGE_SPECIAL 0x800 /* software: Special page */ 32 33#ifdef CONFIG_PTE_64BIT 34/* We never clear the high word of the pte */ 35#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE) 36#else 37#define _PTE_NONE_MASK _PAGE_HASHPTE 38#endif 39 40#define _PMD_PRESENT 0 41#define _PMD_PRESENT_MASK (PAGE_MASK) 42#define _PMD_BAD (~PAGE_MASK) 43 44#endif /* __KERNEL__ */ 45#endif /* _ASM_POWERPC_BOOK3S_32_HASH_H */ 46