LXR linux/arch/xtensa/include/asm/pgtable.h

   1/*
   2 * include/asm-xtensa/pgtable.h
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * Copyright (C) 2001 - 2013 Tensilica Inc.
   9 */
  10
  11#ifndef _XTENSA_PGTABLE_H
  12#define _XTENSA_PGTABLE_H
  13
  14#define __ARCH_USE_5LEVEL_HACK
  15#include <asm/page.h>
  16#include <asm/kmem_layout.h>
  17#include <asm-generic/pgtable-nopmd.h>
  18
  19/*
  20 * We only use two ring levels, user and kernel space.
  21 */
  22
  23#ifdef CONFIG_MMU
  24#define USER_RING               1       /* user ring level */
  25#else
  26#define USER_RING               0
  27#endif
  28#define KERNEL_RING             0       /* kernel ring level */
  29
  30/*
  31 * The Xtensa architecture port of Linux has a two-level page table system,
  32 * i.e. the logical three-level Linux page table layout is folded.
  33 * Each task has the following memory page tables:
  34 *
  35 *   PGD table (page directory), ie. 3rd-level page table:
  36 *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
  37 *      (Architectures that don't have the PMD folded point to the PMD tables)
  38 *
  39 *      The pointer to the PGD table for a given task can be retrieved from
  40 *      the task structure (struct task_struct*) t, e.g. current():
  41 *        (t->mm ? t->mm : t->active_mm)->pgd
  42 *
  43 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
  44 *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
  45 *
  46 *   PTE tables (page table entry), ie. 1st-level page tables:
  47 *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
  48 *      invalid_pte_table for absent mappings.
  49 *
  50 * The individual pages are 4 kB big with special pages for the empty_zero_page.
  51 */
  52
  53#define PGDIR_SHIFT     22
  54#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  55#define PGDIR_MASK      (~(PGDIR_SIZE-1))
  56
  57/*
  58 * Entries per page directory level: we use two-level, so
  59 * we don't really have any PMD directory physically.
  60 */
  61#define PTRS_PER_PTE            1024
  62#define PTRS_PER_PTE_SHIFT      10
  63#define PTRS_PER_PGD            1024
  64#define PGD_ORDER               0
  65#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  66#define FIRST_USER_ADDRESS      0UL
  67#define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
  68
  69#ifdef CONFIG_MMU
  70/*
  71 * Virtual memory area. We keep a distance to other memory regions to be
  72 * on the safe side. We also use this area for cache aliasing.
  73 */
  74#define VMALLOC_START           (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
  75#define VMALLOC_END             (VMALLOC_START + 0x07FEFFFF)
  76#define TLBTEMP_BASE_1          (VMALLOC_END + 1)
  77#define TLBTEMP_BASE_2          (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
  78#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
  79#define TLBTEMP_SIZE            (2 * DCACHE_WAY_SIZE)
  80#else
  81#define TLBTEMP_SIZE            ICACHE_WAY_SIZE
  82#endif
  83
  84#else
  85
  86#define VMALLOC_START           __XTENSA_UL_CONST(0)
  87#define VMALLOC_END             __XTENSA_UL_CONST(0xffffffff)
  88
  89#endif
  90
  91/*
  92 * For the Xtensa architecture, the PTE layout is as follows:
  93 *
  94 *              31------12  11  10-9   8-6  5-4  3-2  1-0
  95 *              +-----------------------------------------+
  96 *              |           |   Software   |   HARDWARE   |
  97 *              |    PPN    |          ADW | RI |Attribute|
  98 *              +-----------------------------------------+
  99 *   pte_none   |             MBZ          | 01 | 11 | 00 |
 100 *              +-----------------------------------------+
 101 *   present    |    PPN    | 0 | 00 | ADW | RI | CA | wx |
 102 *              +- - - - - - - - - - - - - - - - - - - - -+
 103 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
 104 *              +-----------------------------------------+
 105 *   swap       |     index     |   type   | 01 | 11 | 00 |
 106 *              +-----------------------------------------+
 107 *
 108 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
 109 *              +-----------------------------------------+
 110 *   present    |    PPN    | 0 | 00 | ADW | RI | CA | w1 |
 111 *              +-----------------------------------------+
 112 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
 113 *              +-----------------------------------------+
 114 *
 115 *  Legend:
 116 *   PPN        Physical Page Number
 117 *   ADW        software: accessed (young) / dirty / writable
 118 *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
 119 *   CA         cache attribute: 00 bypass, 01 writeback, 10 writethrough
 120 *              (11 is invalid and used to mark pages that are not present)
 121 *   w          page is writable (hw)
 122 *   x          page is executable (hw)
 123 *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
 124 *              (note that the index is always non-zero)
 125 *   type       swap type (5 bits -> 32 types)
 126 *
 127 *  Notes:
 128 *   - (PROT_NONE) is a special case of 'present' but causes an exception for
 129 *     any access (read, write, and execute).
 130 *   - 'multihit-exception' has the highest priority of all MMU exceptions,
 131 *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
 132 *   - on older hardware, the exectuable flag was not supported and
 133 *     used as a 'valid' flag, so it needs to be always set.
 134 *   - we need to keep track of certain flags in software (dirty and young)
 135 *     to do this, we use write exceptions and have a separate software w-flag.
 136 *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
 137 */
 138
 139#define _PAGE_ATTRIB_MASK       0xf
 140
 141#define _PAGE_HW_EXEC           (1<<0)  /* hardware: page is executable */
 142#define _PAGE_HW_WRITE          (1<<1)  /* hardware: page is writable */
 143
 144#define _PAGE_CA_BYPASS         (0<<2)  /* bypass, non-speculative */
 145#define _PAGE_CA_WB             (1<<2)  /* write-back */
 146#define _PAGE_CA_WT             (2<<2)  /* write-through */
 147#define _PAGE_CA_MASK           (3<<2)
 148#define _PAGE_CA_INVALID        (3<<2)
 149
 150/* We use invalid attribute values to distinguish special pte entries */
 151#if XCHAL_HW_VERSION_MAJOR < 2000
 152#define _PAGE_HW_VALID          0x01    /* older HW needed this bit set */
 153#define _PAGE_NONE              0x04
 154#else
 155#define _PAGE_HW_VALID          0x00
 156#define _PAGE_NONE              0x0f
 157#endif
 158
 159#define _PAGE_USER              (1<<4)  /* user access (ring=1) */
 160
 161/* Software */
 162#define _PAGE_WRITABLE_BIT      6
 163#define _PAGE_WRITABLE          (1<<6)  /* software: page writable */
 164#define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
 165#define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
 166
 167#ifdef CONFIG_MMU
 168
 169#define _PAGE_CHG_MASK     (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 170#define _PAGE_PRESENT      (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
 171
 172#define PAGE_NONE          __pgprot(_PAGE_NONE | _PAGE_USER)
 173#define PAGE_COPY          __pgprot(_PAGE_PRESENT | _PAGE_USER)
 174#define PAGE_COPY_EXEC     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 175#define PAGE_READONLY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
 176#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 177#define PAGE_SHARED        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
 178#define PAGE_SHARED_EXEC \
 179        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
 180#define PAGE_KERNEL        __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
 181#define PAGE_KERNEL_RO     __pgprot(_PAGE_PRESENT)
 182#define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
 183
 184#if (DCACHE_WAY_SIZE > PAGE_SIZE)
 185# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
 186#else
 187# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
 188#endif
 189
 190#else /* no mmu */
 191
 192# define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 193# define PAGE_NONE       __pgprot(0)
 194# define PAGE_SHARED     __pgprot(0)
 195# define PAGE_COPY       __pgprot(0)
 196# define PAGE_READONLY   __pgprot(0)
 197# define PAGE_KERNEL     __pgprot(0)
 198
 199#endif
 200
 201/*
 202 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 203 * the MMU can't do page protection for execute, and considers that the same as
 204 * read.  Also, write permissions may imply read permissions.
 205 * What follows is the closest we can get by reasonable means..
 206 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 207 */
 208#define __P000  PAGE_NONE               /* private --- */
 209#define __P001  PAGE_READONLY           /* private --r */
 210#define __P010  PAGE_COPY               /* private -w- */
 211#define __P011  PAGE_COPY               /* private -wr */
 212#define __P100  PAGE_READONLY_EXEC      /* private x-- */
 213#define __P101  PAGE_READONLY_EXEC      /* private x-r */
 214#define __P110  PAGE_COPY_EXEC          /* private xw- */
 215#define __P111  PAGE_COPY_EXEC          /* private xwr */
 216
 217#define __S000  PAGE_NONE               /* shared  --- */
 218#define __S001  PAGE_READONLY           /* shared  --r */
 219#define __S010  PAGE_SHARED             /* shared  -w- */
 220#define __S011  PAGE_SHARED             /* shared  -wr */
 221#define __S100  PAGE_READONLY_EXEC      /* shared  x-- */
 222#define __S101  PAGE_READONLY_EXEC      /* shared  x-r */
 223#define __S110  PAGE_SHARED_EXEC        /* shared  xw- */
 224#define __S111  PAGE_SHARED_EXEC        /* shared  xwr */
 225
 226#ifndef __ASSEMBLY__
 227
 228#define pte_ERROR(e) \
 229        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 230#define pgd_ERROR(e) \
 231        printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 232
 233extern unsigned long empty_zero_page[1024];
 234
 235#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 236
 237#ifdef CONFIG_MMU
 238extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
 239extern void paging_init(void);
 240#else
 241# define swapper_pg_dir NULL
 242static inline void paging_init(void) { }
 243#endif
 244static inline void pgtable_cache_init(void) { }
 245
 246/*
 247 * The pmd contains the kernel virtual address of the pte page.
 248 */
 249#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
 250#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
 251
 252/*
 253 * pte status.
 254 */
 255# define pte_none(pte)   (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
 256#if XCHAL_HW_VERSION_MAJOR < 2000
 257# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
 258#else
 259# define pte_present(pte)                                               \
 260        (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)           \
 261         || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
 262#endif
 263#define pte_clear(mm,addr,ptep)                                         \
 264        do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
 265
 266#define pmd_none(pmd)    (!pmd_val(pmd))
 267#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
 268#define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
 269#define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
 270
 271static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
 272static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 273static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 274static inline int pte_special(pte_t pte) { return 0; }
 275
 276static inline pte_t pte_wrprotect(pte_t pte)    
 277        { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
 278static inline pte_t pte_mkclean(pte_t pte)
 279        { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
 280static inline pte_t pte_mkold(pte_t pte)
 281        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 282static inline pte_t pte_mkdirty(pte_t pte)
 283        { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 284static inline pte_t pte_mkyoung(pte_t pte)
 285        { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 286static inline pte_t pte_mkwrite(pte_t pte)
 287        { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
 288static inline pte_t pte_mkspecial(pte_t pte)
 289        { return pte; }
 290
 291#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
 292
 293/*
 294 * Conversion functions: convert a page and protection to a page entry,
 295 * and a page entry and page directory to the page they refer to.
 296 */
 297
 298#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 299#define pte_same(a,b)           (pte_val(a) == pte_val(b))
 300#define pte_page(x)             pfn_to_page(pte_pfn(x))
 301#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 302#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 303
 304static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 305{
 306        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 307}
 308
 309/*
 310 * Certain architectures need to do special things when pte's
 311 * within a page table are directly modified.  Thus, the following
 312 * hook is made available.
 313 */
 314static inline void update_pte(pte_t *ptep, pte_t pteval)
 315{
 316        *ptep = pteval;
 317#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 318        __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
 319#endif
 320
 321}
 322
 323struct mm_struct;
 324
 325static inline void
 326set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
 327{
 328        update_pte(ptep, pteval);
 329}
 330
 331static inline void set_pte(pte_t *ptep, pte_t pteval)
 332{
 333        update_pte(ptep, pteval);
 334}
 335
 336static inline void
 337set_pmd(pmd_t *pmdp, pmd_t pmdval)
 338{
 339        *pmdp = pmdval;
 340}
 341
 342struct vm_area_struct;
 343
 344static inline int
 345ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
 346                          pte_t *ptep)
 347{
 348        pte_t pte = *ptep;
 349        if (!pte_young(pte))
 350                return 0;
 351        update_pte(ptep, pte_mkold(pte));
 352        return 1;
 353}
 354
 355static inline pte_t
 356ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 357{
 358        pte_t pte = *ptep;
 359        pte_clear(mm, addr, ptep);
 360        return pte;
 361}
 362
 363static inline void
 364ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 365{
 366        pte_t pte = *ptep;
 367        update_pte(ptep, pte_wrprotect(pte));
 368}
 369
 370/* to find an entry in a kernel page-table-directory */
 371#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 372
 373/* to find an entry in a page-table-directory */
 374#define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
 375
 376#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 377
 378/* Find an entry in the second-level page table.. */
 379#define pmd_offset(dir,address) ((pmd_t*)(dir))
 380
 381/* Find an entry in the third-level page table.. */
 382#define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 383#define pte_offset_kernel(dir,addr)                                     \
 384        ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
 385#define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
 386#define pte_unmap(pte)          do { } while (0)
 387
 388
 389/*
 390 * Encode and decode a swap and file entry.
 391 */
 392#define SWP_TYPE_BITS           5
 393#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
 394
 395#define __swp_type(entry)       (((entry).val >> 6) & 0x1f)
 396#define __swp_offset(entry)     ((entry).val >> 11)
 397#define __swp_entry(type,offs)  \
 398        ((swp_entry_t){((type) << 6) | ((offs) << 11) | \
 399         _PAGE_CA_INVALID | _PAGE_USER})
 400#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 401#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 402
 403#endif /*  !defined (__ASSEMBLY__) */
 404
 405
 406#ifdef __ASSEMBLY__
 407
 408/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 409 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 410 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 411 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 412 *
 413 * Note: We require an additional temporary register which can be the same as
 414 *       the register that holds the address.
 415 *
 416 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 417 *
 418 */
 419#define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
 420#define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
 421
 422#define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
 423                                        _PGD_INDEX(tmp, adr);           \
 424                                        addx4   mm, tmp, mm
 425
 426#define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
 427                                        srli    pmd, pmd, PAGE_SHIFT;   \
 428                                        slli    pmd, pmd, PAGE_SHIFT;   \
 429                                        addx4   pmd, tmp, pmd
 430
 431#else
 432
 433#define kern_addr_valid(addr)   (1)
 434
 435extern  void update_mmu_cache(struct vm_area_struct * vma,
 436                              unsigned long address, pte_t *ptep);
 437
 438typedef pte_t *pte_addr_t;
 439
 440#endif /* !defined (__ASSEMBLY__) */
 441
 442#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 443#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 444#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 445#define __HAVE_ARCH_PTEP_MKDIRTY
 446#define __HAVE_ARCH_PTE_SAME
 447/* We provide our own get_unmapped_area to cope with
 448 * SHM area cache aliasing for userland.
 449 */
 450#define HAVE_ARCH_UNMAPPED_AREA
 451
 452#include <asm-generic/pgtable.h>
 453
 454#endif /* _XTENSA_PGTABLE_H */
 455