1
2#ifndef __MACH_IMX_CLK_H
3#define __MACH_IMX_CLK_H
4
5#include <linux/spinlock.h>
6#include <linux/clk-provider.h>
7
8extern spinlock_t imx_ccm_lock;
9
10void imx_check_clocks(struct clk *clks[], unsigned int count);
11void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
12void imx_register_uart_clocks(struct clk ** const clks[]);
13
14extern void imx_cscmr1_fixup(u32 *val);
15
16enum imx_pllv1_type {
17 IMX_PLLV1_IMX1,
18 IMX_PLLV1_IMX21,
19 IMX_PLLV1_IMX25,
20 IMX_PLLV1_IMX27,
21 IMX_PLLV1_IMX31,
22 IMX_PLLV1_IMX35,
23};
24
25enum imx_sccg_pll_type {
26 SCCG_PLL1,
27 SCCG_PLL2,
28};
29
30enum imx_pll14xx_type {
31 PLL_1416X,
32 PLL_1443X,
33};
34
35
36struct imx_pll14xx_rate_table {
37 unsigned int rate;
38 unsigned int pdiv;
39 unsigned int mdiv;
40 unsigned int sdiv;
41 unsigned int kdiv;
42};
43
44struct imx_pll14xx_clk {
45 enum imx_pll14xx_type type;
46 const struct imx_pll14xx_rate_table *rate_table;
47 int rate_count;
48 int flags;
49};
50
51struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
52 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
53
54struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
55 const char *parent, void __iomem *base);
56
57struct clk *imx_clk_pllv2(const char *name, const char *parent,
58 void __iomem *base);
59
60struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
61 void __iomem *base);
62
63struct clk *imx_clk_sccg_pll(const char *name,
64 const char * const *parent_names,
65 u8 num_parents,
66 u8 parent, u8 bypass1, u8 bypass2,
67 void __iomem *base,
68 unsigned long flags);
69
70enum imx_pllv3_type {
71 IMX_PLLV3_GENERIC,
72 IMX_PLLV3_SYS,
73 IMX_PLLV3_USB,
74 IMX_PLLV3_USB_VF610,
75 IMX_PLLV3_AV,
76 IMX_PLLV3_ENET,
77 IMX_PLLV3_ENET_IMX7,
78 IMX_PLLV3_SYS_VF610,
79 IMX_PLLV3_DDR_IMX7,
80};
81
82struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
83 const char *parent_name, void __iomem *base, u32 div_mask);
84
85struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
86 void __iomem *base);
87
88struct clk *clk_register_gate2(struct device *dev, const char *name,
89 const char *parent_name, unsigned long flags,
90 void __iomem *reg, u8 bit_idx, u8 cgr_val,
91 u8 clk_gate_flags, spinlock_t *lock,
92 unsigned int *share_count);
93
94struct clk * imx_obtain_fixed_clock(
95 const char *name, unsigned long rate);
96
97struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
98 const char *name);
99
100struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
101 void __iomem *reg, u8 shift, u32 exclusive_mask);
102
103struct clk *imx_clk_pfd(const char *name, const char *parent_name,
104 void __iomem *reg, u8 idx);
105
106struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
107 void __iomem *reg, u8 idx);
108
109struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
110 void __iomem *reg, u8 shift, u8 width,
111 void __iomem *busy_reg, u8 busy_shift);
112
113struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
114 u8 width, void __iomem *busy_reg, u8 busy_shift,
115 const char * const *parent_names, int num_parents);
116
117struct clk_hw *imx7ulp_clk_composite(const char *name,
118 const char * const *parent_names,
119 int num_parents, bool mux_present,
120 bool rate_present, bool gate_present,
121 void __iomem *reg);
122
123struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
124 void __iomem *reg, u8 shift, u8 width,
125 void (*fixup)(u32 *val));
126
127struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
128 u8 shift, u8 width, const char * const *parents,
129 int num_parents, void (*fixup)(u32 *val));
130
131static inline struct clk *imx_clk_fixed(const char *name, int rate)
132{
133 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
134}
135
136static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
137{
138 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
139}
140
141static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
142{
143 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
144}
145
146static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
147 u8 shift, u8 width, const char * const *parents,
148 int num_parents)
149{
150 return clk_register_mux(NULL, name, parents, num_parents,
151 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
152 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
153}
154
155static inline struct clk *imx_clk_fixed_factor(const char *name,
156 const char *parent, unsigned int mult, unsigned int div)
157{
158 return clk_register_fixed_factor(NULL, name, parent,
159 CLK_SET_RATE_PARENT, mult, div);
160}
161
162static inline struct clk *imx_clk_divider(const char *name, const char *parent,
163 void __iomem *reg, u8 shift, u8 width)
164{
165 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
166 reg, shift, width, 0, &imx_ccm_lock);
167}
168
169static inline struct clk_hw *imx_clk_hw_divider(const char *name,
170 const char *parent,
171 void __iomem *reg, u8 shift,
172 u8 width)
173{
174 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
175 reg, shift, width, 0, &imx_ccm_lock);
176}
177
178static inline struct clk *imx_clk_divider_flags(const char *name,
179 const char *parent, void __iomem *reg, u8 shift, u8 width,
180 unsigned long flags)
181{
182 return clk_register_divider(NULL, name, parent, flags,
183 reg, shift, width, 0, &imx_ccm_lock);
184}
185
186static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
187 const char *parent,
188 void __iomem *reg, u8 shift,
189 u8 width, unsigned long flags)
190{
191 return clk_hw_register_divider(NULL, name, parent, flags,
192 reg, shift, width, 0, &imx_ccm_lock);
193}
194
195static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
196 void __iomem *reg, u8 shift, u8 width)
197{
198 return clk_register_divider(NULL, name, parent,
199 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
200 reg, shift, width, 0, &imx_ccm_lock);
201}
202
203static inline struct clk *imx_clk_divider2_flags(const char *name,
204 const char *parent, void __iomem *reg, u8 shift, u8 width,
205 unsigned long flags)
206{
207 return clk_register_divider(NULL, name, parent,
208 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
209 reg, shift, width, 0, &imx_ccm_lock);
210}
211
212static inline struct clk *imx_clk_gate(const char *name, const char *parent,
213 void __iomem *reg, u8 shift)
214{
215 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
216 shift, 0, &imx_ccm_lock);
217}
218
219static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
220 void __iomem *reg, u8 shift, unsigned long flags)
221{
222 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
223 shift, 0, &imx_ccm_lock);
224}
225
226static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
227 void __iomem *reg, u8 shift)
228{
229 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
230 shift, 0, &imx_ccm_lock);
231}
232
233static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
234 void __iomem *reg, u8 shift)
235{
236 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
237 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
238}
239
240static inline struct clk *imx_clk_gate_dis_flags(const char *name, const char *parent,
241 void __iomem *reg, u8 shift, unsigned long flags)
242{
243 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
244 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
245}
246
247static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
248 void __iomem *reg, u8 shift)
249{
250 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
251 shift, 0x3, 0, &imx_ccm_lock, NULL);
252}
253
254static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
255 void __iomem *reg, u8 shift, unsigned long flags)
256{
257 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
258 shift, 0x3, 0, &imx_ccm_lock, NULL);
259}
260
261static inline struct clk *imx_clk_gate2_shared(const char *name,
262 const char *parent, void __iomem *reg, u8 shift,
263 unsigned int *share_count)
264{
265 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
266 shift, 0x3, 0, &imx_ccm_lock, share_count);
267}
268
269static inline struct clk *imx_clk_gate2_shared2(const char *name,
270 const char *parent, void __iomem *reg, u8 shift,
271 unsigned int *share_count)
272{
273 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
274 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
275 &imx_ccm_lock, share_count);
276}
277
278static inline struct clk *imx_clk_gate2_cgr(const char *name,
279 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
280{
281 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
282 shift, cgr_val, 0, &imx_ccm_lock, NULL);
283}
284
285static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
286 void __iomem *reg, u8 shift)
287{
288 return clk_register_gate(NULL, name, parent,
289 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
290 reg, shift, 0, &imx_ccm_lock);
291}
292
293static inline struct clk *imx_clk_gate3_flags(const char *name,
294 const char *parent, void __iomem *reg, u8 shift,
295 unsigned long flags)
296{
297 return clk_register_gate(NULL, name, parent,
298 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
299 reg, shift, 0, &imx_ccm_lock);
300}
301
302static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
303 void __iomem *reg, u8 shift)
304{
305 return clk_register_gate2(NULL, name, parent,
306 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
307 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
308}
309
310static inline struct clk *imx_clk_gate4_flags(const char *name,
311 const char *parent, void __iomem *reg, u8 shift,
312 unsigned long flags)
313{
314 return clk_register_gate2(NULL, name, parent,
315 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
316 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
317}
318
319static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
320 u8 shift, u8 width, const char * const *parents,
321 int num_parents)
322{
323 return clk_register_mux(NULL, name, parents, num_parents,
324 CLK_SET_RATE_NO_REPARENT, reg, shift,
325 width, 0, &imx_ccm_lock);
326}
327
328static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
329 u8 shift, u8 width, const char * const *parents,
330 int num_parents)
331{
332 return clk_register_mux(NULL, name, parents, num_parents,
333 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
334 reg, shift, width, 0, &imx_ccm_lock);
335}
336
337static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
338 u8 shift, u8 width,
339 const char * const *parents,
340 int num_parents)
341{
342 return clk_hw_register_mux(NULL, name, parents, num_parents,
343 CLK_SET_RATE_NO_REPARENT |
344 CLK_OPS_PARENT_ENABLE,
345 reg, shift, width, 0, &imx_ccm_lock);
346}
347
348static inline struct clk *imx_clk_mux_flags(const char *name,
349 void __iomem *reg, u8 shift, u8 width,
350 const char * const *parents, int num_parents,
351 unsigned long flags)
352{
353 return clk_register_mux(NULL, name, parents, num_parents,
354 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
355 &imx_ccm_lock);
356}
357
358static inline struct clk *imx_clk_mux2_flags(const char *name,
359 void __iomem *reg, u8 shift, u8 width,
360 const char * const *parents,
361 int num_parents, unsigned long flags)
362{
363 return clk_register_mux(NULL, name, parents, num_parents,
364 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
365 reg, shift, width, 0, &imx_ccm_lock);
366}
367
368static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
369 void __iomem *reg, u8 shift,
370 u8 width,
371 const char * const *parents,
372 int num_parents,
373 unsigned long flags)
374{
375 return clk_hw_register_mux(NULL, name, parents, num_parents,
376 flags | CLK_SET_RATE_NO_REPARENT,
377 reg, shift, width, 0, &imx_ccm_lock);
378}
379
380struct clk *imx_clk_cpu(const char *name, const char *parent_name,
381 struct clk *div, struct clk *mux, struct clk *pll,
382 struct clk *step);
383
384struct clk *imx8m_clk_composite_flags(const char *name,
385 const char * const *parent_names,
386 int num_parents, void __iomem *reg,
387 unsigned long flags);
388
389#define __imx8m_clk_composite(name, parent_names, reg, flags) \
390 imx8m_clk_composite_flags(name, parent_names, \
391 ARRAY_SIZE(parent_names), reg, \
392 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
393
394#define imx8m_clk_composite(name, parent_names, reg) \
395 __imx8m_clk_composite(name, parent_names, reg, 0)
396
397#define imx8m_clk_composite_critical(name, parent_names, reg) \
398 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
399
400struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
401 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
402 u8 clk_divider_flags, const struct clk_div_table *table,
403 spinlock_t *lock);
404#endif
405
