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7#include <linux/clk.h>
8#include <linux/clk-provider.h>
9#include <linux/init.h>
10#include <linux/of_device.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/reset.h>
15#include <linux/slab.h>
16
17#include "axg-audio.h"
18#include "clk-input.h"
19#include "clk-regmap.h"
20#include "clk-phase.h"
21#include "sclk-div.h"
22
23#define AXG_MST_IN_COUNT 8
24#define AXG_SLV_SCLK_COUNT 10
25#define AXG_SLV_LRCLK_COUNT 10
26
27#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \
28struct clk_regmap axg_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \
30 .offset = (_reg), \
31 .bit_idx = (_bit), \
32 }, \
33 .hw.init = &(struct clk_init_data) { \
34 .name = "axg_"#_name, \
35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \
37 .num_parents = 1, \
38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
39 }, \
40}
41
42#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
43struct clk_regmap axg_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \
45 .offset = (_reg), \
46 .mask = (_mask), \
47 .shift = (_shift), \
48 .flags = (_dflags), \
49 }, \
50 .hw.init = &(struct clk_init_data){ \
51 .name = "axg_"#_name, \
52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \
54 .num_parents = ARRAY_SIZE(_pnames), \
55 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
56 }, \
57}
58
59#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
60struct clk_regmap axg_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \
62 .offset = (_reg), \
63 .shift = (_shift), \
64 .width = (_width), \
65 .flags = (_dflags), \
66 }, \
67 .hw.init = &(struct clk_init_data){ \
68 .name = "axg_"#_name, \
69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \
71 .num_parents = 1, \
72 .flags = (_iflags), \
73 }, \
74}
75
76#define AXG_PCLK_GATE(_name, _bit) \
77 AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)
78
79
80static AXG_PCLK_GATE(ddr_arb, 0);
81static AXG_PCLK_GATE(pdm, 1);
82static AXG_PCLK_GATE(tdmin_a, 2);
83static AXG_PCLK_GATE(tdmin_b, 3);
84static AXG_PCLK_GATE(tdmin_c, 4);
85static AXG_PCLK_GATE(tdmin_lb, 5);
86static AXG_PCLK_GATE(tdmout_a, 6);
87static AXG_PCLK_GATE(tdmout_b, 7);
88static AXG_PCLK_GATE(tdmout_c, 8);
89static AXG_PCLK_GATE(frddr_a, 9);
90static AXG_PCLK_GATE(frddr_b, 10);
91static AXG_PCLK_GATE(frddr_c, 11);
92static AXG_PCLK_GATE(toddr_a, 12);
93static AXG_PCLK_GATE(toddr_b, 13);
94static AXG_PCLK_GATE(toddr_c, 14);
95static AXG_PCLK_GATE(loopback, 15);
96static AXG_PCLK_GATE(spdifin, 16);
97static AXG_PCLK_GATE(spdifout, 17);
98static AXG_PCLK_GATE(resample, 18);
99static AXG_PCLK_GATE(power_detect, 19);
100
101
102static const char * const mst_mux_parent_names[] = {
103 "axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3",
104 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
105};
106
107#define AXG_MST_MUX(_name, _reg, _flag) \
108 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
109 mst_mux_parent_names, CLK_SET_RATE_PARENT)
110
111#define AXG_MST_MCLK_MUX(_name, _reg) \
112 AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
113
114#define AXG_MST_SYS_MUX(_name, _reg) \
115 AXG_MST_MUX(_name, _reg, 0)
116
117static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
118static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
119static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
120static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
121static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
122static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
123static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
124static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
125static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
126static AXG_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
127
128#define AXG_MST_DIV(_name, _reg, _flag) \
129 AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
130 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \
131
132#define AXG_MST_MCLK_DIV(_name, _reg) \
133 AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
134
135#define AXG_MST_SYS_DIV(_name, _reg) \
136 AXG_MST_DIV(_name, _reg, 0)
137
138static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
139static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
140static AXG_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
141static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
142static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
143static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
144static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
145static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
146static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
147static AXG_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
148
149#define AXG_MST_MCLK_GATE(_name, _reg) \
150 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \
151 CLK_SET_RATE_PARENT)
152
153static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
154static AXG_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
155static AXG_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
156static AXG_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
157static AXG_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
158static AXG_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
159static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
160static AXG_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
161static AXG_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
162static AXG_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
163
164
165#define AXG_MST_SCLK_PRE_EN(_name, _reg) \
166 AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
167 "axg_mst_"#_name"_mclk", 0)
168
169static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
170static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
171static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
172static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
173static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
174static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
175
176#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
177 _hi_shift, _hi_width, _pname, _iflags) \
178struct clk_regmap axg_##_name = { \
179 .data = &(struct meson_sclk_div_data) { \
180 .div = { \
181 .reg_off = (_reg), \
182 .shift = (_div_shift), \
183 .width = (_div_width), \
184 }, \
185 .hi = { \
186 .reg_off = (_reg), \
187 .shift = (_hi_shift), \
188 .width = (_hi_width), \
189 }, \
190 }, \
191 .hw.init = &(struct clk_init_data) { \
192 .name = "axg_"#_name, \
193 .ops = &meson_sclk_div_ops, \
194 .parent_names = (const char *[]) { _pname }, \
195 .num_parents = 1, \
196 .flags = (_iflags), \
197 }, \
198}
199
200#define AXG_MST_SCLK_DIV(_name, _reg) \
201 AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
202 "axg_mst_"#_name"_sclk_pre_en", \
203 CLK_SET_RATE_PARENT)
204
205static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
206static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
207static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
208static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
209static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
210static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
211
212#define AXG_MST_SCLK_POST_EN(_name, _reg) \
213 AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
214 "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
215
216static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
217static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
218static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
219static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
220static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
221static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
222
223#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
224 _pname, _iflags) \
225struct clk_regmap axg_##_name = { \
226 .data = &(struct meson_clk_triphase_data) { \
227 .ph0 = { \
228 .reg_off = (_reg), \
229 .shift = (_shift0), \
230 .width = (_width), \
231 }, \
232 .ph1 = { \
233 .reg_off = (_reg), \
234 .shift = (_shift1), \
235 .width = (_width), \
236 }, \
237 .ph2 = { \
238 .reg_off = (_reg), \
239 .shift = (_shift2), \
240 .width = (_width), \
241 }, \
242 }, \
243 .hw.init = &(struct clk_init_data) { \
244 .name = "axg_"#_name, \
245 .ops = &meson_clk_triphase_ops, \
246 .parent_names = (const char *[]) { _pname }, \
247 .num_parents = 1, \
248 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
249 }, \
250}
251
252#define AXG_MST_SCLK(_name, _reg) \
253 AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
254 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
255
256static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
257static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
258static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
259static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
260static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
261static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
262
263#define AXG_MST_LRCLK_DIV(_name, _reg) \
264 AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
265 "axg_mst_"#_name"_sclk_post_en", 0) \
266
267static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
268static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
269static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
270static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
271static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
272static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
273
274#define AXG_MST_LRCLK(_name, _reg) \
275 AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
276 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
277
278static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
279static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
280static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
281static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
282static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
283static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
284
285static const char * const tdm_sclk_parent_names[] = {
286 "axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk",
287 "axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk",
288 "axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2",
289 "axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5",
290 "axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8",
291 "axg_slv_sclk9"
292};
293
294#define AXG_TDM_SCLK_MUX(_name, _reg) \
295 AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
296 CLK_MUX_ROUND_CLOSEST, \
297 tdm_sclk_parent_names, 0)
298
299static AXG_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
300static AXG_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
301static AXG_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
302static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
303static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
304static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
305static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
306
307#define AXG_TDM_SCLK_PRE_EN(_name, _reg) \
308 AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
309 "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
310
311static AXG_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
312static AXG_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
313static AXG_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
314static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
315static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
316static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
317static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
318
319#define AXG_TDM_SCLK_POST_EN(_name, _reg) \
320 AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
321 "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
322
323static AXG_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
324static AXG_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
325static AXG_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
326static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
327static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
328static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
329static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
330
331#define AXG_TDM_SCLK(_name, _reg) \
332 struct clk_regmap axg_tdm##_name##_sclk = { \
333 .data = &(struct meson_clk_phase_data) { \
334 .ph = { \
335 .reg_off = (_reg), \
336 .shift = 29, \
337 .width = 1, \
338 }, \
339 }, \
340 .hw.init = &(struct clk_init_data) { \
341 .name = "axg_tdm"#_name"_sclk", \
342 .ops = &meson_clk_phase_ops, \
343 .parent_names = (const char *[]) \
344 { "axg_tdm"#_name"_sclk_post_en" }, \
345 .num_parents = 1, \
346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
347 }, \
348}
349
350static AXG_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
351static AXG_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
352static AXG_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
353static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
354static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
355static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
356static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
357
358static const char * const tdm_lrclk_parent_names[] = {
359 "axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk",
360 "axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk",
361 "axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2",
362 "axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5",
363 "axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8",
364 "axg_slv_lrclk9"
365};
366
367#define AXG_TDM_LRLCK(_name, _reg) \
368 AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
369 CLK_MUX_ROUND_CLOSEST, \
370 tdm_lrclk_parent_names, 0)
371
372static AXG_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
373static AXG_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
374static AXG_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
375static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
376static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
377static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
378static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
379
380
381
382
383
384static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
385 .hws = {
386 [AUD_CLKID_DDR_ARB] = &axg_ddr_arb.hw,
387 [AUD_CLKID_PDM] = &axg_pdm.hw,
388 [AUD_CLKID_TDMIN_A] = &axg_tdmin_a.hw,
389 [AUD_CLKID_TDMIN_B] = &axg_tdmin_b.hw,
390 [AUD_CLKID_TDMIN_C] = &axg_tdmin_c.hw,
391 [AUD_CLKID_TDMIN_LB] = &axg_tdmin_lb.hw,
392 [AUD_CLKID_TDMOUT_A] = &axg_tdmout_a.hw,
393 [AUD_CLKID_TDMOUT_B] = &axg_tdmout_b.hw,
394 [AUD_CLKID_TDMOUT_C] = &axg_tdmout_c.hw,
395 [AUD_CLKID_FRDDR_A] = &axg_frddr_a.hw,
396 [AUD_CLKID_FRDDR_B] = &axg_frddr_b.hw,
397 [AUD_CLKID_FRDDR_C] = &axg_frddr_c.hw,
398 [AUD_CLKID_TODDR_A] = &axg_toddr_a.hw,
399 [AUD_CLKID_TODDR_B] = &axg_toddr_b.hw,
400 [AUD_CLKID_TODDR_C] = &axg_toddr_c.hw,
401 [AUD_CLKID_LOOPBACK] = &axg_loopback.hw,
402 [AUD_CLKID_SPDIFIN] = &axg_spdifin.hw,
403 [AUD_CLKID_SPDIFOUT] = &axg_spdifout.hw,
404 [AUD_CLKID_RESAMPLE] = &axg_resample.hw,
405 [AUD_CLKID_POWER_DETECT] = &axg_power_detect.hw,
406 [AUD_CLKID_MST_A_MCLK_SEL] = &axg_mst_a_mclk_sel.hw,
407 [AUD_CLKID_MST_B_MCLK_SEL] = &axg_mst_b_mclk_sel.hw,
408 [AUD_CLKID_MST_C_MCLK_SEL] = &axg_mst_c_mclk_sel.hw,
409 [AUD_CLKID_MST_D_MCLK_SEL] = &axg_mst_d_mclk_sel.hw,
410 [AUD_CLKID_MST_E_MCLK_SEL] = &axg_mst_e_mclk_sel.hw,
411 [AUD_CLKID_MST_F_MCLK_SEL] = &axg_mst_f_mclk_sel.hw,
412 [AUD_CLKID_MST_A_MCLK_DIV] = &axg_mst_a_mclk_div.hw,
413 [AUD_CLKID_MST_B_MCLK_DIV] = &axg_mst_b_mclk_div.hw,
414 [AUD_CLKID_MST_C_MCLK_DIV] = &axg_mst_c_mclk_div.hw,
415 [AUD_CLKID_MST_D_MCLK_DIV] = &axg_mst_d_mclk_div.hw,
416 [AUD_CLKID_MST_E_MCLK_DIV] = &axg_mst_e_mclk_div.hw,
417 [AUD_CLKID_MST_F_MCLK_DIV] = &axg_mst_f_mclk_div.hw,
418 [AUD_CLKID_MST_A_MCLK] = &axg_mst_a_mclk.hw,
419 [AUD_CLKID_MST_B_MCLK] = &axg_mst_b_mclk.hw,
420 [AUD_CLKID_MST_C_MCLK] = &axg_mst_c_mclk.hw,
421 [AUD_CLKID_MST_D_MCLK] = &axg_mst_d_mclk.hw,
422 [AUD_CLKID_MST_E_MCLK] = &axg_mst_e_mclk.hw,
423 [AUD_CLKID_MST_F_MCLK] = &axg_mst_f_mclk.hw,
424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &axg_spdifout_clk_sel.hw,
425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &axg_spdifout_clk_div.hw,
426 [AUD_CLKID_SPDIFOUT_CLK] = &axg_spdifout_clk.hw,
427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &axg_spdifin_clk_sel.hw,
428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &axg_spdifin_clk_div.hw,
429 [AUD_CLKID_SPDIFIN_CLK] = &axg_spdifin_clk.hw,
430 [AUD_CLKID_PDM_DCLK_SEL] = &axg_pdm_dclk_sel.hw,
431 [AUD_CLKID_PDM_DCLK_DIV] = &axg_pdm_dclk_div.hw,
432 [AUD_CLKID_PDM_DCLK] = &axg_pdm_dclk.hw,
433 [AUD_CLKID_PDM_SYSCLK_SEL] = &axg_pdm_sysclk_sel.hw,
434 [AUD_CLKID_PDM_SYSCLK_DIV] = &axg_pdm_sysclk_div.hw,
435 [AUD_CLKID_PDM_SYSCLK] = &axg_pdm_sysclk.hw,
436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &axg_mst_a_sclk_pre_en.hw,
437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &axg_mst_b_sclk_pre_en.hw,
438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &axg_mst_c_sclk_pre_en.hw,
439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &axg_mst_d_sclk_pre_en.hw,
440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &axg_mst_e_sclk_pre_en.hw,
441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &axg_mst_f_sclk_pre_en.hw,
442 [AUD_CLKID_MST_A_SCLK_DIV] = &axg_mst_a_sclk_div.hw,
443 [AUD_CLKID_MST_B_SCLK_DIV] = &axg_mst_b_sclk_div.hw,
444 [AUD_CLKID_MST_C_SCLK_DIV] = &axg_mst_c_sclk_div.hw,
445 [AUD_CLKID_MST_D_SCLK_DIV] = &axg_mst_d_sclk_div.hw,
446 [AUD_CLKID_MST_E_SCLK_DIV] = &axg_mst_e_sclk_div.hw,
447 [AUD_CLKID_MST_F_SCLK_DIV] = &axg_mst_f_sclk_div.hw,
448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &axg_mst_a_sclk_post_en.hw,
449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &axg_mst_b_sclk_post_en.hw,
450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &axg_mst_c_sclk_post_en.hw,
451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &axg_mst_d_sclk_post_en.hw,
452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &axg_mst_e_sclk_post_en.hw,
453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &axg_mst_f_sclk_post_en.hw,
454 [AUD_CLKID_MST_A_SCLK] = &axg_mst_a_sclk.hw,
455 [AUD_CLKID_MST_B_SCLK] = &axg_mst_b_sclk.hw,
456 [AUD_CLKID_MST_C_SCLK] = &axg_mst_c_sclk.hw,
457 [AUD_CLKID_MST_D_SCLK] = &axg_mst_d_sclk.hw,
458 [AUD_CLKID_MST_E_SCLK] = &axg_mst_e_sclk.hw,
459 [AUD_CLKID_MST_F_SCLK] = &axg_mst_f_sclk.hw,
460 [AUD_CLKID_MST_A_LRCLK_DIV] = &axg_mst_a_lrclk_div.hw,
461 [AUD_CLKID_MST_B_LRCLK_DIV] = &axg_mst_b_lrclk_div.hw,
462 [AUD_CLKID_MST_C_LRCLK_DIV] = &axg_mst_c_lrclk_div.hw,
463 [AUD_CLKID_MST_D_LRCLK_DIV] = &axg_mst_d_lrclk_div.hw,
464 [AUD_CLKID_MST_E_LRCLK_DIV] = &axg_mst_e_lrclk_div.hw,
465 [AUD_CLKID_MST_F_LRCLK_DIV] = &axg_mst_f_lrclk_div.hw,
466 [AUD_CLKID_MST_A_LRCLK] = &axg_mst_a_lrclk.hw,
467 [AUD_CLKID_MST_B_LRCLK] = &axg_mst_b_lrclk.hw,
468 [AUD_CLKID_MST_C_LRCLK] = &axg_mst_c_lrclk.hw,
469 [AUD_CLKID_MST_D_LRCLK] = &axg_mst_d_lrclk.hw,
470 [AUD_CLKID_MST_E_LRCLK] = &axg_mst_e_lrclk.hw,
471 [AUD_CLKID_MST_F_LRCLK] = &axg_mst_f_lrclk.hw,
472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &axg_tdmin_a_sclk_sel.hw,
473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &axg_tdmin_b_sclk_sel.hw,
474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &axg_tdmin_c_sclk_sel.hw,
475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &axg_tdmin_lb_sclk_sel.hw,
476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &axg_tdmout_a_sclk_sel.hw,
477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &axg_tdmout_b_sclk_sel.hw,
478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &axg_tdmout_c_sclk_sel.hw,
479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &axg_tdmin_a_sclk_pre_en.hw,
480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &axg_tdmin_b_sclk_pre_en.hw,
481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &axg_tdmin_c_sclk_pre_en.hw,
482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw,
483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw,
484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw,
485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw,
486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw,
487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw,
488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw,
489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw,
490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw,
491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw,
492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw,
493 [AUD_CLKID_TDMIN_A_SCLK] = &axg_tdmin_a_sclk.hw,
494 [AUD_CLKID_TDMIN_B_SCLK] = &axg_tdmin_b_sclk.hw,
495 [AUD_CLKID_TDMIN_C_SCLK] = &axg_tdmin_c_sclk.hw,
496 [AUD_CLKID_TDMIN_LB_SCLK] = &axg_tdmin_lb_sclk.hw,
497 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
498 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
499 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
500 [AUD_CLKID_TDMIN_A_LRCLK] = &axg_tdmin_a_lrclk.hw,
501 [AUD_CLKID_TDMIN_B_LRCLK] = &axg_tdmin_b_lrclk.hw,
502 [AUD_CLKID_TDMIN_C_LRCLK] = &axg_tdmin_c_lrclk.hw,
503 [AUD_CLKID_TDMIN_LB_LRCLK] = &axg_tdmin_lb_lrclk.hw,
504 [AUD_CLKID_TDMOUT_A_LRCLK] = &axg_tdmout_a_lrclk.hw,
505 [AUD_CLKID_TDMOUT_B_LRCLK] = &axg_tdmout_b_lrclk.hw,
506 [AUD_CLKID_TDMOUT_C_LRCLK] = &axg_tdmout_c_lrclk.hw,
507 [NR_CLKS] = NULL,
508 },
509 .num = NR_CLKS,
510};
511
512
513static struct clk_regmap *const axg_audio_clk_regmaps[] = {
514 &axg_ddr_arb,
515 &axg_pdm,
516 &axg_tdmin_a,
517 &axg_tdmin_b,
518 &axg_tdmin_c,
519 &axg_tdmin_lb,
520 &axg_tdmout_a,
521 &axg_tdmout_b,
522 &axg_tdmout_c,
523 &axg_frddr_a,
524 &axg_frddr_b,
525 &axg_frddr_c,
526 &axg_toddr_a,
527 &axg_toddr_b,
528 &axg_toddr_c,
529 &axg_loopback,
530 &axg_spdifin,
531 &axg_spdifout,
532 &axg_resample,
533 &axg_power_detect,
534 &axg_mst_a_mclk_sel,
535 &axg_mst_b_mclk_sel,
536 &axg_mst_c_mclk_sel,
537 &axg_mst_d_mclk_sel,
538 &axg_mst_e_mclk_sel,
539 &axg_mst_f_mclk_sel,
540 &axg_mst_a_mclk_div,
541 &axg_mst_b_mclk_div,
542 &axg_mst_c_mclk_div,
543 &axg_mst_d_mclk_div,
544 &axg_mst_e_mclk_div,
545 &axg_mst_f_mclk_div,
546 &axg_mst_a_mclk,
547 &axg_mst_b_mclk,
548 &axg_mst_c_mclk,
549 &axg_mst_d_mclk,
550 &axg_mst_e_mclk,
551 &axg_mst_f_mclk,
552 &axg_spdifout_clk_sel,
553 &axg_spdifout_clk_div,
554 &axg_spdifout_clk,
555 &axg_spdifin_clk_sel,
556 &axg_spdifin_clk_div,
557 &axg_spdifin_clk,
558 &axg_pdm_dclk_sel,
559 &axg_pdm_dclk_div,
560 &axg_pdm_dclk,
561 &axg_pdm_sysclk_sel,
562 &axg_pdm_sysclk_div,
563 &axg_pdm_sysclk,
564 &axg_mst_a_sclk_pre_en,
565 &axg_mst_b_sclk_pre_en,
566 &axg_mst_c_sclk_pre_en,
567 &axg_mst_d_sclk_pre_en,
568 &axg_mst_e_sclk_pre_en,
569 &axg_mst_f_sclk_pre_en,
570 &axg_mst_a_sclk_div,
571 &axg_mst_b_sclk_div,
572 &axg_mst_c_sclk_div,
573 &axg_mst_d_sclk_div,
574 &axg_mst_e_sclk_div,
575 &axg_mst_f_sclk_div,
576 &axg_mst_a_sclk_post_en,
577 &axg_mst_b_sclk_post_en,
578 &axg_mst_c_sclk_post_en,
579 &axg_mst_d_sclk_post_en,
580 &axg_mst_e_sclk_post_en,
581 &axg_mst_f_sclk_post_en,
582 &axg_mst_a_sclk,
583 &axg_mst_b_sclk,
584 &axg_mst_c_sclk,
585 &axg_mst_d_sclk,
586 &axg_mst_e_sclk,
587 &axg_mst_f_sclk,
588 &axg_mst_a_lrclk_div,
589 &axg_mst_b_lrclk_div,
590 &axg_mst_c_lrclk_div,
591 &axg_mst_d_lrclk_div,
592 &axg_mst_e_lrclk_div,
593 &axg_mst_f_lrclk_div,
594 &axg_mst_a_lrclk,
595 &axg_mst_b_lrclk,
596 &axg_mst_c_lrclk,
597 &axg_mst_d_lrclk,
598 &axg_mst_e_lrclk,
599 &axg_mst_f_lrclk,
600 &axg_tdmin_a_sclk_sel,
601 &axg_tdmin_b_sclk_sel,
602 &axg_tdmin_c_sclk_sel,
603 &axg_tdmin_lb_sclk_sel,
604 &axg_tdmout_a_sclk_sel,
605 &axg_tdmout_b_sclk_sel,
606 &axg_tdmout_c_sclk_sel,
607 &axg_tdmin_a_sclk_pre_en,
608 &axg_tdmin_b_sclk_pre_en,
609 &axg_tdmin_c_sclk_pre_en,
610 &axg_tdmin_lb_sclk_pre_en,
611 &axg_tdmout_a_sclk_pre_en,
612 &axg_tdmout_b_sclk_pre_en,
613 &axg_tdmout_c_sclk_pre_en,
614 &axg_tdmin_a_sclk_post_en,
615 &axg_tdmin_b_sclk_post_en,
616 &axg_tdmin_c_sclk_post_en,
617 &axg_tdmin_lb_sclk_post_en,
618 &axg_tdmout_a_sclk_post_en,
619 &axg_tdmout_b_sclk_post_en,
620 &axg_tdmout_c_sclk_post_en,
621 &axg_tdmin_a_sclk,
622 &axg_tdmin_b_sclk,
623 &axg_tdmin_c_sclk,
624 &axg_tdmin_lb_sclk,
625 &axg_tdmout_a_sclk,
626 &axg_tdmout_b_sclk,
627 &axg_tdmout_c_sclk,
628 &axg_tdmin_a_lrclk,
629 &axg_tdmin_b_lrclk,
630 &axg_tdmin_c_lrclk,
631 &axg_tdmin_lb_lrclk,
632 &axg_tdmout_a_lrclk,
633 &axg_tdmout_b_lrclk,
634 &axg_tdmout_c_lrclk,
635};
636
637static int devm_clk_get_enable(struct device *dev, char *id)
638{
639 struct clk *clk;
640 int ret;
641
642 clk = devm_clk_get(dev, id);
643 if (IS_ERR(clk)) {
644 ret = PTR_ERR(clk);
645 if (ret != -EPROBE_DEFER)
646 dev_err(dev, "failed to get %s", id);
647 return ret;
648 }
649
650 ret = clk_prepare_enable(clk);
651 if (ret) {
652 dev_err(dev, "failed to enable %s", id);
653 return ret;
654 }
655
656 ret = devm_add_action_or_reset(dev,
657 (void(*)(void *))clk_disable_unprepare,
658 clk);
659 if (ret) {
660 dev_err(dev, "failed to add reset action on %s", id);
661 return ret;
662 }
663
664 return 0;
665}
666
667static int axg_register_clk_hw_input(struct device *dev,
668 const char *name,
669 unsigned int clkid)
670{
671 char *clk_name;
672 struct clk_hw *hw;
673 int err = 0;
674
675 clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
676 if (!clk_name)
677 return -ENOMEM;
678
679 hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
680 if (IS_ERR(hw)) {
681
682 if (PTR_ERR(hw) == -ENOENT) {
683 dev_dbg(dev, "%s not provided", name);
684 } else {
685 err = PTR_ERR(hw);
686 if (err != -EPROBE_DEFER)
687 dev_err(dev, "failed to get %s clock", name);
688 }
689 } else {
690 axg_audio_hw_onecell_data.hws[clkid] = hw;
691 }
692
693 kfree(clk_name);
694 return err;
695}
696
697static int axg_register_clk_hw_inputs(struct device *dev,
698 const char *basename,
699 unsigned int count,
700 unsigned int clkid)
701{
702 char *name;
703 int i, ret;
704
705 for (i = 0; i < count; i++) {
706 name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
707 if (!name)
708 return -ENOMEM;
709
710 ret = axg_register_clk_hw_input(dev, name, clkid + i);
711 kfree(name);
712 if (ret)
713 return ret;
714 }
715
716 return 0;
717}
718
719static const struct regmap_config axg_audio_regmap_cfg = {
720 .reg_bits = 32,
721 .val_bits = 32,
722 .reg_stride = 4,
723 .max_register = AUDIO_CLK_PDMIN_CTRL1,
724};
725
726static int axg_audio_clkc_probe(struct platform_device *pdev)
727{
728 struct device *dev = &pdev->dev;
729 struct regmap *map;
730 struct resource *res;
731 void __iomem *regs;
732 struct clk_hw *hw;
733 int ret, i;
734
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 regs = devm_ioremap_resource(dev, res);
737 if (IS_ERR(regs))
738 return PTR_ERR(regs);
739
740 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
741 if (IS_ERR(map)) {
742 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
743 return PTR_ERR(map);
744 }
745
746
747 ret = devm_clk_get_enable(dev, "pclk");
748 if (ret)
749 return ret;
750
751 ret = device_reset(dev);
752 if (ret) {
753 dev_err(dev, "failed to reset device\n");
754 return ret;
755 }
756
757
758 hw = meson_clk_hw_register_input(dev, "pclk", "axg_audio_pclk", 0);
759 if (IS_ERR(hw))
760 return PTR_ERR(hw);
761
762 axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
763
764
765 ret = axg_register_clk_hw_inputs(dev, "mst_in",
766 AXG_MST_IN_COUNT,
767 AUD_CLKID_MST0);
768 if (ret)
769 return ret;
770
771
772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
773 AXG_SLV_SCLK_COUNT,
774 AUD_CLKID_SLV_SCLK0);
775 if (ret)
776 return ret;
777
778
779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
780 AXG_SLV_LRCLK_COUNT,
781 AUD_CLKID_SLV_LRCLK0);
782 if (ret)
783 return ret;
784
785
786 for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++)
787 axg_audio_clk_regmaps[i]->map = map;
788
789
790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
791 hw = axg_audio_hw_onecell_data.hws[i];
792
793 if (!hw)
794 continue;
795
796 ret = devm_clk_hw_register(dev, hw);
797 if (ret) {
798 dev_err(dev, "failed to register clock %s\n",
799 hw->init->name);
800 return ret;
801 }
802 }
803
804 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
805 &axg_audio_hw_onecell_data);
806}
807
808static const struct of_device_id clkc_match_table[] = {
809 { .compatible = "amlogic,axg-audio-clkc" },
810 {}
811};
812MODULE_DEVICE_TABLE(of, clkc_match_table);
813
814static struct platform_driver axg_audio_driver = {
815 .probe = axg_audio_clkc_probe,
816 .driver = {
817 .name = "axg-audio-clkc",
818 .of_match_table = clkc_match_table,
819 },
820};
821module_platform_driver(axg_audio_driver);
822
823MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
824MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
825MODULE_LICENSE("GPL v2");
826
