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12#include <linux/edac.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_platform.h>
20#include <linux/types.h>
21
22#include <asm/dcr.h>
23
24#include "edac_module.h"
25#include "ppc4xx_edac.h"
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110
111#define EDAC_OPSTATE_INT_STR "interrupt"
112#define EDAC_OPSTATE_POLL_STR "polled"
113#define EDAC_OPSTATE_UNKNOWN_STR "unknown"
114
115#define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
116#define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
117
118#define PPC4XX_EDAC_MESSAGE_SIZE 256
119
120
121
122
123#define ppc4xx_edac_printk(level, fmt, arg...) \
124 edac_printk(level, "PPC4xx MC", fmt, ##arg)
125
126
127
128
129#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
130 edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
131
132
133
134
135
136#define SDRAM_MBCF_SZ_MiB_MIN 4
137#define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
138 << (SDRAM_MBCF_SZ_DECODE(n)))
139#define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
140 << (20 - PAGE_SHIFT + \
141 SDRAM_MBCF_SZ_DECODE(n)))
142
143
144
145
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147
148
149
150#define SDRAM_DCR_RESOURCE_LEN 2
151#define SDRAM_DCR_ADDR_OFFSET 0
152#define SDRAM_DCR_DATA_OFFSET 1
153
154
155
156
157#define INTMAP_ECCDED_INDEX 0
158#define INTMAP_ECCSEC_INDEX 1
159
160
161
162
163
164
165struct ppc4xx_edac_pdata {
166 dcr_host_t dcr_host;
167 struct {
168 int sec;
169 int ded;
170 } irqs;
171};
172
173
174
175
176
177struct ppc4xx_ecc_status {
178 u32 ecces;
179 u32 besr;
180 u32 bearh;
181 u32 bearl;
182 u32 wmirq;
183};
184
185
186
187static int ppc4xx_edac_probe(struct platform_device *device);
188static int ppc4xx_edac_remove(struct platform_device *device);
189
190
191
192
193
194
195
196static const struct of_device_id ppc4xx_edac_match[] = {
197 {
198 .compatible = "ibm,sdram-4xx-ddr2"
199 },
200 { }
201};
202MODULE_DEVICE_TABLE(of, ppc4xx_edac_match);
203
204static struct platform_driver ppc4xx_edac_driver = {
205 .probe = ppc4xx_edac_probe,
206 .remove = ppc4xx_edac_remove,
207 .driver = {
208 .name = PPC4XX_EDAC_MODULE_NAME,
209 .of_match_table = ppc4xx_edac_match,
210 },
211};
212
213
214
215
216
217static const unsigned ppc4xx_edac_nr_csrows = 2;
218static const unsigned ppc4xx_edac_nr_chans = 1;
219
220
221
222
223
224static const char * const ppc4xx_plb_masters[9] = {
225 [SDRAM_PLB_M0ID_ICU] = "ICU",
226 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
227 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
228 [SDRAM_PLB_M0ID_DMA] = "DMA",
229 [SDRAM_PLB_M0ID_DCU] = "DCU",
230 [SDRAM_PLB_M0ID_OPB] = "OPB",
231 [SDRAM_PLB_M0ID_MAL] = "MAL",
232 [SDRAM_PLB_M0ID_SEC] = "SEC",
233 [SDRAM_PLB_M0ID_AHB] = "AHB"
234};
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244
245
246static inline u32
247mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
248{
249 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
250 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
251 idcr_n);
252}
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261
262
263static inline void
264mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
265{
266 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
267 dcr_host->base + SDRAM_DCR_DATA_OFFSET,
268 idcr_n,
269 value);
270}
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282
283
284static bool
285ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
286 unsigned int bank)
287{
288 switch (bank) {
289 case 0:
290 return status->ecces & SDRAM_ECCES_BK0ER;
291 case 1:
292 return status->ecces & SDRAM_ECCES_BK1ER;
293 default:
294 return false;
295 }
296}
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314
315static int
316ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
317 const struct ppc4xx_ecc_status *status,
318 char *buffer,
319 size_t size)
320{
321 int n, total = 0;
322 unsigned int row, rows;
323
324 n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
325
326 if (n < 0 || n >= size)
327 goto fail;
328
329 buffer += n;
330 size -= n;
331 total += n;
332
333 for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
334 if (ppc4xx_edac_check_bank_error(status, row)) {
335 n = snprintf(buffer, size, "%s%u",
336 (rows++ ? ", " : ""), row);
337
338 if (n < 0 || n >= size)
339 goto fail;
340
341 buffer += n;
342 size -= n;
343 total += n;
344 }
345 }
346
347 n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
348
349 if (n < 0 || n >= size)
350 goto fail;
351
352 buffer += n;
353 size -= n;
354 total += n;
355
356 fail:
357 return total;
358}
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376
377static int
378ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
379 const struct ppc4xx_ecc_status *status,
380 char *buffer,
381 size_t size)
382{
383 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
384 const char *ckber = NULL;
385
386 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
387 case SDRAM_ECCES_CKBER_NONE:
388 ckber = "None";
389 break;
390 case SDRAM_ECCES_CKBER_32_ECC_0_3:
391 ckber = "ECC0:3";
392 break;
393 case SDRAM_ECCES_CKBER_32_ECC_4_8:
394 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
395 SDRAM_MCOPT1_WDTH_MASK) {
396 case SDRAM_MCOPT1_WDTH_16:
397 ckber = "ECC0:3";
398 break;
399 case SDRAM_MCOPT1_WDTH_32:
400 ckber = "ECC4:8";
401 break;
402 default:
403 ckber = "Unknown";
404 break;
405 }
406 break;
407 case SDRAM_ECCES_CKBER_32_ECC_0_8:
408 ckber = "ECC0:8";
409 break;
410 default:
411 ckber = "Unknown";
412 break;
413 }
414
415 return snprintf(buffer, size, "Checkbit Error: %s", ckber);
416}
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434
435static int
436ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
437 const struct ppc4xx_ecc_status *status,
438 char *buffer,
439 size_t size)
440{
441 int n, total = 0;
442 unsigned int lane, lanes;
443 const unsigned int first_lane = 0;
444 const unsigned int lane_count = 16;
445
446 n = snprintf(buffer, size, "; Byte Lane Errors: ");
447
448 if (n < 0 || n >= size)
449 goto fail;
450
451 buffer += n;
452 size -= n;
453 total += n;
454
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
456 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
457 n = snprintf(buffer, size,
458 "%s%u",
459 (lanes++ ? ", " : ""), lane);
460
461 if (n < 0 || n >= size)
462 goto fail;
463
464 buffer += n;
465 size -= n;
466 total += n;
467 }
468 }
469
470 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
471
472 if (n < 0 || n >= size)
473 goto fail;
474
475 buffer += n;
476 size -= n;
477 total += n;
478
479 fail:
480 return total;
481}
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499
500static int
501ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
502 const struct ppc4xx_ecc_status *status,
503 char *buffer,
504 size_t size)
505{
506 int n, total = 0;
507
508 n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
509
510 if (n < 0 || n >= size)
511 goto fail;
512
513 buffer += n;
514 size -= n;
515 total += n;
516
517 n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
518
519 if (n < 0 || n >= size)
520 goto fail;
521
522 buffer += n;
523 size -= n;
524 total += n;
525
526 n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
527
528 if (n < 0 || n >= size)
529 goto fail;
530
531 buffer += n;
532 size -= n;
533 total += n;
534
535 fail:
536 return total;
537}
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555
556static int
557ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
558 const struct ppc4xx_ecc_status *status,
559 char *buffer,
560 size_t size)
561{
562 unsigned int master;
563 bool read;
564
565 if ((status->besr & SDRAM_BESR_MASK) == 0)
566 return 0;
567
568 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
569 return 0;
570
571 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
572
573 master = SDRAM_BESR_M0ID_DECODE(status->besr);
574
575 return snprintf(buffer, size,
576 "%s error w/ PLB master %u \"%s\"; ",
577 (read ? "Read" : "Write"),
578 master,
579 (((master >= SDRAM_PLB_M0ID_FIRST) &&
580 (master <= SDRAM_PLB_M0ID_LAST)) ?
581 ppc4xx_plb_masters[master] : "UNKNOWN"));
582}
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596
597static void
598ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
599 const struct ppc4xx_ecc_status *status,
600 char *buffer,
601 size_t size)
602{
603 int n;
604
605 if (buffer == NULL || size == 0)
606 return;
607
608 n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
609
610 if (n < 0 || n >= size)
611 return;
612
613 buffer += n;
614 size -= n;
615
616 ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
617}
618
619#ifdef DEBUG
620
621
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629
630static void
631ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
632 const struct ppc4xx_ecc_status *status)
633{
634 char message[PPC4XX_EDAC_MESSAGE_SIZE];
635
636 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
637
638 ppc4xx_edac_mc_printk(KERN_INFO, mci,
639 "\n"
640 "\tECCES: 0x%08x\n"
641 "\tWMIRQ: 0x%08x\n"
642 "\tBESR: 0x%08x\n"
643 "\tBEAR: 0x%08x%08x\n"
644 "\t%s\n",
645 status->ecces,
646 status->wmirq,
647 status->besr,
648 status->bearh,
649 status->bearl,
650 message);
651}
652#endif
653
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665
666
667static void
668ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
669 struct ppc4xx_ecc_status *status)
670{
671 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
672 const dcr_host_t *dcr_host = &pdata->dcr_host;
673
674 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
675 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
676 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
677 status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
678 status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
679}
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691
692static void
693ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
694 const struct ppc4xx_ecc_status *status)
695{
696 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
697 const dcr_host_t *dcr_host = &pdata->dcr_host;
698
699 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
700 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
701 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
702 mtsdram(dcr_host, SDRAM_BEARL, 0);
703 mtsdram(dcr_host, SDRAM_BEARH, 0);
704}
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718
719static void
720ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
721 const struct ppc4xx_ecc_status *status)
722{
723 int row;
724 char message[PPC4XX_EDAC_MESSAGE_SIZE];
725
726 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
727
728 for (row = 0; row < mci->nr_csrows; row++)
729 if (ppc4xx_edac_check_bank_error(status, row))
730 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
731 0, 0, 0,
732 row, 0, -1,
733 message, "");
734}
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736
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741
742
743
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745
746
747static void
748ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
749 const struct ppc4xx_ecc_status *status)
750{
751 const u64 bear = ((u64)status->bearh << 32 | status->bearl);
752 const unsigned long page = bear >> PAGE_SHIFT;
753 const unsigned long offset = bear & ~PAGE_MASK;
754 int row;
755 char message[PPC4XX_EDAC_MESSAGE_SIZE];
756
757 ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
758
759 for (row = 0; row < mci->nr_csrows; row++)
760 if (ppc4xx_edac_check_bank_error(status, row))
761 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
762 page, offset, 0,
763 row, 0, -1,
764 message, "");
765}
766
767
768
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775
776
777static void
778ppc4xx_edac_check(struct mem_ctl_info *mci)
779{
780#ifdef DEBUG
781 static unsigned int count;
782#endif
783 struct ppc4xx_ecc_status status;
784
785 ppc4xx_ecc_get_status(mci, &status);
786
787#ifdef DEBUG
788 if (count++ % 30 == 0)
789 ppc4xx_ecc_dump_status(mci, &status);
790#endif
791
792 if (status.ecces & SDRAM_ECCES_UE)
793 ppc4xx_edac_handle_ue(mci, &status);
794
795 if (status.ecces & SDRAM_ECCES_CE)
796 ppc4xx_edac_handle_ce(mci, &status);
797
798 ppc4xx_ecc_clear_status(mci, &status);
799}
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811
812
813
814static irqreturn_t
815ppc4xx_edac_isr(int irq, void *dev_id)
816{
817 struct mem_ctl_info *mci = dev_id;
818
819 ppc4xx_edac_check(mci);
820
821 return IRQ_HANDLED;
822}
823
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840
841static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1)
842{
843 switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
844 case SDRAM_MCOPT1_WDTH_16:
845 return DEV_X2;
846 case SDRAM_MCOPT1_WDTH_32:
847 return DEV_X4;
848 default:
849 return DEV_UNKNOWN;
850 }
851}
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862
863
864static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1)
865{
866 bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
867
868 switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
869 case SDRAM_MCOPT1_DDR2_TYPE:
870 return rden ? MEM_RDDR2 : MEM_DDR2;
871 case SDRAM_MCOPT1_DDR1_TYPE:
872 return rden ? MEM_RDDR : MEM_DDR;
873 default:
874 return MEM_UNKNOWN;
875 }
876}
877
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893
894static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
895{
896 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
897 int status = 0;
898 enum mem_type mtype;
899 enum dev_type dtype;
900 enum edac_type edac_mode;
901 int row, j;
902 u32 mbxcf, size, nr_pages;
903
904
905
906 mtype = ppc4xx_edac_get_mtype(mcopt1);
907 dtype = ppc4xx_edac_get_dtype(mcopt1);
908
909
910
911 if (mci->edac_cap & EDAC_FLAG_SECDED)
912 edac_mode = EDAC_SECDED;
913 else if (mci->edac_cap & EDAC_FLAG_EC)
914 edac_mode = EDAC_EC;
915 else
916 edac_mode = EDAC_NONE;
917
918
919
920
921
922
923 for (row = 0; row < mci->nr_csrows; row++) {
924 struct csrow_info *csi = mci->csrows[row];
925
926
927
928
929
930
931 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
932
933 if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
934 continue;
935
936
937
938 size = mbxcf & SDRAM_MBCF_SZ_MASK;
939
940 switch (size) {
941 case SDRAM_MBCF_SZ_4MB:
942 case SDRAM_MBCF_SZ_8MB:
943 case SDRAM_MBCF_SZ_16MB:
944 case SDRAM_MBCF_SZ_32MB:
945 case SDRAM_MBCF_SZ_64MB:
946 case SDRAM_MBCF_SZ_128MB:
947 case SDRAM_MBCF_SZ_256MB:
948 case SDRAM_MBCF_SZ_512MB:
949 case SDRAM_MBCF_SZ_1GB:
950 case SDRAM_MBCF_SZ_2GB:
951 case SDRAM_MBCF_SZ_4GB:
952 case SDRAM_MBCF_SZ_8GB:
953 nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
954 break;
955 default:
956 ppc4xx_edac_mc_printk(KERN_ERR, mci,
957 "Unrecognized memory bank %d "
958 "size 0x%08x\n",
959 row, SDRAM_MBCF_SZ_DECODE(size));
960 status = -EINVAL;
961 goto done;
962 }
963
964
965
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972
973
974
975
976 for (j = 0; j < csi->nr_channels; j++) {
977 struct dimm_info *dimm = csi->channels[j]->dimm;
978
979 dimm->nr_pages = nr_pages / csi->nr_channels;
980 dimm->grain = 1;
981
982 dimm->mtype = mtype;
983 dimm->dtype = dtype;
984
985 dimm->edac_mode = edac_mode;
986 }
987 }
988
989 done:
990 return status;
991}
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1010
1011static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
1012 struct platform_device *op,
1013 const dcr_host_t *dcr_host, u32 mcopt1)
1014{
1015 int status = 0;
1016 const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1017 struct ppc4xx_edac_pdata *pdata = NULL;
1018 const struct device_node *np = op->dev.of_node;
1019
1020 if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
1021 return -EINVAL;
1022
1023
1024
1025 mci->pdev = &op->dev;
1026
1027 dev_set_drvdata(mci->pdev, mci);
1028
1029 pdata = mci->pvt_info;
1030
1031 pdata->dcr_host = *dcr_host;
1032
1033
1034
1035 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1036 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1037
1038 mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1039 EDAC_FLAG_EC |
1040 EDAC_FLAG_SECDED);
1041
1042 mci->scrub_cap = SCRUB_NONE;
1043 mci->scrub_mode = SCRUB_NONE;
1044
1045
1046
1047
1048
1049
1050 switch (memcheck) {
1051 case SDRAM_MCOPT1_MCHK_CHK:
1052 mci->edac_cap = EDAC_FLAG_EC;
1053 break;
1054 case SDRAM_MCOPT1_MCHK_CHK_REP:
1055 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1056 mci->scrub_mode = SCRUB_SW_SRC;
1057 break;
1058 default:
1059 mci->edac_cap = EDAC_FLAG_NONE;
1060 break;
1061 }
1062
1063
1064
1065 mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1066 mci->ctl_name = ppc4xx_edac_match->compatible,
1067 mci->dev_name = np->full_name;
1068
1069
1070
1071 mci->edac_check = ppc4xx_edac_check;
1072 mci->ctl_page_to_phys = NULL;
1073
1074
1075
1076 status = ppc4xx_edac_init_csrows(mci, mcopt1);
1077
1078 if (status)
1079 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1080 "Failed to initialize rows!\n");
1081
1082 return status;
1083}
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100static int ppc4xx_edac_register_irq(struct platform_device *op,
1101 struct mem_ctl_info *mci)
1102{
1103 int status = 0;
1104 int ded_irq, sec_irq;
1105 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1106 struct device_node *np = op->dev.of_node;
1107
1108 ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1109 sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1110
1111 if (!ded_irq || !sec_irq) {
1112 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1113 "Unable to map interrupts.\n");
1114 status = -ENODEV;
1115 goto fail;
1116 }
1117
1118 status = request_irq(ded_irq,
1119 ppc4xx_edac_isr,
1120 0,
1121 "[EDAC] MC ECCDED",
1122 mci);
1123
1124 if (status < 0) {
1125 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1126 "Unable to request irq %d for ECC DED",
1127 ded_irq);
1128 status = -ENODEV;
1129 goto fail1;
1130 }
1131
1132 status = request_irq(sec_irq,
1133 ppc4xx_edac_isr,
1134 0,
1135 "[EDAC] MC ECCSEC",
1136 mci);
1137
1138 if (status < 0) {
1139 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1140 "Unable to request irq %d for ECC SEC",
1141 sec_irq);
1142 status = -ENODEV;
1143 goto fail2;
1144 }
1145
1146 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1147 ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1148
1149 pdata->irqs.ded = ded_irq;
1150 pdata->irqs.sec = sec_irq;
1151
1152 return 0;
1153
1154 fail2:
1155 free_irq(sec_irq, mci);
1156
1157 fail1:
1158 free_irq(ded_irq, mci);
1159
1160 fail:
1161 return status;
1162}
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178static int ppc4xx_edac_map_dcrs(const struct device_node *np,
1179 dcr_host_t *dcr_host)
1180{
1181 unsigned int dcr_base, dcr_len;
1182
1183 if (np == NULL || dcr_host == NULL)
1184 return -EINVAL;
1185
1186
1187
1188 dcr_base = dcr_resource_start(np, 0);
1189 dcr_len = dcr_resource_len(np, 0);
1190
1191 if (dcr_base == 0 || dcr_len == 0) {
1192 ppc4xx_edac_printk(KERN_ERR,
1193 "Failed to obtain DCR property.\n");
1194 return -ENODEV;
1195 }
1196
1197 if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1198 ppc4xx_edac_printk(KERN_ERR,
1199 "Unexpected DCR length %d, expected %d.\n",
1200 dcr_len, SDRAM_DCR_RESOURCE_LEN);
1201 return -ENODEV;
1202 }
1203
1204
1205
1206 *dcr_host = dcr_map(np, dcr_base, dcr_len);
1207
1208 if (!DCR_MAP_OK(*dcr_host)) {
1209 ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1210 return -ENODEV;
1211 }
1212
1213 return 0;
1214}
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227static int ppc4xx_edac_probe(struct platform_device *op)
1228{
1229 int status = 0;
1230 u32 mcopt1, memcheck;
1231 dcr_host_t dcr_host;
1232 const struct device_node *np = op->dev.of_node;
1233 struct mem_ctl_info *mci = NULL;
1234 struct edac_mc_layer layers[2];
1235 static int ppc4xx_edac_instance;
1236
1237
1238
1239
1240
1241
1242 if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1243 !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1244 ppc4xx_edac_printk(KERN_NOTICE,
1245 "Only the PPC405EX[r] is supported.\n");
1246 return -ENODEV;
1247 }
1248
1249
1250
1251
1252
1253
1254 status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1255
1256 if (status)
1257 return status;
1258
1259
1260
1261
1262
1263
1264
1265 mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1266 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1267
1268 if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1269 ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or "
1270 "ECC is disabled.\n", np);
1271 status = -ENODEV;
1272 goto done;
1273 }
1274
1275
1276
1277
1278
1279
1280 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1281 layers[0].size = ppc4xx_edac_nr_csrows;
1282 layers[0].is_virt_csrow = true;
1283 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1284 layers[1].size = ppc4xx_edac_nr_chans;
1285 layers[1].is_virt_csrow = false;
1286 mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
1287 sizeof(struct ppc4xx_edac_pdata));
1288 if (mci == NULL) {
1289 ppc4xx_edac_printk(KERN_ERR, "%pOF: "
1290 "Failed to allocate EDAC MC instance!\n",
1291 np);
1292 status = -ENOMEM;
1293 goto done;
1294 }
1295
1296 status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1297
1298 if (status) {
1299 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1300 "Failed to initialize instance!\n");
1301 goto fail;
1302 }
1303
1304
1305
1306
1307
1308
1309
1310 if (edac_mc_add_mc(mci)) {
1311 ppc4xx_edac_mc_printk(KERN_ERR, mci,
1312 "Failed to add instance!\n");
1313 status = -ENODEV;
1314 goto fail;
1315 }
1316
1317 if (edac_op_state == EDAC_OPSTATE_INT) {
1318 status = ppc4xx_edac_register_irq(op, mci);
1319
1320 if (status)
1321 goto fail1;
1322 }
1323
1324 ppc4xx_edac_instance++;
1325
1326 return 0;
1327
1328 fail1:
1329 edac_mc_del_mc(mci->pdev);
1330
1331 fail:
1332 edac_mc_free(mci);
1333
1334 done:
1335 return status;
1336}
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350static int
1351ppc4xx_edac_remove(struct platform_device *op)
1352{
1353 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1354 struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1355
1356 if (edac_op_state == EDAC_OPSTATE_INT) {
1357 free_irq(pdata->irqs.sec, mci);
1358 free_irq(pdata->irqs.ded, mci);
1359 }
1360
1361 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1362
1363 edac_mc_del_mc(mci->pdev);
1364 edac_mc_free(mci);
1365
1366 return 0;
1367}
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static inline void __init
1379ppc4xx_edac_opstate_init(void)
1380{
1381 switch (edac_op_state) {
1382 case EDAC_OPSTATE_POLL:
1383 case EDAC_OPSTATE_INT:
1384 break;
1385 default:
1386 edac_op_state = EDAC_OPSTATE_INT;
1387 break;
1388 }
1389
1390 ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1391 ((edac_op_state == EDAC_OPSTATE_POLL) ?
1392 EDAC_OPSTATE_POLL_STR :
1393 ((edac_op_state == EDAC_OPSTATE_INT) ?
1394 EDAC_OPSTATE_INT_STR :
1395 EDAC_OPSTATE_UNKNOWN_STR)));
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406static int __init
1407ppc4xx_edac_init(void)
1408{
1409 ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1410
1411 ppc4xx_edac_opstate_init();
1412
1413 return platform_driver_register(&ppc4xx_edac_driver);
1414}
1415
1416
1417
1418
1419
1420
1421
1422
1423static void __exit
1424ppc4xx_edac_exit(void)
1425{
1426 platform_driver_unregister(&ppc4xx_edac_driver);
1427}
1428
1429module_init(ppc4xx_edac_init);
1430module_exit(ppc4xx_edac_exit);
1431
1432MODULE_LICENSE("GPL v2");
1433MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1434MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1435module_param(edac_op_state, int, 0444);
1436MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1437 "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
1438