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26#ifndef __DAL_DCHUBBUB_H__
27#define __DAL_DCHUBBUB_H__
28
29
30enum dcc_control {
31 dcc_control__256_256_xxx,
32 dcc_control__128_128_xxx,
33 dcc_control__256_64_64,
34};
35
36enum segment_order {
37 segment_order__na,
38 segment_order__contiguous,
39 segment_order__non_contiguous,
40};
41
42struct dcn_hubbub_wm_set {
43 uint32_t wm_set;
44 uint32_t data_urgent;
45 uint32_t pte_meta_urgent;
46 uint32_t sr_enter;
47 uint32_t sr_exit;
48 uint32_t dram_clk_chanage;
49};
50
51struct dcn_hubbub_wm {
52 struct dcn_hubbub_wm_set sets[4];
53};
54
55struct hubbub_funcs {
56 void (*update_dchub)(
57 struct hubbub *hubbub,
58 struct dchub_init_data *dh_data);
59
60 bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
61 const struct dc_dcc_surface_param *input,
62 struct dc_surface_dcc_cap *output);
63
64 bool (*dcc_support_swizzle)(
65 enum swizzle_mode_values swizzle,
66 unsigned int bytes_per_element,
67 enum segment_order *segment_order_horz,
68 enum segment_order *segment_order_vert);
69
70 bool (*dcc_support_pixel_format)(
71 enum surface_pixel_format format,
72 unsigned int *bytes_per_element);
73
74 void (*wm_read_state)(struct hubbub *hubbub,
75 struct dcn_hubbub_wm *wm);
76};
77
78struct hubbub {
79 const struct hubbub_funcs *funcs;
80 struct dc_context *ctx;
81};
82
83#endif
84