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8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/component.h>
11#include <linux/module.h>
12#include <linux/i2c.h>
13#include <linux/regmap.h>
14#include <linux/regulator/consumer.h>
15#include <linux/spinlock.h>
16#include <linux/videodev2.h>
17#include <drm/drmP.h>
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_fb_helper.h>
20#include <drm/drm_probe_helper.h>
21#include <video/imx-ipu-v3.h>
22
23#include "imx-drm.h"
24
25#define TVE_COM_CONF_REG 0x00
26#define TVE_TVDAC0_CONT_REG 0x28
27#define TVE_TVDAC1_CONT_REG 0x2c
28#define TVE_TVDAC2_CONT_REG 0x30
29#define TVE_CD_CONT_REG 0x34
30#define TVE_INT_CONT_REG 0x64
31#define TVE_STAT_REG 0x68
32#define TVE_TST_MODE_REG 0x6c
33#define TVE_MV_CONT_REG 0xdc
34
35
36#define TVE_SYNC_CH_2_EN BIT(22)
37#define TVE_SYNC_CH_1_EN BIT(21)
38#define TVE_SYNC_CH_0_EN BIT(20)
39#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
40#define TVE_TV_OUT_DISABLE (0x0 << 12)
41#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
42#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
43#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
44#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
45#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
46#define TVE_TV_OUT_YPBPR (0x6 << 12)
47#define TVE_TV_OUT_RGB (0x7 << 12)
48#define TVE_TV_STAND_MASK (0xf << 8)
49#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
50#define TVE_P2I_CONV_EN BIT(7)
51#define TVE_INP_VIDEO_FORM BIT(6)
52#define TVE_INP_YCBCR_422 (0x0 << 6)
53#define TVE_INP_YCBCR_444 (0x1 << 6)
54#define TVE_DATA_SOURCE_MASK (0x3 << 4)
55#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
56#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
57#define TVE_DATA_SOURCE_EXT (0x2 << 4)
58#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
59#define TVE_IPU_CLK_EN_OFS 3
60#define TVE_IPU_CLK_EN BIT(3)
61#define TVE_DAC_SAMP_RATE_OFS 1
62#define TVE_DAC_SAMP_RATE_WIDTH 2
63#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
64#define TVE_DAC_FULL_RATE (0x0 << 1)
65#define TVE_DAC_DIV2_RATE (0x1 << 1)
66#define TVE_DAC_DIV4_RATE (0x2 << 1)
67#define TVE_EN BIT(0)
68
69
70#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
71
72
73#define TVE_CD_CH_2_SM_EN BIT(22)
74#define TVE_CD_CH_1_SM_EN BIT(21)
75#define TVE_CD_CH_0_SM_EN BIT(20)
76#define TVE_CD_CH_2_LM_EN BIT(18)
77#define TVE_CD_CH_1_LM_EN BIT(17)
78#define TVE_CD_CH_0_LM_EN BIT(16)
79#define TVE_CD_CH_2_REF_LVL BIT(10)
80#define TVE_CD_CH_1_REF_LVL BIT(9)
81#define TVE_CD_CH_0_REF_LVL BIT(8)
82#define TVE_CD_EN BIT(0)
83
84
85#define TVE_FRAME_END_IEN BIT(13)
86#define TVE_CD_MON_END_IEN BIT(2)
87#define TVE_CD_SM_IEN BIT(1)
88#define TVE_CD_LM_IEN BIT(0)
89
90
91#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
92
93#define IMX_TVE_DAC_VOLTAGE 2750000
94
95enum {
96 TVE_MODE_TVOUT,
97 TVE_MODE_VGA,
98};
99
100struct imx_tve {
101 struct drm_connector connector;
102 struct drm_encoder encoder;
103 struct device *dev;
104 spinlock_t lock;
105 bool enabled;
106 int mode;
107 int di_hsync_pin;
108 int di_vsync_pin;
109
110 struct regmap *regmap;
111 struct regulator *dac_reg;
112 struct i2c_adapter *ddc;
113 struct clk *clk;
114 struct clk *di_sel_clk;
115 struct clk_hw clk_hw_di;
116 struct clk *di_clk;
117};
118
119static inline struct imx_tve *con_to_tve(struct drm_connector *c)
120{
121 return container_of(c, struct imx_tve, connector);
122}
123
124static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
125{
126 return container_of(e, struct imx_tve, encoder);
127}
128
129static void tve_lock(void *__tve)
130__acquires(&tve->lock)
131{
132 struct imx_tve *tve = __tve;
133
134 spin_lock(&tve->lock);
135}
136
137static void tve_unlock(void *__tve)
138__releases(&tve->lock)
139{
140 struct imx_tve *tve = __tve;
141
142 spin_unlock(&tve->lock);
143}
144
145static void tve_enable(struct imx_tve *tve)
146{
147 if (!tve->enabled) {
148 tve->enabled = true;
149 clk_prepare_enable(tve->clk);
150 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
151 TVE_EN, TVE_EN);
152 }
153
154
155 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
156
157
158 if (tve->mode == TVE_MODE_VGA)
159 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
160 else
161 regmap_write(tve->regmap, TVE_INT_CONT_REG,
162 TVE_CD_SM_IEN |
163 TVE_CD_LM_IEN |
164 TVE_CD_MON_END_IEN);
165}
166
167static void tve_disable(struct imx_tve *tve)
168{
169 if (tve->enabled) {
170 tve->enabled = false;
171 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
172 clk_disable_unprepare(tve->clk);
173 }
174}
175
176static int tve_setup_tvout(struct imx_tve *tve)
177{
178 return -ENOTSUPP;
179}
180
181static int tve_setup_vga(struct imx_tve *tve)
182{
183 unsigned int mask;
184 unsigned int val;
185 int ret;
186
187
188 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
189 TVE_TVDAC_GAIN_MASK, 0x0a);
190 if (ret)
191 return ret;
192
193 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
194 TVE_TVDAC_GAIN_MASK, 0x0a);
195 if (ret)
196 return ret;
197
198 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
199 TVE_TVDAC_GAIN_MASK, 0x0a);
200 if (ret)
201 return ret;
202
203
204 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
205 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
206 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
207 val |= TVE_TV_STAND_HD_1080P30 | 0;
208 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
209 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
210 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
211 if (ret)
212 return ret;
213
214
215 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
216 TVE_TVDAC_TEST_MODE_MASK, 1);
217}
218
219static int imx_tve_connector_get_modes(struct drm_connector *connector)
220{
221 struct imx_tve *tve = con_to_tve(connector);
222 struct edid *edid;
223 int ret = 0;
224
225 if (!tve->ddc)
226 return 0;
227
228 edid = drm_get_edid(connector, tve->ddc);
229 if (edid) {
230 drm_connector_update_edid_property(connector, edid);
231 ret = drm_add_edid_modes(connector, edid);
232 kfree(edid);
233 }
234
235 return ret;
236}
237
238static int imx_tve_connector_mode_valid(struct drm_connector *connector,
239 struct drm_display_mode *mode)
240{
241 struct imx_tve *tve = con_to_tve(connector);
242 unsigned long rate;
243
244
245 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
246 if (rate == mode->clock)
247 return MODE_OK;
248
249
250 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
251 if (rate == mode->clock)
252 return MODE_OK;
253
254 dev_warn(tve->dev, "ignoring mode %dx%d\n",
255 mode->hdisplay, mode->vdisplay);
256
257 return MODE_BAD;
258}
259
260static struct drm_encoder *imx_tve_connector_best_encoder(
261 struct drm_connector *connector)
262{
263 struct imx_tve *tve = con_to_tve(connector);
264
265 return &tve->encoder;
266}
267
268static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
269 struct drm_display_mode *orig_mode,
270 struct drm_display_mode *mode)
271{
272 struct imx_tve *tve = enc_to_tve(encoder);
273 unsigned long rounded_rate;
274 unsigned long rate;
275 int div = 1;
276 int ret;
277
278
279
280
281
282
283 rate = 2000UL * mode->clock;
284 clk_set_rate(tve->clk, rate);
285 rounded_rate = clk_get_rate(tve->clk);
286 if (rounded_rate >= rate)
287 div = 2;
288 clk_set_rate(tve->di_clk, rounded_rate / div);
289
290 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
291 if (ret < 0) {
292 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
293 ret);
294 }
295
296 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
297 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
298
299 if (tve->mode == TVE_MODE_VGA)
300 ret = tve_setup_vga(tve);
301 else
302 ret = tve_setup_tvout(tve);
303 if (ret)
304 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
305}
306
307static void imx_tve_encoder_enable(struct drm_encoder *encoder)
308{
309 struct imx_tve *tve = enc_to_tve(encoder);
310
311 tve_enable(tve);
312}
313
314static void imx_tve_encoder_disable(struct drm_encoder *encoder)
315{
316 struct imx_tve *tve = enc_to_tve(encoder);
317
318 tve_disable(tve);
319}
320
321static int imx_tve_atomic_check(struct drm_encoder *encoder,
322 struct drm_crtc_state *crtc_state,
323 struct drm_connector_state *conn_state)
324{
325 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
326 struct imx_tve *tve = enc_to_tve(encoder);
327
328 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
329 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
330 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
331
332 return 0;
333}
334
335static const struct drm_connector_funcs imx_tve_connector_funcs = {
336 .fill_modes = drm_helper_probe_single_connector_modes,
337 .destroy = imx_drm_connector_destroy,
338 .reset = drm_atomic_helper_connector_reset,
339 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
340 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
341};
342
343static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
344 .get_modes = imx_tve_connector_get_modes,
345 .best_encoder = imx_tve_connector_best_encoder,
346 .mode_valid = imx_tve_connector_mode_valid,
347};
348
349static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
350 .destroy = imx_drm_encoder_destroy,
351};
352
353static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
354 .mode_set = imx_tve_encoder_mode_set,
355 .enable = imx_tve_encoder_enable,
356 .disable = imx_tve_encoder_disable,
357 .atomic_check = imx_tve_atomic_check,
358};
359
360static irqreturn_t imx_tve_irq_handler(int irq, void *data)
361{
362 struct imx_tve *tve = data;
363 unsigned int val;
364
365 regmap_read(tve->regmap, TVE_STAT_REG, &val);
366
367
368 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
369
370 return IRQ_HANDLED;
371}
372
373static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
374 unsigned long parent_rate)
375{
376 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
377 unsigned int val;
378 int ret;
379
380 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
381 if (ret < 0)
382 return 0;
383
384 switch (val & TVE_DAC_SAMP_RATE_MASK) {
385 case TVE_DAC_DIV4_RATE:
386 return parent_rate / 4;
387 case TVE_DAC_DIV2_RATE:
388 return parent_rate / 2;
389 case TVE_DAC_FULL_RATE:
390 default:
391 return parent_rate;
392 }
393
394 return 0;
395}
396
397static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
398 unsigned long *prate)
399{
400 unsigned long div;
401
402 div = *prate / rate;
403 if (div >= 4)
404 return *prate / 4;
405 else if (div >= 2)
406 return *prate / 2;
407 return *prate;
408}
409
410static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
411 unsigned long parent_rate)
412{
413 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
414 unsigned long div;
415 u32 val;
416 int ret;
417
418 div = parent_rate / rate;
419 if (div >= 4)
420 val = TVE_DAC_DIV4_RATE;
421 else if (div >= 2)
422 val = TVE_DAC_DIV2_RATE;
423 else
424 val = TVE_DAC_FULL_RATE;
425
426 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
427 TVE_DAC_SAMP_RATE_MASK, val);
428
429 if (ret < 0) {
430 dev_err(tve->dev, "failed to set divider: %d\n", ret);
431 return ret;
432 }
433
434 return 0;
435}
436
437static const struct clk_ops clk_tve_di_ops = {
438 .round_rate = clk_tve_di_round_rate,
439 .set_rate = clk_tve_di_set_rate,
440 .recalc_rate = clk_tve_di_recalc_rate,
441};
442
443static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
444{
445 const char *tve_di_parent[1];
446 struct clk_init_data init = {
447 .name = "tve_di",
448 .ops = &clk_tve_di_ops,
449 .num_parents = 1,
450 .flags = 0,
451 };
452
453 tve_di_parent[0] = __clk_get_name(tve->clk);
454 init.parent_names = (const char **)&tve_di_parent;
455
456 tve->clk_hw_di.init = &init;
457 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
458 if (IS_ERR(tve->di_clk)) {
459 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
460 PTR_ERR(tve->di_clk));
461 return PTR_ERR(tve->di_clk);
462 }
463
464 return 0;
465}
466
467static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
468{
469 int encoder_type;
470 int ret;
471
472 encoder_type = tve->mode == TVE_MODE_VGA ?
473 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
474
475 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
476 if (ret)
477 return ret;
478
479 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
480 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
481 encoder_type, NULL);
482
483 drm_connector_helper_add(&tve->connector,
484 &imx_tve_connector_helper_funcs);
485 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
486 DRM_MODE_CONNECTOR_VGA);
487
488 drm_connector_attach_encoder(&tve->connector, &tve->encoder);
489
490 return 0;
491}
492
493static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
494{
495 return (reg % 4 == 0) && (reg <= 0xdc);
496}
497
498static struct regmap_config tve_regmap_config = {
499 .reg_bits = 32,
500 .val_bits = 32,
501 .reg_stride = 4,
502
503 .readable_reg = imx_tve_readable_reg,
504
505 .lock = tve_lock,
506 .unlock = tve_unlock,
507
508 .max_register = 0xdc,
509};
510
511static const char * const imx_tve_modes[] = {
512 [TVE_MODE_TVOUT] = "tvout",
513 [TVE_MODE_VGA] = "vga",
514};
515
516static const int of_get_tve_mode(struct device_node *np)
517{
518 const char *bm;
519 int ret, i;
520
521 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
522 if (ret < 0)
523 return ret;
524
525 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
526 if (!strcasecmp(bm, imx_tve_modes[i]))
527 return i;
528
529 return -EINVAL;
530}
531
532static int imx_tve_bind(struct device *dev, struct device *master, void *data)
533{
534 struct platform_device *pdev = to_platform_device(dev);
535 struct drm_device *drm = data;
536 struct device_node *np = dev->of_node;
537 struct device_node *ddc_node;
538 struct imx_tve *tve;
539 struct resource *res;
540 void __iomem *base;
541 unsigned int val;
542 int irq;
543 int ret;
544
545 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
546 if (!tve)
547 return -ENOMEM;
548
549 tve->dev = dev;
550 spin_lock_init(&tve->lock);
551
552 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
553 if (ddc_node) {
554 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
555 of_node_put(ddc_node);
556 }
557
558 tve->mode = of_get_tve_mode(np);
559 if (tve->mode != TVE_MODE_VGA) {
560 dev_err(dev, "only VGA mode supported, currently\n");
561 return -EINVAL;
562 }
563
564 if (tve->mode == TVE_MODE_VGA) {
565 ret = of_property_read_u32(np, "fsl,hsync-pin",
566 &tve->di_hsync_pin);
567
568 if (ret < 0) {
569 dev_err(dev, "failed to get hsync pin\n");
570 return ret;
571 }
572
573 ret = of_property_read_u32(np, "fsl,vsync-pin",
574 &tve->di_vsync_pin);
575
576 if (ret < 0) {
577 dev_err(dev, "failed to get vsync pin\n");
578 return ret;
579 }
580 }
581
582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 base = devm_ioremap_resource(dev, res);
584 if (IS_ERR(base))
585 return PTR_ERR(base);
586
587 tve_regmap_config.lock_arg = tve;
588 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
589 &tve_regmap_config);
590 if (IS_ERR(tve->regmap)) {
591 dev_err(dev, "failed to init regmap: %ld\n",
592 PTR_ERR(tve->regmap));
593 return PTR_ERR(tve->regmap);
594 }
595
596 irq = platform_get_irq(pdev, 0);
597 if (irq < 0) {
598 dev_err(dev, "failed to get irq\n");
599 return irq;
600 }
601
602 ret = devm_request_threaded_irq(dev, irq, NULL,
603 imx_tve_irq_handler, IRQF_ONESHOT,
604 "imx-tve", tve);
605 if (ret < 0) {
606 dev_err(dev, "failed to request irq: %d\n", ret);
607 return ret;
608 }
609
610 tve->dac_reg = devm_regulator_get(dev, "dac");
611 if (!IS_ERR(tve->dac_reg)) {
612 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
613 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
614 ret = regulator_enable(tve->dac_reg);
615 if (ret)
616 return ret;
617 }
618
619 tve->clk = devm_clk_get(dev, "tve");
620 if (IS_ERR(tve->clk)) {
621 dev_err(dev, "failed to get high speed tve clock: %ld\n",
622 PTR_ERR(tve->clk));
623 return PTR_ERR(tve->clk);
624 }
625
626
627 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
628 if (IS_ERR(tve->di_sel_clk)) {
629 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
630 PTR_ERR(tve->di_sel_clk));
631 return PTR_ERR(tve->di_sel_clk);
632 }
633
634 ret = tve_clk_init(tve, base);
635 if (ret < 0)
636 return ret;
637
638 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
639 if (ret < 0) {
640 dev_err(dev, "failed to read configuration register: %d\n",
641 ret);
642 return ret;
643 }
644 if (val != 0x00100000) {
645 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
646 return -ENODEV;
647 }
648
649
650 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
651 if (ret)
652 return ret;
653
654 ret = imx_tve_register(drm, tve);
655 if (ret)
656 return ret;
657
658 dev_set_drvdata(dev, tve);
659
660 return 0;
661}
662
663static void imx_tve_unbind(struct device *dev, struct device *master,
664 void *data)
665{
666 struct imx_tve *tve = dev_get_drvdata(dev);
667
668 if (!IS_ERR(tve->dac_reg))
669 regulator_disable(tve->dac_reg);
670}
671
672static const struct component_ops imx_tve_ops = {
673 .bind = imx_tve_bind,
674 .unbind = imx_tve_unbind,
675};
676
677static int imx_tve_probe(struct platform_device *pdev)
678{
679 return component_add(&pdev->dev, &imx_tve_ops);
680}
681
682static int imx_tve_remove(struct platform_device *pdev)
683{
684 component_del(&pdev->dev, &imx_tve_ops);
685 return 0;
686}
687
688static const struct of_device_id imx_tve_dt_ids[] = {
689 { .compatible = "fsl,imx53-tve", },
690 { }
691};
692MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
693
694static struct platform_driver imx_tve_driver = {
695 .probe = imx_tve_probe,
696 .remove = imx_tve_remove,
697 .driver = {
698 .of_match_table = imx_tve_dt_ids,
699 .name = "imx-tve",
700 },
701};
702
703module_platform_driver(imx_tve_driver);
704
705MODULE_DESCRIPTION("i.MX Television Encoder driver");
706MODULE_AUTHOR("Philipp Zabel, Pengutronix");
707MODULE_LICENSE("GPL");
708MODULE_ALIAS("platform:imx-tve");
709
