1/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#ifndef _DPU_HW_UTIL_H 14#define _DPU_HW_UTIL_H 15 16#include <linux/io.h> 17#include <linux/slab.h> 18#include "dpu_hw_mdss.h" 19 20#define REG_MASK(n) ((BIT(n)) - 1) 21 22/* 23 * This is the common struct maintained by each sub block 24 * for mapping the register offsets in this block to the 25 * absoulute IO address 26 * @base_off: mdp register mapped offset 27 * @blk_off: pipe offset relative to mdss offset 28 * @length length of register block offset 29 * @xin_id xin id 30 * @hwversion mdss hw version number 31 */ 32struct dpu_hw_blk_reg_map { 33 void __iomem *base_off; 34 u32 blk_off; 35 u32 length; 36 u32 xin_id; 37 u32 hwversion; 38 u32 log_mask; 39}; 40 41/** 42 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration 43 * @enable: detail enhancer enable/disable 44 * @sharpen_level1: sharpening strength for noise 45 * @sharpen_level2: sharpening strength for signal 46 * @ clip: clip shift 47 * @ limit: limit value 48 * @ thr_quiet: quiet threshold 49 * @ thr_dieout: dieout threshold 50 * @ thr_high: low threshold 51 * @ thr_high: high threshold 52 * @ prec_shift: precision shift 53 * @ adjust_a: A-coefficients for mapping curve 54 * @ adjust_b: B-coefficients for mapping curve 55 * @ adjust_c: C-coefficients for mapping curve 56 */ 57struct dpu_hw_scaler3_de_cfg { 58 u32 enable; 59 int16_t sharpen_level1; 60 int16_t sharpen_level2; 61 uint16_t clip; 62 uint16_t limit; 63 uint16_t thr_quiet; 64 uint16_t thr_dieout; 65 uint16_t thr_low; 66 uint16_t thr_high; 67 uint16_t prec_shift; 68 int16_t adjust_a[DPU_MAX_DE_CURVES]; 69 int16_t adjust_b[DPU_MAX_DE_CURVES]; 70 int16_t adjust_c[DPU_MAX_DE_CURVES]; 71}; 72 73 74/** 75 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration 76 * @enable: scaler enable 77 * @dir_en: direction detection block enable 78 * @ init_phase_x: horizontal initial phase 79 * @ phase_step_x: horizontal phase step 80 * @ init_phase_y: vertical initial phase 81 * @ phase_step_y: vertical phase step 82 * @ preload_x: horizontal preload value 83 * @ preload_y: vertical preload value 84 * @ src_width: source width 85 * @ src_height: source height 86 * @ dst_width: destination width 87 * @ dst_height: destination height 88 * @ y_rgb_filter_cfg: y/rgb plane filter configuration 89 * @ uv_filter_cfg: uv plane filter configuration 90 * @ alpha_filter_cfg: alpha filter configuration 91 * @ blend_cfg: blend coefficients configuration 92 * @ lut_flag: scaler LUT update flags 93 * 0x1 swap LUT bank 94 * 0x2 update 2D filter LUT 95 * 0x4 update y circular filter LUT 96 * 0x8 update uv circular filter LUT 97 * 0x10 update y separable filter LUT 98 * 0x20 update uv separable filter LUT 99 * @ dir_lut_idx: 2D filter LUT index 100 * @ y_rgb_cir_lut_idx: y circular filter LUT index 101 * @ uv_cir_lut_idx: uv circular filter LUT index 102 * @ y_rgb_sep_lut_idx: y circular filter LUT index 103 * @ uv_sep_lut_idx: uv separable filter LUT index 104 * @ dir_lut: pointer to 2D LUT 105 * @ cir_lut: pointer to circular filter LUT 106 * @ sep_lut: pointer to separable filter LUT 107 * @ de: detail enhancer configuration 108 */ 109struct dpu_hw_scaler3_cfg { 110 u32 enable; 111 u32 dir_en; 112 int32_t init_phase_x[DPU_MAX_PLANES]; 113 int32_t phase_step_x[DPU_MAX_PLANES]; 114 int32_t init_phase_y[DPU_MAX_PLANES]; 115 int32_t phase_step_y[DPU_MAX_PLANES]; 116 117 u32 preload_x[DPU_MAX_PLANES]; 118 u32 preload_y[DPU_MAX_PLANES]; 119 u32 src_width[DPU_MAX_PLANES]; 120 u32 src_height[DPU_MAX_PLANES]; 121 122 u32 dst_width; 123 u32 dst_height; 124 125 u32 y_rgb_filter_cfg; 126 u32 uv_filter_cfg; 127 u32 alpha_filter_cfg; 128 u32 blend_cfg; 129 130 u32 lut_flag; 131 u32 dir_lut_idx; 132 133 u32 y_rgb_cir_lut_idx; 134 u32 uv_cir_lut_idx; 135 u32 y_rgb_sep_lut_idx; 136 u32 uv_sep_lut_idx; 137 u32 *dir_lut; 138 size_t dir_len; 139 u32 *cir_lut; 140 size_t cir_len; 141 u32 *sep_lut; 142 size_t sep_len; 143 144 /* 145 * Detail enhancer settings 146 */ 147 struct dpu_hw_scaler3_de_cfg de; 148}; 149 150/** 151 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure 152 * @num_ext_pxls_lr: Number of total horizontal pixels 153 * @num_ext_pxls_tb: Number of total vertical lines 154 * @left_ftch: Number of extra pixels to overfetch from left 155 * @right_ftch: Number of extra pixels to overfetch from right 156 * @top_ftch: Number of extra lines to overfetch from top 157 * @btm_ftch: Number of extra lines to overfetch from bottom 158 * @left_rpt: Number of extra pixels to repeat from left 159 * @right_rpt: Number of extra pixels to repeat from right 160 * @top_rpt: Number of extra lines to repeat from top 161 * @btm_rpt: Number of extra lines to repeat from bottom 162 */ 163struct dpu_drm_pix_ext_v1 { 164 /* 165 * Number of pixels ext in left, right, top and bottom direction 166 * for all color components. 167 */ 168 int32_t num_ext_pxls_lr[DPU_MAX_PLANES]; 169 int32_t num_ext_pxls_tb[DPU_MAX_PLANES]; 170 171 /* 172 * Number of pixels needs to be overfetched in left, right, top 173 * and bottom directions from source image for scaling. 174 */ 175 int32_t left_ftch[DPU_MAX_PLANES]; 176 int32_t right_ftch[DPU_MAX_PLANES]; 177 int32_t top_ftch[DPU_MAX_PLANES]; 178 int32_t btm_ftch[DPU_MAX_PLANES]; 179 /* 180 * Number of pixels needs to be repeated in left, right, top and 181 * bottom directions for scaling. 182 */ 183 int32_t left_rpt[DPU_MAX_PLANES]; 184 int32_t right_rpt[DPU_MAX_PLANES]; 185 int32_t top_rpt[DPU_MAX_PLANES]; 186 int32_t btm_rpt[DPU_MAX_PLANES]; 187 188}; 189 190/** 191 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure 192 * @enable: Enables/disables detail enhancer 193 * @sharpen_level1: Sharpening strength for noise 194 * @sharpen_level2: Sharpening strength for context 195 * @clip: Clip coefficient 196 * @limit: Detail enhancer limit factor 197 * @thr_quiet: Quite zone threshold 198 * @thr_dieout: Die-out zone threshold 199 * @thr_low: Linear zone left threshold 200 * @thr_high: Linear zone right threshold 201 * @prec_shift: Detail enhancer precision 202 * @adjust_a: Mapping curves A coefficients 203 * @adjust_b: Mapping curves B coefficients 204 * @adjust_c: Mapping curves C coefficients 205 */ 206struct dpu_drm_de_v1 { 207 uint32_t enable; 208 int16_t sharpen_level1; 209 int16_t sharpen_level2; 210 uint16_t clip; 211 uint16_t limit; 212 uint16_t thr_quiet; 213 uint16_t thr_dieout; 214 uint16_t thr_low; 215 uint16_t thr_high; 216 uint16_t prec_shift; 217 int16_t adjust_a[DPU_MAX_DE_CURVES]; 218 int16_t adjust_b[DPU_MAX_DE_CURVES]; 219 int16_t adjust_c[DPU_MAX_DE_CURVES]; 220}; 221 222/** 223 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler 224 * @enable: Scaler enable 225 * @dir_en: Detail enhancer enable 226 * @pe: Pixel extension settings 227 * @horz_decimate: Horizontal decimation factor 228 * @vert_decimate: Vertical decimation factor 229 * @init_phase_x: Initial scaler phase values for x 230 * @phase_step_x: Phase step values for x 231 * @init_phase_y: Initial scaler phase values for y 232 * @phase_step_y: Phase step values for y 233 * @preload_x: Horizontal preload value 234 * @preload_y: Vertical preload value 235 * @src_width: Source width 236 * @src_height: Source height 237 * @dst_width: Destination width 238 * @dst_height: Destination height 239 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 240 * @uv_filter_cfg: UV plane filter configuration 241 * @alpha_filter_cfg: Alpha filter configuration 242 * @blend_cfg: Selection of blend coefficients 243 * @lut_flag: LUT configuration flags 244 * @dir_lut_idx: 2d 4x4 LUT index 245 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 246 * @uv_cir_lut_idx: UV circular LUT index 247 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 248 * @uv_sep_lut_idx: UV separable LUT index 249 * @de: Detail enhancer settings 250 */ 251struct dpu_drm_scaler_v2 { 252 /* 253 * General definitions 254 */ 255 uint32_t enable; 256 uint32_t dir_en; 257 258 /* 259 * Pix ext settings 260 */ 261 struct dpu_drm_pix_ext_v1 pe; 262 263 /* 264 * Decimation settings 265 */ 266 uint32_t horz_decimate; 267 uint32_t vert_decimate; 268 269 /* 270 * Phase settings 271 */ 272 int32_t init_phase_x[DPU_MAX_PLANES]; 273 int32_t phase_step_x[DPU_MAX_PLANES]; 274 int32_t init_phase_y[DPU_MAX_PLANES]; 275 int32_t phase_step_y[DPU_MAX_PLANES]; 276 277 uint32_t preload_x[DPU_MAX_PLANES]; 278 uint32_t preload_y[DPU_MAX_PLANES]; 279 uint32_t src_width[DPU_MAX_PLANES]; 280 uint32_t src_height[DPU_MAX_PLANES]; 281 282 uint32_t dst_width; 283 uint32_t dst_height; 284 285 uint32_t y_rgb_filter_cfg; 286 uint32_t uv_filter_cfg; 287 uint32_t alpha_filter_cfg; 288 uint32_t blend_cfg; 289 290 uint32_t lut_flag; 291 uint32_t dir_lut_idx; 292 293 /* for Y(RGB) and UV planes*/ 294 uint32_t y_rgb_cir_lut_idx; 295 uint32_t uv_cir_lut_idx; 296 uint32_t y_rgb_sep_lut_idx; 297 uint32_t uv_sep_lut_idx; 298 299 /* 300 * Detail enhancer settings 301 */ 302 struct dpu_drm_de_v1 de; 303}; 304 305 306u32 *dpu_hw_util_get_log_mask_ptr(void); 307 308void dpu_reg_write(struct dpu_hw_blk_reg_map *c, 309 u32 reg_off, 310 u32 val, 311 const char *name); 312int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off); 313 314#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) 315#define DPU_REG_READ(c, off) dpu_reg_read(c, off) 316 317void *dpu_hw_util_get_dir(void); 318 319void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, 320 struct dpu_hw_scaler3_cfg *scaler3_cfg, 321 u32 scaler_offset, u32 scaler_version, 322 const struct dpu_format *format); 323 324u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, 325 u32 scaler_offset); 326 327void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 328 u32 csc_reg_off, 329 struct dpu_csc_cfg *data, bool csc10); 330 331#endif /* _DPU_HW_UTIL_H */ 332