LXR linux/drivers/gpu/drm/msm/dsi/phy/dsi

   1/*
   2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 and
   6 * only version 2 as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13
  14#ifndef __DSI_PHY_H__
  15#define __DSI_PHY_H__
  16
  17#include <linux/regulator/consumer.h>
  18
  19#include "dsi.h"
  20
  21#define dsi_phy_read(offset) msm_readl((offset))
  22#define dsi_phy_write(offset, data) msm_writel((data), (offset))
  23
  24struct msm_dsi_phy_ops {
  25        int (*init) (struct msm_dsi_phy *phy);
  26        int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
  27                        struct msm_dsi_phy_clk_request *clk_req);
  28        void (*disable)(struct msm_dsi_phy *phy);
  29};
  30
  31struct msm_dsi_phy_cfg {
  32        enum msm_dsi_phy_type type;
  33        struct dsi_reg_config reg_cfg;
  34        struct msm_dsi_phy_ops ops;
  35
  36        /*
  37         * Each cell {phy_id, pll_id} of the truth table indicates
  38         * if the source PLL selection bit should be set for each PHY.
  39         * Fill default H/W values in illegal cells, eg. cell {0, 1}.
  40         */
  41        bool src_pll_truthtable[DSI_MAX][DSI_MAX];
  42        const resource_size_t io_start[DSI_MAX];
  43        const int num_dsi_phy;
  44};
  45
  46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
  47extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
  48extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
  49extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
  50extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
  51extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
  52
  53struct msm_dsi_dphy_timing {
  54        u32 clk_pre;
  55        u32 clk_post;
  56        u32 clk_zero;
  57        u32 clk_trail;
  58        u32 clk_prepare;
  59        u32 hs_exit;
  60        u32 hs_zero;
  61        u32 hs_prepare;
  62        u32 hs_trail;
  63        u32 hs_rqst;
  64        u32 ta_go;
  65        u32 ta_sure;
  66        u32 ta_get;
  67
  68        struct msm_dsi_phy_shared_timings shared_timings;
  69
  70        /* For PHY v2 only */
  71        u32 hs_rqst_ckln;
  72        u32 hs_prep_dly;
  73        u32 hs_prep_dly_ckln;
  74        u8 hs_halfbyte_en;
  75        u8 hs_halfbyte_en_ckln;
  76};
  77
  78struct msm_dsi_phy {
  79        struct platform_device *pdev;
  80        void __iomem *base;
  81        void __iomem *reg_base;
  82        void __iomem *lane_base;
  83        int id;
  84
  85        struct clk *ahb_clk;
  86        struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
  87
  88        struct msm_dsi_dphy_timing timing;
  89        const struct msm_dsi_phy_cfg *cfg;
  90
  91        enum msm_dsi_phy_usecase usecase;
  92        bool regulator_ldo_mode;
  93
  94        struct msm_dsi_pll *pll;
  95};
  96
  97/*
  98 * PHY internal functions
  99 */
 100int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
 101                             struct msm_dsi_phy_clk_request *clk_req);
 102int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
 103                                struct msm_dsi_phy_clk_request *clk_req);
 104int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
 105                                struct msm_dsi_phy_clk_request *clk_req);
 106void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
 107                                u32 bit_mask);
 108int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
 109
 110#endif /* __DSI_PHY_H__ */
 111
 112