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15#include <linux/export.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/platform_device.h>
23#include <linux/videodev2.h>
24#include <uapi/linux/v4l2-mediabus.h>
25#include <linux/clk.h>
26#include <linux/clk-provider.h>
27#include <linux/clkdev.h>
28
29#include "ipu-prv.h"
30
31struct ipu_csi {
32 void __iomem *base;
33 int id;
34 u32 module;
35 struct clk *clk_ipu;
36 spinlock_t lock;
37 bool inuse;
38 struct ipu_soc *ipu;
39};
40
41
42#define CSI_SENS_CONF 0x0000
43#define CSI_SENS_FRM_SIZE 0x0004
44#define CSI_ACT_FRM_SIZE 0x0008
45#define CSI_OUT_FRM_CTRL 0x000c
46#define CSI_TST_CTRL 0x0010
47#define CSI_CCIR_CODE_1 0x0014
48#define CSI_CCIR_CODE_2 0x0018
49#define CSI_CCIR_CODE_3 0x001c
50#define CSI_MIPI_DI 0x0020
51#define CSI_SKIP 0x0024
52#define CSI_CPD_CTRL 0x0028
53#define CSI_CPD_RC(n) (0x002c + ((n)*4))
54#define CSI_CPD_RS(n) (0x004c + ((n)*4))
55#define CSI_CPD_GRC(n) (0x005c + ((n)*4))
56#define CSI_CPD_GRS(n) (0x007c + ((n)*4))
57#define CSI_CPD_GBC(n) (0x008c + ((n)*4))
58#define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
59#define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
60#define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
61#define CSI_CPD_OFFSET1 0x00ec
62#define CSI_CPD_OFFSET2 0x00f0
63
64
65#define CSI_SENS_CONF_DATA_FMT_SHIFT 8
66#define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
67#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
68#define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
69#define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
70#define CSI_SENS_CONF_DATA_FMT_BAYER 3L
71#define CSI_SENS_CONF_DATA_FMT_RGB565 4L
72#define CSI_SENS_CONF_DATA_FMT_RGB555 5L
73#define CSI_SENS_CONF_DATA_FMT_RGB444 6L
74#define CSI_SENS_CONF_DATA_FMT_JPEG 7L
75
76#define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
77#define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
78#define CSI_SENS_CONF_DATA_POL_SHIFT 2
79#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
80#define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
81#define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
82#define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
83#define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
84#define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
85#define CSI_SENS_CONF_DIVRATIO_SHIFT 16
86
87#define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
88#define CSI_SENS_CONF_DATA_DEST_SHIFT 24
89#define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
90#define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
91#define CSI_SENS_CONF_JPEG_EN_SHIFT 28
92#define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
93#define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
94
95#define CSI_DATA_DEST_IC 2
96#define CSI_DATA_DEST_IDMAC 4
97
98#define CSI_CCIR_ERR_DET_EN 0x01000000
99#define CSI_HORI_DOWNSIZE_EN 0x80000000
100#define CSI_VERT_DOWNSIZE_EN 0x40000000
101#define CSI_TEST_GEN_MODE_EN 0x01000000
102
103#define CSI_HSC_MASK 0x1fff0000
104#define CSI_HSC_SHIFT 16
105#define CSI_VSC_MASK 0x00000fff
106#define CSI_VSC_SHIFT 0
107
108#define CSI_TEST_GEN_R_MASK 0x000000ff
109#define CSI_TEST_GEN_R_SHIFT 0
110#define CSI_TEST_GEN_G_MASK 0x0000ff00
111#define CSI_TEST_GEN_G_SHIFT 8
112#define CSI_TEST_GEN_B_MASK 0x00ff0000
113#define CSI_TEST_GEN_B_SHIFT 16
114
115#define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
116#define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
117#define CSI_SKIP_SMFC_MASK 0x000000f8
118#define CSI_SKIP_SMFC_SHIFT 3
119#define CSI_ID_2_SKIP_MASK 0x00000300
120#define CSI_ID_2_SKIP_SHIFT 8
121
122#define CSI_COLOR_FIRST_ROW_MASK 0x00000002
123#define CSI_COLOR_FIRST_COMP_MASK 0x00000001
124
125
126#define MIPI_DT_YUV420 0x18
127#define MIPI_DT_YUV420_LEGACY 0x1a
128#define MIPI_DT_YUV422 0x1e
129#define MIPI_DT_RGB444 0x20
130#define MIPI_DT_RGB555 0x21
131#define MIPI_DT_RGB565 0x22
132#define MIPI_DT_RGB666 0x23
133#define MIPI_DT_RGB888 0x24
134#define MIPI_DT_RAW6 0x28
135#define MIPI_DT_RAW7 0x29
136#define MIPI_DT_RAW8 0x2a
137#define MIPI_DT_RAW10 0x2b
138#define MIPI_DT_RAW12 0x2c
139#define MIPI_DT_RAW14 0x2d
140
141
142
143
144struct ipu_csi_bus_config {
145 unsigned data_width:4;
146 unsigned clk_mode:3;
147 unsigned ext_vsync:1;
148 unsigned vsync_pol:1;
149 unsigned hsync_pol:1;
150 unsigned pixclk_pol:1;
151 unsigned data_pol:1;
152 unsigned sens_clksrc:1;
153 unsigned pack_tight:1;
154 unsigned force_eof:1;
155 unsigned data_en_pol:1;
156
157 unsigned data_fmt;
158 unsigned mipi_dt;
159};
160
161
162
163
164enum ipu_csi_data_width {
165 IPU_CSI_DATA_WIDTH_4 = 0,
166 IPU_CSI_DATA_WIDTH_8 = 1,
167 IPU_CSI_DATA_WIDTH_10 = 3,
168 IPU_CSI_DATA_WIDTH_12 = 5,
169 IPU_CSI_DATA_WIDTH_16 = 9,
170};
171
172
173
174
175enum ipu_csi_clk_mode {
176 IPU_CSI_CLK_MODE_GATED_CLK,
177 IPU_CSI_CLK_MODE_NONGATED_CLK,
178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
184};
185
186static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
187{
188 return readl(csi->base + offset);
189}
190
191static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
192 unsigned offset)
193{
194 writel(value, csi->base + offset);
195}
196
197
198
199
200
201static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
202 u32 ipu_clk)
203{
204 u32 temp;
205 int div_ratio;
206
207 div_ratio = (ipu_clk / pixel_clk) - 1;
208
209 if (div_ratio > 0xFF || div_ratio < 0) {
210 dev_err(csi->ipu->dev,
211 "value of pixel_clk extends normal range\n");
212 return -EINVAL;
213 }
214
215 temp = ipu_csi_read(csi, CSI_SENS_CONF);
216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
218 CSI_SENS_CONF);
219
220 return 0;
221}
222
223
224
225
226
227static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code,
228 enum v4l2_mbus_type mbus_type)
229{
230 switch (mbus_code) {
231 case MEDIA_BUS_FMT_BGR565_2X8_BE:
232 case MEDIA_BUS_FMT_BGR565_2X8_LE:
233 case MEDIA_BUS_FMT_RGB565_2X8_BE:
234 case MEDIA_BUS_FMT_RGB565_2X8_LE:
235 if (mbus_type == V4L2_MBUS_CSI2_DPHY)
236 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
237 else
238 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
239 cfg->mipi_dt = MIPI_DT_RGB565;
240 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
241 break;
242 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
243 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
244 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
245 cfg->mipi_dt = MIPI_DT_RGB444;
246 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
247 break;
248 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
249 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
250 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
251 cfg->mipi_dt = MIPI_DT_RGB555;
252 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
253 break;
254 case MEDIA_BUS_FMT_RGB888_1X24:
255 case MEDIA_BUS_FMT_BGR888_1X24:
256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
257 cfg->mipi_dt = MIPI_DT_RGB888;
258 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
259 break;
260 case MEDIA_BUS_FMT_UYVY8_2X8:
261 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
262 cfg->mipi_dt = MIPI_DT_YUV422;
263 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
264 break;
265 case MEDIA_BUS_FMT_YUYV8_2X8:
266 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
267 cfg->mipi_dt = MIPI_DT_YUV422;
268 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
269 break;
270 case MEDIA_BUS_FMT_UYVY8_1X16:
271 case MEDIA_BUS_FMT_YUYV8_1X16:
272 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
273 cfg->mipi_dt = MIPI_DT_YUV422;
274 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
275 break;
276 case MEDIA_BUS_FMT_SBGGR8_1X8:
277 case MEDIA_BUS_FMT_SGBRG8_1X8:
278 case MEDIA_BUS_FMT_SGRBG8_1X8:
279 case MEDIA_BUS_FMT_SRGGB8_1X8:
280 case MEDIA_BUS_FMT_Y8_1X8:
281 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
282 cfg->mipi_dt = MIPI_DT_RAW8;
283 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
284 break;
285 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
286 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
287 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
288 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
289 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
290 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
291 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
292 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
293 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
294 cfg->mipi_dt = MIPI_DT_RAW10;
295 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
296 break;
297 case MEDIA_BUS_FMT_SBGGR10_1X10:
298 case MEDIA_BUS_FMT_SGBRG10_1X10:
299 case MEDIA_BUS_FMT_SGRBG10_1X10:
300 case MEDIA_BUS_FMT_SRGGB10_1X10:
301 case MEDIA_BUS_FMT_Y10_1X10:
302 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
303 cfg->mipi_dt = MIPI_DT_RAW10;
304 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
305 break;
306 case MEDIA_BUS_FMT_SBGGR12_1X12:
307 case MEDIA_BUS_FMT_SGBRG12_1X12:
308 case MEDIA_BUS_FMT_SGRBG12_1X12:
309 case MEDIA_BUS_FMT_SRGGB12_1X12:
310 case MEDIA_BUS_FMT_Y12_1X12:
311 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
312 cfg->mipi_dt = MIPI_DT_RAW12;
313 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
314 break;
315 case MEDIA_BUS_FMT_JPEG_1X8:
316
317 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
318 cfg->mipi_dt = MIPI_DT_RAW8;
319 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
320 break;
321 default:
322 return -EINVAL;
323 }
324
325 return 0;
326}
327
328
329static inline enum v4l2_field
330ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std)
331{
332 return (field != V4L2_FIELD_ALTERNATE) ? field :
333 ((std & V4L2_STD_525_60) ?
334 V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB);
335}
336
337
338
339
340static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
341 const struct v4l2_mbus_config *mbus_cfg,
342 const struct v4l2_mbus_framefmt *mbus_fmt)
343{
344 int ret;
345
346 memset(csicfg, 0, sizeof(*csicfg));
347
348 ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type);
349 if (ret < 0)
350 return ret;
351
352 switch (mbus_cfg->type) {
353 case V4L2_MBUS_PARALLEL:
354 csicfg->ext_vsync = 1;
355 csicfg->vsync_pol = (mbus_cfg->flags &
356 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
357 csicfg->hsync_pol = (mbus_cfg->flags &
358 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
359 csicfg->pixclk_pol = (mbus_cfg->flags &
360 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
361 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
362 break;
363 case V4L2_MBUS_BT656:
364 csicfg->ext_vsync = 0;
365 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) ||
366 mbus_fmt->field == V4L2_FIELD_ALTERNATE)
367 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
368 else
369 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
370 break;
371 case V4L2_MBUS_CSI2_DPHY:
372
373
374
375
376 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
377 break;
378 default:
379
380 break;
381 }
382
383 return 0;
384}
385
386static int
387ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
388 const struct v4l2_mbus_framefmt *infmt,
389 const struct v4l2_mbus_framefmt *outfmt,
390 v4l2_std_id std)
391{
392 enum v4l2_field infield, outfield;
393 bool swap_fields;
394
395
396 infield = ipu_csi_translate_field(infmt->field, std);
397 outfield = ipu_csi_translate_field(outfmt->field, std);
398
399
400
401
402
403
404
405
406
407 swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) &&
408 V4L2_FIELD_IS_SEQUENTIAL(outfield) &&
409 infield != outfield);
410
411 if (!swap_fields) {
412
413
414
415
416
417
418 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
419 CSI_CCIR_CODE_1);
420 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
421 } else {
422 dev_dbg(csi->ipu->dev, "capture field swap\n");
423
424
425 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
426 CSI_CCIR_CODE_1);
427 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
428 }
429
430 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
431
432 return 0;
433}
434
435
436int ipu_csi_init_interface(struct ipu_csi *csi,
437 const struct v4l2_mbus_config *mbus_cfg,
438 const struct v4l2_mbus_framefmt *infmt,
439 const struct v4l2_mbus_framefmt *outfmt)
440{
441 struct ipu_csi_bus_config cfg;
442 unsigned long flags;
443 u32 width, height, data = 0;
444 v4l2_std_id std;
445 int ret;
446
447 ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt);
448 if (ret < 0)
449 return ret;
450
451
452 width = infmt->width;
453 height = infmt->height;
454 if (infmt->field == V4L2_FIELD_ALTERNATE)
455 height *= 2;
456
457
458 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
459 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
460 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
461 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
462 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
463 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
464 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
465 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
466 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
467 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
468 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
469
470 spin_lock_irqsave(&csi->lock, flags);
471
472 ipu_csi_write(csi, data, CSI_SENS_CONF);
473
474
475
476 switch (cfg.clk_mode) {
477 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
478 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
479 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
480 break;
481 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
482 if (width == 720 && height == 480) {
483 std = V4L2_STD_NTSC;
484 height = 525;
485 } else if (width == 720 && height == 576) {
486 std = V4L2_STD_PAL;
487 height = 625;
488 } else {
489 dev_err(csi->ipu->dev,
490 "Unsupported interlaced video mode\n");
491 ret = -EINVAL;
492 goto out_unlock;
493 }
494
495 ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std);
496 if (ret)
497 goto out_unlock;
498 break;
499 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
500 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
501 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
502 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
503 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
504 CSI_CCIR_CODE_1);
505 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
506 break;
507 case IPU_CSI_CLK_MODE_GATED_CLK:
508 case IPU_CSI_CLK_MODE_NONGATED_CLK:
509 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
510 break;
511 }
512
513
514 ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
515 CSI_SENS_FRM_SIZE);
516
517 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
518 ipu_csi_read(csi, CSI_SENS_CONF));
519 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
520 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
521
522out_unlock:
523 spin_unlock_irqrestore(&csi->lock, flags);
524
525 return ret;
526}
527EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
528
529bool ipu_csi_is_interlaced(struct ipu_csi *csi)
530{
531 unsigned long flags;
532 u32 sensor_protocol;
533
534 spin_lock_irqsave(&csi->lock, flags);
535 sensor_protocol =
536 (ipu_csi_read(csi, CSI_SENS_CONF) &
537 CSI_SENS_CONF_SENS_PRTCL_MASK) >>
538 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
539 spin_unlock_irqrestore(&csi->lock, flags);
540
541 switch (sensor_protocol) {
542 case IPU_CSI_CLK_MODE_GATED_CLK:
543 case IPU_CSI_CLK_MODE_NONGATED_CLK:
544 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
545 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
546 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
547 return false;
548 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
549 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
550 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
551 return true;
552 default:
553 dev_err(csi->ipu->dev,
554 "CSI %d sensor protocol unsupported\n", csi->id);
555 return false;
556 }
557}
558EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
559
560void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
561{
562 unsigned long flags;
563 u32 reg;
564
565 spin_lock_irqsave(&csi->lock, flags);
566
567 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
568 w->width = (reg & 0xFFFF) + 1;
569 w->height = (reg >> 16 & 0xFFFF) + 1;
570
571 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
572 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
573 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
574
575 spin_unlock_irqrestore(&csi->lock, flags);
576}
577EXPORT_SYMBOL_GPL(ipu_csi_get_window);
578
579void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
580{
581 unsigned long flags;
582 u32 reg;
583
584 spin_lock_irqsave(&csi->lock, flags);
585
586 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
587 CSI_ACT_FRM_SIZE);
588
589 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
590 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
591 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
592 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
593
594 spin_unlock_irqrestore(&csi->lock, flags);
595}
596EXPORT_SYMBOL_GPL(ipu_csi_set_window);
597
598void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
599{
600 unsigned long flags;
601 u32 reg;
602
603 spin_lock_irqsave(&csi->lock, flags);
604
605 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
606 reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
607 reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
608 (vert ? CSI_VERT_DOWNSIZE_EN : 0);
609 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
610
611 spin_unlock_irqrestore(&csi->lock, flags);
612}
613EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
614
615void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
616 u32 r_value, u32 g_value, u32 b_value,
617 u32 pix_clk)
618{
619 unsigned long flags;
620 u32 ipu_clk = clk_get_rate(csi->clk_ipu);
621 u32 temp;
622
623 spin_lock_irqsave(&csi->lock, flags);
624
625 temp = ipu_csi_read(csi, CSI_TST_CTRL);
626
627 if (!active) {
628 temp &= ~CSI_TEST_GEN_MODE_EN;
629 ipu_csi_write(csi, temp, CSI_TST_CTRL);
630 } else {
631
632 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
633
634 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
635 CSI_TEST_GEN_B_MASK);
636 temp |= CSI_TEST_GEN_MODE_EN;
637 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
638 (g_value << CSI_TEST_GEN_G_SHIFT) |
639 (b_value << CSI_TEST_GEN_B_SHIFT);
640 ipu_csi_write(csi, temp, CSI_TST_CTRL);
641 }
642
643 spin_unlock_irqrestore(&csi->lock, flags);
644}
645EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
646
647int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
648 struct v4l2_mbus_framefmt *mbus_fmt)
649{
650 struct ipu_csi_bus_config cfg;
651 unsigned long flags;
652 u32 temp;
653 int ret;
654
655 if (vc > 3)
656 return -EINVAL;
657
658 ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2_DPHY);
659 if (ret < 0)
660 return ret;
661
662 spin_lock_irqsave(&csi->lock, flags);
663
664 temp = ipu_csi_read(csi, CSI_MIPI_DI);
665 temp &= ~(0xff << (vc * 8));
666 temp |= (cfg.mipi_dt << (vc * 8));
667 ipu_csi_write(csi, temp, CSI_MIPI_DI);
668
669 spin_unlock_irqrestore(&csi->lock, flags);
670
671 return 0;
672}
673EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
674
675int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
676 u32 max_ratio, u32 id)
677{
678 unsigned long flags;
679 u32 temp;
680
681 if (max_ratio > 5 || id > 3)
682 return -EINVAL;
683
684 spin_lock_irqsave(&csi->lock, flags);
685
686 temp = ipu_csi_read(csi, CSI_SKIP);
687 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
688 CSI_SKIP_SMFC_MASK);
689 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
690 (id << CSI_ID_2_SKIP_SHIFT) |
691 (skip << CSI_SKIP_SMFC_SHIFT);
692 ipu_csi_write(csi, temp, CSI_SKIP);
693
694 spin_unlock_irqrestore(&csi->lock, flags);
695
696 return 0;
697}
698EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
699
700int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
701{
702 unsigned long flags;
703 u32 csi_sens_conf, dest;
704
705 if (csi_dest == IPU_CSI_DEST_IDMAC)
706 dest = CSI_DATA_DEST_IDMAC;
707 else
708 dest = CSI_DATA_DEST_IC;
709
710 spin_lock_irqsave(&csi->lock, flags);
711
712 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
713 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
714 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
715 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
716
717 spin_unlock_irqrestore(&csi->lock, flags);
718
719 return 0;
720}
721EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
722
723int ipu_csi_enable(struct ipu_csi *csi)
724{
725 ipu_module_enable(csi->ipu, csi->module);
726
727 return 0;
728}
729EXPORT_SYMBOL_GPL(ipu_csi_enable);
730
731int ipu_csi_disable(struct ipu_csi *csi)
732{
733 ipu_module_disable(csi->ipu, csi->module);
734
735 return 0;
736}
737EXPORT_SYMBOL_GPL(ipu_csi_disable);
738
739struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
740{
741 unsigned long flags;
742 struct ipu_csi *csi, *ret;
743
744 if (id > 1)
745 return ERR_PTR(-EINVAL);
746
747 csi = ipu->csi_priv[id];
748 ret = csi;
749
750 spin_lock_irqsave(&csi->lock, flags);
751
752 if (csi->inuse) {
753 ret = ERR_PTR(-EBUSY);
754 goto unlock;
755 }
756
757 csi->inuse = true;
758unlock:
759 spin_unlock_irqrestore(&csi->lock, flags);
760 return ret;
761}
762EXPORT_SYMBOL_GPL(ipu_csi_get);
763
764void ipu_csi_put(struct ipu_csi *csi)
765{
766 unsigned long flags;
767
768 spin_lock_irqsave(&csi->lock, flags);
769 csi->inuse = false;
770 spin_unlock_irqrestore(&csi->lock, flags);
771}
772EXPORT_SYMBOL_GPL(ipu_csi_put);
773
774int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
775 unsigned long base, u32 module, struct clk *clk_ipu)
776{
777 struct ipu_csi *csi;
778
779 if (id > 1)
780 return -ENODEV;
781
782 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
783 if (!csi)
784 return -ENOMEM;
785
786 ipu->csi_priv[id] = csi;
787
788 spin_lock_init(&csi->lock);
789 csi->module = module;
790 csi->id = id;
791 csi->clk_ipu = clk_ipu;
792 csi->base = devm_ioremap(dev, base, PAGE_SIZE);
793 if (!csi->base)
794 return -ENOMEM;
795
796 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
797 id, base, csi->base);
798 csi->ipu = ipu;
799
800 return 0;
801}
802
803void ipu_csi_exit(struct ipu_soc *ipu, int id)
804{
805}
806
807void ipu_csi_dump(struct ipu_csi *csi)
808{
809 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
810 ipu_csi_read(csi, CSI_SENS_CONF));
811 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
812 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
813 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
814 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
815 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
816 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
817 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
818 ipu_csi_read(csi, CSI_TST_CTRL));
819 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
820 ipu_csi_read(csi, CSI_CCIR_CODE_1));
821 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
822 ipu_csi_read(csi, CSI_CCIR_CODE_2));
823 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
824 ipu_csi_read(csi, CSI_CCIR_CODE_3));
825 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
826 ipu_csi_read(csi, CSI_MIPI_DI));
827 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
828 ipu_csi_read(csi, CSI_SKIP));
829}
830EXPORT_SYMBOL_GPL(ipu_csi_dump);
831
