1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/errno.h>
25#include <linux/io.h>
26#include <linux/io-pgtable.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/spinlock.h>
30#include <linux/slab.h>
31#include <linux/iommu.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/of_iommu.h>
35
36#include <asm/cacheflush.h>
37#include <asm/sizes.h>
38
39#include "msm_iommu_hw-8xxx.h"
40#include "msm_iommu.h"
41
42#define MRC(reg, processor, op1, crn, crm, op2) \
43__asm__ __volatile__ ( \
44" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
45: "=r" (reg))
46
47
48#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
49
50DEFINE_SPINLOCK(msm_iommu_lock);
51static LIST_HEAD(qcom_iommu_devices);
52static struct iommu_ops msm_iommu_ops;
53
54struct msm_priv {
55 struct list_head list_attached;
56 struct iommu_domain domain;
57 struct io_pgtable_cfg cfg;
58 struct io_pgtable_ops *iop;
59 struct device *dev;
60 spinlock_t pgtlock;
61};
62
63static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
64{
65 return container_of(dom, struct msm_priv, domain);
66}
67
68static int __enable_clocks(struct msm_iommu_dev *iommu)
69{
70 int ret;
71
72 ret = clk_enable(iommu->pclk);
73 if (ret)
74 goto fail;
75
76 if (iommu->clk) {
77 ret = clk_enable(iommu->clk);
78 if (ret)
79 clk_disable(iommu->pclk);
80 }
81fail:
82 return ret;
83}
84
85static void __disable_clocks(struct msm_iommu_dev *iommu)
86{
87 if (iommu->clk)
88 clk_disable(iommu->clk);
89 clk_disable(iommu->pclk);
90}
91
92static void msm_iommu_reset(void __iomem *base, int ncb)
93{
94 int ctx;
95
96 SET_RPUE(base, 0);
97 SET_RPUEIE(base, 0);
98 SET_ESRRESTORE(base, 0);
99 SET_TBE(base, 0);
100 SET_CR(base, 0);
101 SET_SPDMBE(base, 0);
102 SET_TESTBUSCR(base, 0);
103 SET_TLBRSW(base, 0);
104 SET_GLOBAL_TLBIALL(base, 0);
105 SET_RPU_ACR(base, 0);
106 SET_TLBLKCRWE(base, 1);
107
108 for (ctx = 0; ctx < ncb; ctx++) {
109 SET_BPRCOSH(base, ctx, 0);
110 SET_BPRCISH(base, ctx, 0);
111 SET_BPRCNSH(base, ctx, 0);
112 SET_BPSHCFG(base, ctx, 0);
113 SET_BPMTCFG(base, ctx, 0);
114 SET_ACTLR(base, ctx, 0);
115 SET_SCTLR(base, ctx, 0);
116 SET_FSRRESTORE(base, ctx, 0);
117 SET_TTBR0(base, ctx, 0);
118 SET_TTBR1(base, ctx, 0);
119 SET_TTBCR(base, ctx, 0);
120 SET_BFBCR(base, ctx, 0);
121 SET_PAR(base, ctx, 0);
122 SET_FAR(base, ctx, 0);
123 SET_CTX_TLBIALL(base, ctx, 0);
124 SET_TLBFLPTER(base, ctx, 0);
125 SET_TLBSLPTER(base, ctx, 0);
126 SET_TLBLKCR(base, ctx, 0);
127 SET_CONTEXTIDR(base, ctx, 0);
128 }
129}
130
131static void __flush_iotlb(void *cookie)
132{
133 struct msm_priv *priv = cookie;
134 struct msm_iommu_dev *iommu = NULL;
135 struct msm_iommu_ctx_dev *master;
136 int ret = 0;
137
138 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
139 ret = __enable_clocks(iommu);
140 if (ret)
141 goto fail;
142
143 list_for_each_entry(master, &iommu->ctx_list, list)
144 SET_CTX_TLBIALL(iommu->base, master->num, 0);
145
146 __disable_clocks(iommu);
147 }
148fail:
149 return;
150}
151
152static void __flush_iotlb_range(unsigned long iova, size_t size,
153 size_t granule, bool leaf, void *cookie)
154{
155 struct msm_priv *priv = cookie;
156 struct msm_iommu_dev *iommu = NULL;
157 struct msm_iommu_ctx_dev *master;
158 int ret = 0;
159 int temp_size;
160
161 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
162 ret = __enable_clocks(iommu);
163 if (ret)
164 goto fail;
165
166 list_for_each_entry(master, &iommu->ctx_list, list) {
167 temp_size = size;
168 do {
169 iova &= TLBIVA_VA;
170 iova |= GET_CONTEXTIDR_ASID(iommu->base,
171 master->num);
172 SET_TLBIVA(iommu->base, master->num, iova);
173 iova += granule;
174 } while (temp_size -= granule);
175 }
176
177 __disable_clocks(iommu);
178 }
179
180fail:
181 return;
182}
183
184static void __flush_iotlb_sync(void *cookie)
185{
186
187
188
189
190
191
192}
193
194static const struct iommu_gather_ops msm_iommu_gather_ops = {
195 .tlb_flush_all = __flush_iotlb,
196 .tlb_add_flush = __flush_iotlb_range,
197 .tlb_sync = __flush_iotlb_sync,
198};
199
200static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
201{
202 int idx;
203
204 do {
205 idx = find_next_zero_bit(map, end, start);
206 if (idx == end)
207 return -ENOSPC;
208 } while (test_and_set_bit(idx, map));
209
210 return idx;
211}
212
213static void msm_iommu_free_ctx(unsigned long *map, int idx)
214{
215 clear_bit(idx, map);
216}
217
218static void config_mids(struct msm_iommu_dev *iommu,
219 struct msm_iommu_ctx_dev *master)
220{
221 int mid, ctx, i;
222
223 for (i = 0; i < master->num_mids; i++) {
224 mid = master->mids[i];
225 ctx = master->num;
226
227 SET_M2VCBR_N(iommu->base, mid, 0);
228 SET_CBACR_N(iommu->base, ctx, 0);
229
230
231 SET_VMID(iommu->base, mid, 0);
232
233
234 SET_CBNDX(iommu->base, mid, ctx);
235
236
237 SET_CBVMID(iommu->base, ctx, 0);
238
239
240 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
241
242
243 SET_NSCFG(iommu->base, mid, 3);
244 }
245}
246
247static void __reset_context(void __iomem *base, int ctx)
248{
249 SET_BPRCOSH(base, ctx, 0);
250 SET_BPRCISH(base, ctx, 0);
251 SET_BPRCNSH(base, ctx, 0);
252 SET_BPSHCFG(base, ctx, 0);
253 SET_BPMTCFG(base, ctx, 0);
254 SET_ACTLR(base, ctx, 0);
255 SET_SCTLR(base, ctx, 0);
256 SET_FSRRESTORE(base, ctx, 0);
257 SET_TTBR0(base, ctx, 0);
258 SET_TTBR1(base, ctx, 0);
259 SET_TTBCR(base, ctx, 0);
260 SET_BFBCR(base, ctx, 0);
261 SET_PAR(base, ctx, 0);
262 SET_FAR(base, ctx, 0);
263 SET_CTX_TLBIALL(base, ctx, 0);
264 SET_TLBFLPTER(base, ctx, 0);
265 SET_TLBSLPTER(base, ctx, 0);
266 SET_TLBLKCR(base, ctx, 0);
267}
268
269static void __program_context(void __iomem *base, int ctx,
270 struct msm_priv *priv)
271{
272 __reset_context(base, ctx);
273
274
275 SET_TRE(base, ctx, 1);
276 SET_AFE(base, ctx, 1);
277
278
279
280 SET_TLBMCFG(base, ctx, 0x3);
281
282
283 SET_V2PCFG(base, ctx, 0x3);
284
285 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
286 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]);
287 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]);
288
289
290 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
291 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
292
293
294 SET_CTX_TLBIALL(base, ctx, 0);
295
296
297 SET_IRPTNDX(base, ctx, 0);
298
299
300 SET_CFEIE(base, ctx, 1);
301
302
303 SET_CFCFG(base, ctx, 1);
304
305
306 SET_RCISH(base, ctx, 1);
307 SET_RCOSH(base, ctx, 1);
308 SET_RCNSH(base, ctx, 1);
309
310
311 SET_BFBDFE(base, ctx, 1);
312
313
314 SET_M(base, ctx, 1);
315}
316
317static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
318{
319 struct msm_priv *priv;
320
321 if (type != IOMMU_DOMAIN_UNMANAGED)
322 return NULL;
323
324 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
325 if (!priv)
326 goto fail_nomem;
327
328 INIT_LIST_HEAD(&priv->list_attached);
329
330 priv->domain.geometry.aperture_start = 0;
331 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
332 priv->domain.geometry.force_aperture = true;
333
334 return &priv->domain;
335
336fail_nomem:
337 kfree(priv);
338 return NULL;
339}
340
341static void msm_iommu_domain_free(struct iommu_domain *domain)
342{
343 struct msm_priv *priv;
344 unsigned long flags;
345
346 spin_lock_irqsave(&msm_iommu_lock, flags);
347 priv = to_msm_priv(domain);
348 kfree(priv);
349 spin_unlock_irqrestore(&msm_iommu_lock, flags);
350}
351
352static int msm_iommu_domain_config(struct msm_priv *priv)
353{
354 spin_lock_init(&priv->pgtlock);
355
356 priv->cfg = (struct io_pgtable_cfg) {
357 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP,
358 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
359 .ias = 32,
360 .oas = 32,
361 .tlb = &msm_iommu_gather_ops,
362 .iommu_dev = priv->dev,
363 };
364
365 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
366 if (!priv->iop) {
367 dev_err(priv->dev, "Failed to allocate pgtable\n");
368 return -EINVAL;
369 }
370
371 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
372
373 return 0;
374}
375
376
377static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
378{
379 struct msm_iommu_dev *iommu, *ret = NULL;
380 struct msm_iommu_ctx_dev *master;
381
382 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
383 master = list_first_entry(&iommu->ctx_list,
384 struct msm_iommu_ctx_dev,
385 list);
386 if (master->of_node == dev->of_node) {
387 ret = iommu;
388 break;
389 }
390 }
391
392 return ret;
393}
394
395static int msm_iommu_add_device(struct device *dev)
396{
397 struct msm_iommu_dev *iommu;
398 struct iommu_group *group;
399 unsigned long flags;
400
401 spin_lock_irqsave(&msm_iommu_lock, flags);
402 iommu = find_iommu_for_dev(dev);
403 spin_unlock_irqrestore(&msm_iommu_lock, flags);
404
405 if (iommu)
406 iommu_device_link(&iommu->iommu, dev);
407 else
408 return -ENODEV;
409
410 group = iommu_group_get_for_dev(dev);
411 if (IS_ERR(group))
412 return PTR_ERR(group);
413
414 iommu_group_put(group);
415
416 return 0;
417}
418
419static void msm_iommu_remove_device(struct device *dev)
420{
421 struct msm_iommu_dev *iommu;
422 unsigned long flags;
423
424 spin_lock_irqsave(&msm_iommu_lock, flags);
425 iommu = find_iommu_for_dev(dev);
426 spin_unlock_irqrestore(&msm_iommu_lock, flags);
427
428 if (iommu)
429 iommu_device_unlink(&iommu->iommu, dev);
430
431 iommu_group_remove_device(dev);
432}
433
434static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
435{
436 int ret = 0;
437 unsigned long flags;
438 struct msm_iommu_dev *iommu;
439 struct msm_priv *priv = to_msm_priv(domain);
440 struct msm_iommu_ctx_dev *master;
441
442 priv->dev = dev;
443 msm_iommu_domain_config(priv);
444
445 spin_lock_irqsave(&msm_iommu_lock, flags);
446 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
447 master = list_first_entry(&iommu->ctx_list,
448 struct msm_iommu_ctx_dev,
449 list);
450 if (master->of_node == dev->of_node) {
451 ret = __enable_clocks(iommu);
452 if (ret)
453 goto fail;
454
455 list_for_each_entry(master, &iommu->ctx_list, list) {
456 if (master->num) {
457 dev_err(dev, "domain already attached");
458 ret = -EEXIST;
459 goto fail;
460 }
461 master->num =
462 msm_iommu_alloc_ctx(iommu->context_map,
463 0, iommu->ncb);
464 if (IS_ERR_VALUE(master->num)) {
465 ret = -ENODEV;
466 goto fail;
467 }
468 config_mids(iommu, master);
469 __program_context(iommu->base, master->num,
470 priv);
471 }
472 __disable_clocks(iommu);
473 list_add(&iommu->dom_node, &priv->list_attached);
474 }
475 }
476
477fail:
478 spin_unlock_irqrestore(&msm_iommu_lock, flags);
479
480 return ret;
481}
482
483static void msm_iommu_detach_dev(struct iommu_domain *domain,
484 struct device *dev)
485{
486 struct msm_priv *priv = to_msm_priv(domain);
487 unsigned long flags;
488 struct msm_iommu_dev *iommu;
489 struct msm_iommu_ctx_dev *master;
490 int ret;
491
492 free_io_pgtable_ops(priv->iop);
493
494 spin_lock_irqsave(&msm_iommu_lock, flags);
495 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
496 ret = __enable_clocks(iommu);
497 if (ret)
498 goto fail;
499
500 list_for_each_entry(master, &iommu->ctx_list, list) {
501 msm_iommu_free_ctx(iommu->context_map, master->num);
502 __reset_context(iommu->base, master->num);
503 }
504 __disable_clocks(iommu);
505 }
506fail:
507 spin_unlock_irqrestore(&msm_iommu_lock, flags);
508}
509
510static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
511 phys_addr_t pa, size_t len, int prot)
512{
513 struct msm_priv *priv = to_msm_priv(domain);
514 unsigned long flags;
515 int ret;
516
517 spin_lock_irqsave(&priv->pgtlock, flags);
518 ret = priv->iop->map(priv->iop, iova, pa, len, prot);
519 spin_unlock_irqrestore(&priv->pgtlock, flags);
520
521 return ret;
522}
523
524static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
525 size_t len)
526{
527 struct msm_priv *priv = to_msm_priv(domain);
528 unsigned long flags;
529
530 spin_lock_irqsave(&priv->pgtlock, flags);
531 len = priv->iop->unmap(priv->iop, iova, len);
532 spin_unlock_irqrestore(&priv->pgtlock, flags);
533
534 return len;
535}
536
537static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
538 dma_addr_t va)
539{
540 struct msm_priv *priv;
541 struct msm_iommu_dev *iommu;
542 struct msm_iommu_ctx_dev *master;
543 unsigned int par;
544 unsigned long flags;
545 phys_addr_t ret = 0;
546
547 spin_lock_irqsave(&msm_iommu_lock, flags);
548
549 priv = to_msm_priv(domain);
550 iommu = list_first_entry(&priv->list_attached,
551 struct msm_iommu_dev, dom_node);
552
553 if (list_empty(&iommu->ctx_list))
554 goto fail;
555
556 master = list_first_entry(&iommu->ctx_list,
557 struct msm_iommu_ctx_dev, list);
558 if (!master)
559 goto fail;
560
561 ret = __enable_clocks(iommu);
562 if (ret)
563 goto fail;
564
565
566 SET_CTX_TLBIALL(iommu->base, master->num, 0);
567 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
568
569 par = GET_PAR(iommu->base, master->num);
570
571
572 if (GET_NOFAULT_SS(iommu->base, master->num))
573 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
574 else
575 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
576
577 if (GET_FAULT(iommu->base, master->num))
578 ret = 0;
579
580 __disable_clocks(iommu);
581fail:
582 spin_unlock_irqrestore(&msm_iommu_lock, flags);
583 return ret;
584}
585
586static bool msm_iommu_capable(enum iommu_cap cap)
587{
588 return false;
589}
590
591static void print_ctx_regs(void __iomem *base, int ctx)
592{
593 unsigned int fsr = GET_FSR(base, ctx);
594 pr_err("FAR = %08x PAR = %08x\n",
595 GET_FAR(base, ctx), GET_PAR(base, ctx));
596 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
597 (fsr & 0x02) ? "TF " : "",
598 (fsr & 0x04) ? "AFF " : "",
599 (fsr & 0x08) ? "APF " : "",
600 (fsr & 0x10) ? "TLBMF " : "",
601 (fsr & 0x20) ? "HTWDEEF " : "",
602 (fsr & 0x40) ? "HTWSEEF " : "",
603 (fsr & 0x80) ? "MHF " : "",
604 (fsr & 0x10000) ? "SL " : "",
605 (fsr & 0x40000000) ? "SS " : "",
606 (fsr & 0x80000000) ? "MULTI " : "");
607
608 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
609 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
610 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
611 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
612 pr_err("SCTLR = %08x ACTLR = %08x\n",
613 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
614}
615
616static void insert_iommu_master(struct device *dev,
617 struct msm_iommu_dev **iommu,
618 struct of_phandle_args *spec)
619{
620 struct msm_iommu_ctx_dev *master = dev->archdata.iommu;
621 int sid;
622
623 if (list_empty(&(*iommu)->ctx_list)) {
624 master = kzalloc(sizeof(*master), GFP_ATOMIC);
625 master->of_node = dev->of_node;
626 list_add(&master->list, &(*iommu)->ctx_list);
627 dev->archdata.iommu = master;
628 }
629
630 for (sid = 0; sid < master->num_mids; sid++)
631 if (master->mids[sid] == spec->args[0]) {
632 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
633 sid);
634 return;
635 }
636
637 master->mids[master->num_mids++] = spec->args[0];
638}
639
640static int qcom_iommu_of_xlate(struct device *dev,
641 struct of_phandle_args *spec)
642{
643 struct msm_iommu_dev *iommu;
644 unsigned long flags;
645 int ret = 0;
646
647 spin_lock_irqsave(&msm_iommu_lock, flags);
648 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
649 if (iommu->dev->of_node == spec->np)
650 break;
651
652 if (!iommu || iommu->dev->of_node != spec->np) {
653 ret = -ENODEV;
654 goto fail;
655 }
656
657 insert_iommu_master(dev, &iommu, spec);
658fail:
659 spin_unlock_irqrestore(&msm_iommu_lock, flags);
660
661 return ret;
662}
663
664irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
665{
666 struct msm_iommu_dev *iommu = dev_id;
667 unsigned int fsr;
668 int i, ret;
669
670 spin_lock(&msm_iommu_lock);
671
672 if (!iommu) {
673 pr_err("Invalid device ID in context interrupt handler\n");
674 goto fail;
675 }
676
677 pr_err("Unexpected IOMMU page fault!\n");
678 pr_err("base = %08x\n", (unsigned int)iommu->base);
679
680 ret = __enable_clocks(iommu);
681 if (ret)
682 goto fail;
683
684 for (i = 0; i < iommu->ncb; i++) {
685 fsr = GET_FSR(iommu->base, i);
686 if (fsr) {
687 pr_err("Fault occurred in context %d.\n", i);
688 pr_err("Interesting registers:\n");
689 print_ctx_regs(iommu->base, i);
690 SET_FSR(iommu->base, i, 0x4000000F);
691 }
692 }
693 __disable_clocks(iommu);
694fail:
695 spin_unlock(&msm_iommu_lock);
696 return 0;
697}
698
699static struct iommu_ops msm_iommu_ops = {
700 .capable = msm_iommu_capable,
701 .domain_alloc = msm_iommu_domain_alloc,
702 .domain_free = msm_iommu_domain_free,
703 .attach_dev = msm_iommu_attach_dev,
704 .detach_dev = msm_iommu_detach_dev,
705 .map = msm_iommu_map,
706 .unmap = msm_iommu_unmap,
707 .iova_to_phys = msm_iommu_iova_to_phys,
708 .add_device = msm_iommu_add_device,
709 .remove_device = msm_iommu_remove_device,
710 .device_group = generic_device_group,
711 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
712 .of_xlate = qcom_iommu_of_xlate,
713};
714
715static int msm_iommu_probe(struct platform_device *pdev)
716{
717 struct resource *r;
718 resource_size_t ioaddr;
719 struct msm_iommu_dev *iommu;
720 int ret, par, val;
721
722 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
723 if (!iommu)
724 return -ENODEV;
725
726 iommu->dev = &pdev->dev;
727 INIT_LIST_HEAD(&iommu->ctx_list);
728
729 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
730 if (IS_ERR(iommu->pclk)) {
731 dev_err(iommu->dev, "could not get smmu_pclk\n");
732 return PTR_ERR(iommu->pclk);
733 }
734
735 ret = clk_prepare(iommu->pclk);
736 if (ret) {
737 dev_err(iommu->dev, "could not prepare smmu_pclk\n");
738 return ret;
739 }
740
741 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
742 if (IS_ERR(iommu->clk)) {
743 dev_err(iommu->dev, "could not get iommu_clk\n");
744 clk_unprepare(iommu->pclk);
745 return PTR_ERR(iommu->clk);
746 }
747
748 ret = clk_prepare(iommu->clk);
749 if (ret) {
750 dev_err(iommu->dev, "could not prepare iommu_clk\n");
751 clk_unprepare(iommu->pclk);
752 return ret;
753 }
754
755 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
756 iommu->base = devm_ioremap_resource(iommu->dev, r);
757 if (IS_ERR(iommu->base)) {
758 dev_err(iommu->dev, "could not get iommu base\n");
759 ret = PTR_ERR(iommu->base);
760 goto fail;
761 }
762 ioaddr = r->start;
763
764 iommu->irq = platform_get_irq(pdev, 0);
765 if (iommu->irq < 0) {
766 dev_err(iommu->dev, "could not get iommu irq\n");
767 ret = -ENODEV;
768 goto fail;
769 }
770
771 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
772 if (ret) {
773 dev_err(iommu->dev, "could not get ncb\n");
774 goto fail;
775 }
776 iommu->ncb = val;
777
778 msm_iommu_reset(iommu->base, iommu->ncb);
779 SET_M(iommu->base, 0, 1);
780 SET_PAR(iommu->base, 0, 0);
781 SET_V2PCFG(iommu->base, 0, 1);
782 SET_V2PPR(iommu->base, 0, 0);
783 par = GET_PAR(iommu->base, 0);
784 SET_V2PCFG(iommu->base, 0, 0);
785 SET_M(iommu->base, 0, 0);
786
787 if (!par) {
788 pr_err("Invalid PAR value detected\n");
789 ret = -ENODEV;
790 goto fail;
791 }
792
793 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
794 msm_iommu_fault_handler,
795 IRQF_ONESHOT | IRQF_SHARED,
796 "msm_iommu_secure_irpt_handler",
797 iommu);
798 if (ret) {
799 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
800 goto fail;
801 }
802
803 list_add(&iommu->dev_node, &qcom_iommu_devices);
804
805 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
806 "msm-smmu.%pa", &ioaddr);
807 if (ret) {
808 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
809 goto fail;
810 }
811
812 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops);
813 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);
814
815 ret = iommu_device_register(&iommu->iommu);
816 if (ret) {
817 pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
818 goto fail;
819 }
820
821 bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
822
823 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
824 iommu->base, iommu->irq, iommu->ncb);
825
826 return ret;
827fail:
828 clk_unprepare(iommu->clk);
829 clk_unprepare(iommu->pclk);
830 return ret;
831}
832
833static const struct of_device_id msm_iommu_dt_match[] = {
834 { .compatible = "qcom,apq8064-iommu" },
835 {}
836};
837
838static int msm_iommu_remove(struct platform_device *pdev)
839{
840 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
841
842 clk_unprepare(iommu->clk);
843 clk_unprepare(iommu->pclk);
844 return 0;
845}
846
847static struct platform_driver msm_iommu_driver = {
848 .driver = {
849 .name = "msm_iommu",
850 .of_match_table = msm_iommu_dt_match,
851 },
852 .probe = msm_iommu_probe,
853 .remove = msm_iommu_remove,
854};
855
856static int __init msm_iommu_driver_init(void)
857{
858 int ret;
859
860 ret = platform_driver_register(&msm_iommu_driver);
861 if (ret != 0)
862 pr_err("Failed to register IOMMU driver\n");
863
864 return ret;
865}
866subsys_initcall(msm_iommu_driver_init);
867
868
