LXR linux/drivers/media/platform/omap3isp/isp.h

   1/*
   2 * isp.h
   3 *
   4 * TI OMAP3 ISP - Core
   5 *
   6 * Copyright (C) 2009-2010 Nokia Corporation
   7 * Copyright (C) 2009 Texas Instruments, Inc.
   8 *
   9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10 *           Sakari Ailus <sakari.ailus@iki.fi>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 */
  16
  17#ifndef OMAP3_ISP_CORE_H
  18#define OMAP3_ISP_CORE_H
  19
  20#include <media/media-entity.h>
  21#include <media/v4l2-async.h>
  22#include <media/v4l2-device.h>
  23#include <linux/clk-provider.h>
  24#include <linux/device.h>
  25#include <linux/io.h>
  26#include <linux/platform_device.h>
  27#include <linux/wait.h>
  28
  29#include "omap3isp.h"
  30#include "ispstat.h"
  31#include "ispccdc.h"
  32#include "ispreg.h"
  33#include "ispresizer.h"
  34#include "isppreview.h"
  35#include "ispcsiphy.h"
  36#include "ispcsi2.h"
  37#include "ispccp2.h"
  38
  39#define ISP_TOK_TERM            0xFFFFFFFF      /*
  40                                                 * terminating token for ISP
  41                                                 * modules reg list
  42                                                 */
  43#define to_isp_device(ptr_module)                               \
  44        container_of(ptr_module, struct isp_device, isp_##ptr_module)
  45#define to_device(ptr_module)                                           \
  46        (to_isp_device(ptr_module)->dev)
  47
  48enum isp_mem_resources {
  49        OMAP3_ISP_IOMEM_MAIN,
  50        OMAP3_ISP_IOMEM_CCP2,
  51        OMAP3_ISP_IOMEM_CCDC,
  52        OMAP3_ISP_IOMEM_HIST,
  53        OMAP3_ISP_IOMEM_H3A,
  54        OMAP3_ISP_IOMEM_PREV,
  55        OMAP3_ISP_IOMEM_RESZ,
  56        OMAP3_ISP_IOMEM_SBL,
  57        OMAP3_ISP_IOMEM_CSI2A_REGS1,
  58        OMAP3_ISP_IOMEM_CSIPHY2,
  59        OMAP3_ISP_IOMEM_CSI2A_REGS2,
  60        OMAP3_ISP_IOMEM_CSI2C_REGS1,
  61        OMAP3_ISP_IOMEM_CSIPHY1,
  62        OMAP3_ISP_IOMEM_CSI2C_REGS2,
  63        OMAP3_ISP_IOMEM_LAST
  64};
  65
  66enum isp_sbl_resource {
  67        OMAP3_ISP_SBL_CSI1_READ         = 0x1,
  68        OMAP3_ISP_SBL_CSI1_WRITE        = 0x2,
  69        OMAP3_ISP_SBL_CSI2A_WRITE       = 0x4,
  70        OMAP3_ISP_SBL_CSI2C_WRITE       = 0x8,
  71        OMAP3_ISP_SBL_CCDC_LSC_READ     = 0x10,
  72        OMAP3_ISP_SBL_CCDC_WRITE        = 0x20,
  73        OMAP3_ISP_SBL_PREVIEW_READ      = 0x40,
  74        OMAP3_ISP_SBL_PREVIEW_WRITE     = 0x80,
  75        OMAP3_ISP_SBL_RESIZER_READ      = 0x100,
  76        OMAP3_ISP_SBL_RESIZER_WRITE     = 0x200,
  77};
  78
  79enum isp_subclk_resource {
  80        OMAP3_ISP_SUBCLK_CCDC           = (1 << 0),
  81        OMAP3_ISP_SUBCLK_AEWB           = (1 << 1),
  82        OMAP3_ISP_SUBCLK_AF             = (1 << 2),
  83        OMAP3_ISP_SUBCLK_HIST           = (1 << 3),
  84        OMAP3_ISP_SUBCLK_PREVIEW        = (1 << 4),
  85        OMAP3_ISP_SUBCLK_RESIZER        = (1 << 5),
  86};
  87
  88/* ISP: OMAP 34xx ES 1.0 */
  89#define ISP_REVISION_1_0                0x10
  90/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
  91#define ISP_REVISION_2_0                0x20
  92/* ISP2P: OMAP 36xx */
  93#define ISP_REVISION_15_0               0xF0
  94
  95#define ISP_PHY_TYPE_3430               0
  96#define ISP_PHY_TYPE_3630               1
  97
  98struct regmap;
  99
 100/*
 101 * struct isp_res_mapping - Map ISP io resources to ISP revision.
 102 * @isp_rev: ISP_REVISION_x_x
 103 * @offset: register offsets of various ISP sub-blocks
 104 * @phy_type: ISP_PHY_TYPE_{3430,3630}
 105 */
 106struct isp_res_mapping {
 107        u32 isp_rev;
 108        u32 offset[OMAP3_ISP_IOMEM_LAST];
 109        u32 phy_type;
 110};
 111
 112/*
 113 * struct isp_reg - Structure for ISP register values.
 114 * @reg: 32-bit Register address.
 115 * @val: 32-bit Register value.
 116 */
 117struct isp_reg {
 118        enum isp_mem_resources mmio_range;
 119        u32 reg;
 120        u32 val;
 121};
 122
 123enum isp_xclk_id {
 124        ISP_XCLK_A,
 125        ISP_XCLK_B,
 126};
 127
 128struct isp_xclk {
 129        struct isp_device *isp;
 130        struct clk_hw hw;
 131        struct clk *clk;
 132        enum isp_xclk_id id;
 133
 134        spinlock_t lock;        /* Protects enabled and divider */
 135        bool enabled;
 136        unsigned int divider;
 137};
 138
 139/*
 140 * struct isp_device - ISP device structure.
 141 * @dev: Device pointer specific to the OMAP3 ISP.
 142 * @revision: Stores current ISP module revision.
 143 * @irq_num: Currently used IRQ number.
 144 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 145 *             regions.
 146 * @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register
 147 *                       region.
 148 * @syscon: Regmap for the syscon register space
 149 * @syscon_offset: Offset of the CSIPHY control register in syscon
 150 * @phy_type: ISP_PHY_TYPE_{3430,3630}
 151 * @mapping: IOMMU mapping
 152 * @stat_lock: Spinlock for handling statistics
 153 * @isp_mutex: Mutex for serializing requests to ISP.
 154 * @stop_failure: Indicates that an entity failed to stop.
 155 * @crashed: Crashed ent_enum
 156 * @has_context: Context has been saved at least once and can be restored.
 157 * @ref_count: Reference count for handling multiple ISP requests.
 158 * @cam_ick: Pointer to camera interface clock structure.
 159 * @cam_mclk: Pointer to camera functional clock structure.
 160 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 161 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 162 * @xclks: External clocks provided by the ISP
 163 * @irq: Currently attached ISP ISR callbacks information structure.
 164 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 165 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 166 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 167 *           White Balance SCM.
 168 * @isp_res: Pointer to current settings for ISP Resizer.
 169 * @isp_prev: Pointer to current settings for ISP Preview.
 170 * @isp_ccdc: Pointer to current settings for ISP CCDC.
 171 * @platform_cb: ISP driver callback function pointers for platform code
 172 *
 173 * This structure is used to store the OMAP ISP Information.
 174 */
 175struct isp_device {
 176        struct v4l2_device v4l2_dev;
 177        struct v4l2_async_notifier notifier;
 178        struct media_device media_dev;
 179        struct device *dev;
 180        u32 revision;
 181
 182        /* platform HW resources */
 183        unsigned int irq_num;
 184
 185        void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
 186        unsigned long mmio_hist_base_phys;
 187        struct regmap *syscon;
 188        u32 syscon_offset;
 189        u32 phy_type;
 190
 191        struct dma_iommu_mapping *mapping;
 192
 193        /* ISP Obj */
 194        spinlock_t stat_lock;   /* common lock for statistic drivers */
 195        struct mutex isp_mutex; /* For handling ref_count field */
 196        bool stop_failure;
 197        struct media_entity_enum crashed;
 198        int has_context;
 199        int ref_count;
 200        unsigned int autoidle;
 201#define ISP_CLK_CAM_ICK         0
 202#define ISP_CLK_CAM_MCLK        1
 203#define ISP_CLK_CSI2_FCK        2
 204#define ISP_CLK_L3_ICK          3
 205        struct clk *clock[4];
 206        struct isp_xclk xclks[2];
 207
 208        /* ISP modules */
 209        struct ispstat isp_af;
 210        struct ispstat isp_aewb;
 211        struct ispstat isp_hist;
 212        struct isp_res_device isp_res;
 213        struct isp_prev_device isp_prev;
 214        struct isp_ccdc_device isp_ccdc;
 215        struct isp_csi2_device isp_csi2a;
 216        struct isp_csi2_device isp_csi2c;
 217        struct isp_ccp2_device isp_ccp2;
 218        struct isp_csiphy isp_csiphy1;
 219        struct isp_csiphy isp_csiphy2;
 220
 221        unsigned int sbl_resources;
 222        unsigned int subclk_resources;
 223};
 224
 225struct isp_async_subdev {
 226        struct v4l2_async_subdev asd;
 227        struct isp_bus_cfg bus;
 228};
 229
 230#define v4l2_subdev_to_bus_cfg(sd) \
 231        (&container_of((sd)->asd, struct isp_async_subdev, asd)->bus)
 232
 233#define v4l2_dev_to_isp_device(dev) \
 234        container_of(dev, struct isp_device, v4l2_dev)
 235
 236void omap3isp_hist_dma_done(struct isp_device *isp);
 237
 238void omap3isp_flush(struct isp_device *isp);
 239
 240int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 241                              atomic_t *stopping);
 242
 243int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
 244                                     atomic_t *stopping);
 245
 246int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
 247                                 enum isp_pipeline_stream_state state);
 248void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
 249void omap3isp_configure_bridge(struct isp_device *isp,
 250                               enum ccdc_input_entity input,
 251                               const struct isp_parallel_cfg *buscfg,
 252                               unsigned int shift, unsigned int bridge);
 253
 254struct isp_device *omap3isp_get(struct isp_device *isp);
 255void omap3isp_put(struct isp_device *isp);
 256
 257void omap3isp_print_status(struct isp_device *isp);
 258
 259void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
 260void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
 261
 262void omap3isp_subclk_enable(struct isp_device *isp,
 263                            enum isp_subclk_resource res);
 264void omap3isp_subclk_disable(struct isp_device *isp,
 265                             enum isp_subclk_resource res);
 266
 267int omap3isp_register_entities(struct platform_device *pdev,
 268                               struct v4l2_device *v4l2_dev);
 269void omap3isp_unregister_entities(struct platform_device *pdev);
 270
 271/*
 272 * isp_reg_readl - Read value of an OMAP3 ISP register
 273 * @isp: Device pointer specific to the OMAP3 ISP.
 274 * @isp_mmio_range: Range to which the register offset refers to.
 275 * @reg_offset: Register offset to read from.
 276 *
 277 * Returns an unsigned 32 bit value with the required register contents.
 278 */
 279static inline
 280u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
 281                  u32 reg_offset)
 282{
 283        return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
 284}
 285
 286/*
 287 * isp_reg_writel - Write value to an OMAP3 ISP register
 288 * @isp: Device pointer specific to the OMAP3 ISP.
 289 * @reg_value: 32 bit value to write to the register.
 290 * @isp_mmio_range: Range to which the register offset refers to.
 291 * @reg_offset: Register offset to write into.
 292 */
 293static inline
 294void isp_reg_writel(struct isp_device *isp, u32 reg_value,
 295                    enum isp_mem_resources isp_mmio_range, u32 reg_offset)
 296{
 297        __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
 298}
 299
 300/*
 301 * isp_reg_clr - Clear individual bits in an OMAP3 ISP register
 302 * @isp: Device pointer specific to the OMAP3 ISP.
 303 * @mmio_range: Range to which the register offset refers to.
 304 * @reg: Register offset to work on.
 305 * @clr_bits: 32 bit value which would be cleared in the register.
 306 */
 307static inline
 308void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
 309                 u32 reg, u32 clr_bits)
 310{
 311        u32 v = isp_reg_readl(isp, mmio_range, reg);
 312
 313        isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
 314}
 315
 316/*
 317 * isp_reg_set - Set individual bits in an OMAP3 ISP register
 318 * @isp: Device pointer specific to the OMAP3 ISP.
 319 * @mmio_range: Range to which the register offset refers to.
 320 * @reg: Register offset to work on.
 321 * @set_bits: 32 bit value which would be set in the register.
 322 */
 323static inline
 324void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 325                 u32 reg, u32 set_bits)
 326{
 327        u32 v = isp_reg_readl(isp, mmio_range, reg);
 328
 329        isp_reg_writel(isp, v | set_bits, mmio_range, reg);
 330}
 331
 332/*
 333 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 334 * @isp: Device pointer specific to the OMAP3 ISP.
 335 * @mmio_range: Range to which the register offset refers to.
 336 * @reg: Register offset to work on.
 337 * @clr_bits: 32 bit value which would be cleared in the register.
 338 * @set_bits: 32 bit value which would be set in the register.
 339 *
 340 * The clear operation is done first, and then the set operation.
 341 */
 342static inline
 343void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 344                     u32 reg, u32 clr_bits, u32 set_bits)
 345{
 346        u32 v = isp_reg_readl(isp, mmio_range, reg);
 347
 348        isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
 349}
 350
 351static inline enum v4l2_buf_type
 352isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
 353{
 354        if (pad >= subdev->entity.num_pads)
 355                return 0;
 356
 357        if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
 358                return V4L2_BUF_TYPE_VIDEO_OUTPUT;
 359        else
 360                return V4L2_BUF_TYPE_VIDEO_CAPTURE;
 361}
 362
 363#endif  /* OMAP3_ISP_CORE_H */
 364