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16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/sys_soc.h>
23#include <linux/clk.h>
24#include <linux/ktime.h>
25#include <linux/dma-mapping.h>
26#include <linux/mmc/host.h>
27#include "sdhci-pltfm.h"
28#include "sdhci-esdhc.h"
29
30#define VENDOR_V_22 0x12
31#define VENDOR_V_23 0x13
32
33#define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
34
35struct esdhc_clk_fixup {
36 const unsigned int sd_dflt_max_clk;
37 const unsigned int max_clk[MMC_TIMING_NUM];
38};
39
40static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
41 .sd_dflt_max_clk = 25000000,
42 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
43 .max_clk[MMC_TIMING_SD_HS] = 46500000,
44};
45
46static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
47 .sd_dflt_max_clk = 25000000,
48 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
49 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
50};
51
52static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
53 .sd_dflt_max_clk = 25000000,
54 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
55 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
56};
57
58static const struct esdhc_clk_fixup p1010_esdhc_clk = {
59 .sd_dflt_max_clk = 20000000,
60 .max_clk[MMC_TIMING_LEGACY] = 20000000,
61 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
62 .max_clk[MMC_TIMING_SD_HS] = 40000000,
63};
64
65static const struct of_device_id sdhci_esdhc_of_match[] = {
66 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
67 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
68 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
69 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
70 { .compatible = "fsl,mpc8379-esdhc" },
71 { .compatible = "fsl,mpc8536-esdhc" },
72 { .compatible = "fsl,esdhc" },
73 { }
74};
75MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
76
77struct sdhci_esdhc {
78 u8 vendor_ver;
79 u8 spec_ver;
80 bool quirk_incorrect_hostver;
81 bool quirk_limited_clk_division;
82 bool quirk_unreliable_pulse_detection;
83 bool quirk_fixup_tuning;
84 unsigned int peripheral_clock;
85 const struct esdhc_clk_fixup *clk_fixup;
86 u32 div_ratio;
87};
88
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103
104static u32 esdhc_readl_fixup(struct sdhci_host *host,
105 int spec_reg, u32 value)
106{
107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
108 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
109 u32 ret;
110
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113
114
115
116
117
118
119 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
120 if (esdhc->vendor_ver > VENDOR_V_22) {
121 ret = value | SDHCI_CAN_DO_ADMA2;
122 return ret;
123 }
124 }
125
126
127
128
129
130
131
132 if (spec_reg == SDHCI_PRESENT_STATE) {
133 ret = value & 0x000fffff;
134 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
135 ret |= (value << 1) & SDHCI_CMD_LVL;
136 return ret;
137 }
138
139
140
141
142
143
144 if (spec_reg == SDHCI_CAPABILITIES_1) {
145 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
146 SDHCI_SUPPORT_DDR50);
147 return ret;
148 }
149
150 ret = value;
151 return ret;
152}
153
154static u16 esdhc_readw_fixup(struct sdhci_host *host,
155 int spec_reg, u32 value)
156{
157 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
158 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
159 u16 ret;
160 int shift = (spec_reg & 0x2) * 8;
161
162 if (spec_reg == SDHCI_HOST_VERSION)
163 ret = value & 0xffff;
164 else
165 ret = (value >> shift) & 0xffff;
166
167
168
169 if ((spec_reg == SDHCI_HOST_VERSION) &&
170 (esdhc->quirk_incorrect_hostver))
171 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
172 return ret;
173}
174
175static u8 esdhc_readb_fixup(struct sdhci_host *host,
176 int spec_reg, u32 value)
177{
178 u8 ret;
179 u8 dma_bits;
180 int shift = (spec_reg & 0x3) * 8;
181
182 ret = (value >> shift) & 0xff;
183
184
185
186
187
188 if (spec_reg == SDHCI_HOST_CONTROL) {
189
190 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
191
192 ret &= ~SDHCI_CTRL_DMA_MASK;
193 ret |= dma_bits;
194 }
195 return ret;
196}
197
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212
213
214static u32 esdhc_writel_fixup(struct sdhci_host *host,
215 int spec_reg, u32 value, u32 old_value)
216{
217 u32 ret;
218
219
220
221
222
223
224 if (spec_reg == SDHCI_INT_ENABLE)
225 ret = value | SDHCI_INT_BLK_GAP;
226 else
227 ret = value;
228
229 return ret;
230}
231
232static u32 esdhc_writew_fixup(struct sdhci_host *host,
233 int spec_reg, u16 value, u32 old_value)
234{
235 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
236 int shift = (spec_reg & 0x2) * 8;
237 u32 ret;
238
239 switch (spec_reg) {
240 case SDHCI_TRANSFER_MODE:
241
242
243
244
245 pltfm_host->xfer_mode_shadow = value;
246 return old_value;
247 case SDHCI_COMMAND:
248 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
249 return ret;
250 }
251
252 ret = old_value & (~(0xffff << shift));
253 ret |= (value << shift);
254
255 if (spec_reg == SDHCI_BLOCK_SIZE) {
256
257
258
259
260
261 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
262 }
263 return ret;
264}
265
266static u32 esdhc_writeb_fixup(struct sdhci_host *host,
267 int spec_reg, u8 value, u32 old_value)
268{
269 u32 ret;
270 u32 dma_bits;
271 u8 tmp;
272 int shift = (spec_reg & 0x3) * 8;
273
274
275
276
277
278 if (spec_reg == SDHCI_POWER_CONTROL)
279 return old_value;
280
281
282
283
284 if (spec_reg == SDHCI_HOST_CONTROL) {
285
286
287
288
289 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
290 return old_value;
291
292
293 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
294 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
295 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
296 (old_value & SDHCI_CTRL_DMA_MASK);
297 ret = (ret & (~0xff)) | tmp;
298
299
300 ret &= ~ESDHC_HOST_CONTROL_RES;
301 return ret;
302 }
303
304 ret = (old_value & (~(0xff << shift))) | (value << shift);
305 return ret;
306}
307
308static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
309{
310 u32 ret;
311 u32 value;
312
313 if (reg == SDHCI_CAPABILITIES_1)
314 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
315 else
316 value = ioread32be(host->ioaddr + reg);
317
318 ret = esdhc_readl_fixup(host, reg, value);
319
320 return ret;
321}
322
323static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
324{
325 u32 ret;
326 u32 value;
327
328 if (reg == SDHCI_CAPABILITIES_1)
329 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
330 else
331 value = ioread32(host->ioaddr + reg);
332
333 ret = esdhc_readl_fixup(host, reg, value);
334
335 return ret;
336}
337
338static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
339{
340 u16 ret;
341 u32 value;
342 int base = reg & ~0x3;
343
344 value = ioread32be(host->ioaddr + base);
345 ret = esdhc_readw_fixup(host, reg, value);
346 return ret;
347}
348
349static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
350{
351 u16 ret;
352 u32 value;
353 int base = reg & ~0x3;
354
355 value = ioread32(host->ioaddr + base);
356 ret = esdhc_readw_fixup(host, reg, value);
357 return ret;
358}
359
360static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
361{
362 u8 ret;
363 u32 value;
364 int base = reg & ~0x3;
365
366 value = ioread32be(host->ioaddr + base);
367 ret = esdhc_readb_fixup(host, reg, value);
368 return ret;
369}
370
371static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
372{
373 u8 ret;
374 u32 value;
375 int base = reg & ~0x3;
376
377 value = ioread32(host->ioaddr + base);
378 ret = esdhc_readb_fixup(host, reg, value);
379 return ret;
380}
381
382static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
383{
384 u32 value;
385
386 value = esdhc_writel_fixup(host, reg, val, 0);
387 iowrite32be(value, host->ioaddr + reg);
388}
389
390static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
391{
392 u32 value;
393
394 value = esdhc_writel_fixup(host, reg, val, 0);
395 iowrite32(value, host->ioaddr + reg);
396}
397
398static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
399{
400 int base = reg & ~0x3;
401 u32 value;
402 u32 ret;
403
404 value = ioread32be(host->ioaddr + base);
405 ret = esdhc_writew_fixup(host, reg, val, value);
406 if (reg != SDHCI_TRANSFER_MODE)
407 iowrite32be(ret, host->ioaddr + base);
408}
409
410static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
411{
412 int base = reg & ~0x3;
413 u32 value;
414 u32 ret;
415
416 value = ioread32(host->ioaddr + base);
417 ret = esdhc_writew_fixup(host, reg, val, value);
418 if (reg != SDHCI_TRANSFER_MODE)
419 iowrite32(ret, host->ioaddr + base);
420}
421
422static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
423{
424 int base = reg & ~0x3;
425 u32 value;
426 u32 ret;
427
428 value = ioread32be(host->ioaddr + base);
429 ret = esdhc_writeb_fixup(host, reg, val, value);
430 iowrite32be(ret, host->ioaddr + base);
431}
432
433static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
434{
435 int base = reg & ~0x3;
436 u32 value;
437 u32 ret;
438
439 value = ioread32(host->ioaddr + base);
440 ret = esdhc_writeb_fixup(host, reg, val, value);
441 iowrite32(ret, host->ioaddr + base);
442}
443
444
445
446
447
448
449
450
451static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
452{
453 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
454 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
455 bool applicable;
456 dma_addr_t dmastart;
457 dma_addr_t dmanow;
458
459 applicable = (intmask & SDHCI_INT_DATA_END) &&
460 (intmask & SDHCI_INT_BLK_GAP) &&
461 (esdhc->vendor_ver == VENDOR_V_23);
462 if (!applicable)
463 return;
464
465 host->data->error = 0;
466 dmastart = sg_dma_address(host->data->sg);
467 dmanow = dmastart + host->data->bytes_xfered;
468
469
470
471 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
472 SDHCI_DEFAULT_BOUNDARY_SIZE;
473 host->data->bytes_xfered = dmanow - dmastart;
474 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
475}
476
477static int esdhc_of_enable_dma(struct sdhci_host *host)
478{
479 u32 value;
480 struct device *dev = mmc_dev(host->mmc);
481
482 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
483 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))
484 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
485
486 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
487 value |= ESDHC_DMA_SNOOP;
488 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
489 return 0;
490}
491
492static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
493{
494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
495 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
496
497 if (esdhc->peripheral_clock)
498 return esdhc->peripheral_clock;
499 else
500 return pltfm_host->clock;
501}
502
503static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
504{
505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
506 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
507 unsigned int clock;
508
509 if (esdhc->peripheral_clock)
510 clock = esdhc->peripheral_clock;
511 else
512 clock = pltfm_host->clock;
513 return clock / 256 / 16;
514}
515
516static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
517{
518 u32 val;
519 ktime_t timeout;
520
521 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
522
523 if (enable)
524 val |= ESDHC_CLOCK_SDCLKEN;
525 else
526 val &= ~ESDHC_CLOCK_SDCLKEN;
527
528 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
529
530
531 timeout = ktime_add_ms(ktime_get(), 20);
532 val = ESDHC_CLOCK_STABLE;
533 while (1) {
534 bool timedout = ktime_after(ktime_get(), timeout);
535
536 if (sdhci_readl(host, ESDHC_PRSSTAT) & val)
537 break;
538 if (timedout) {
539 pr_err("%s: Internal clock never stabilised.\n",
540 mmc_hostname(host->mmc));
541 break;
542 }
543 udelay(10);
544 }
545}
546
547static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
548{
549 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
550 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
551 int pre_div = 1;
552 int div = 1;
553 int division;
554 ktime_t timeout;
555 long fixup = 0;
556 u32 temp;
557
558 host->mmc->actual_clock = 0;
559
560 if (clock == 0) {
561 esdhc_clock_enable(host, false);
562 return;
563 }
564
565
566 if (esdhc->vendor_ver < VENDOR_V_23)
567 pre_div = 2;
568
569 if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
570 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
571 fixup = esdhc->clk_fixup->sd_dflt_max_clk;
572 else if (esdhc->clk_fixup)
573 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
574
575 if (fixup && clock > fixup)
576 clock = fixup;
577
578 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
579 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
580 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
581 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
582
583 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
584 pre_div *= 2;
585
586 while (host->max_clk / pre_div / div > clock && div < 16)
587 div++;
588
589 if (esdhc->quirk_limited_clk_division &&
590 clock == MMC_HS200_MAX_DTR &&
591 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
592 host->flags & SDHCI_HS400_TUNING)) {
593 division = pre_div * div;
594 if (division <= 4) {
595 pre_div = 4;
596 div = 1;
597 } else if (division <= 8) {
598 pre_div = 4;
599 div = 2;
600 } else if (division <= 12) {
601 pre_div = 4;
602 div = 3;
603 } else {
604 pr_warn("%s: using unsupported clock division.\n",
605 mmc_hostname(host->mmc));
606 }
607 }
608
609 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
610 clock, host->max_clk / pre_div / div);
611 host->mmc->actual_clock = host->max_clk / pre_div / div;
612 esdhc->div_ratio = pre_div * div;
613 pre_div >>= 1;
614 div--;
615
616 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
617 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
618 | (div << ESDHC_DIVIDER_SHIFT)
619 | (pre_div << ESDHC_PREDIV_SHIFT));
620 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
621
622 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
623 clock == MMC_HS200_MAX_DTR) {
624 temp = sdhci_readl(host, ESDHC_TBCTL);
625 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
626 temp = sdhci_readl(host, ESDHC_SDCLKCTL);
627 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
628 esdhc_clock_enable(host, true);
629
630 temp = sdhci_readl(host, ESDHC_DLLCFG0);
631 temp |= ESDHC_DLL_ENABLE;
632 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
633 temp |= ESDHC_DLL_FREQ_SEL;
634 sdhci_writel(host, temp, ESDHC_DLLCFG0);
635 temp = sdhci_readl(host, ESDHC_TBCTL);
636 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
637
638 esdhc_clock_enable(host, false);
639 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);
640 temp |= ESDHC_FLUSH_ASYNC_FIFO;
641 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
642 }
643
644
645 timeout = ktime_add_ms(ktime_get(), 20);
646 while (1) {
647 bool timedout = ktime_after(ktime_get(), timeout);
648
649 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
650 break;
651 if (timedout) {
652 pr_err("%s: Internal clock never stabilised.\n",
653 mmc_hostname(host->mmc));
654 return;
655 }
656 udelay(10);
657 }
658
659 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
660 temp |= ESDHC_CLOCK_SDCLKEN;
661 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
662}
663
664static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
665{
666 u32 ctrl;
667
668 ctrl = sdhci_readl(host, ESDHC_PROCTL);
669 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
670 switch (width) {
671 case MMC_BUS_WIDTH_8:
672 ctrl |= ESDHC_CTRL_8BITBUS;
673 break;
674
675 case MMC_BUS_WIDTH_4:
676 ctrl |= ESDHC_CTRL_4BITBUS;
677 break;
678
679 default:
680 break;
681 }
682
683 sdhci_writel(host, ctrl, ESDHC_PROCTL);
684}
685
686static void esdhc_reset(struct sdhci_host *host, u8 mask)
687{
688 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
689 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
690 u32 val;
691
692 sdhci_reset(host, mask);
693
694 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
695 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
696
697 if (mask & SDHCI_RESET_ALL) {
698 val = sdhci_readl(host, ESDHC_TBCTL);
699 val &= ~ESDHC_TB_EN;
700 sdhci_writel(host, val, ESDHC_TBCTL);
701
702 if (esdhc->quirk_unreliable_pulse_detection) {
703 val = sdhci_readl(host, ESDHC_DLLCFG1);
704 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
705 sdhci_writel(host, val, ESDHC_DLLCFG1);
706 }
707 }
708}
709
710
711
712
713
714
715static const struct of_device_id scfg_device_ids[] = {
716 { .compatible = "fsl,t1040-scfg", },
717 { .compatible = "fsl,ls1012a-scfg", },
718 { .compatible = "fsl,ls1046a-scfg", },
719 {}
720};
721
722
723#define SCFG_SDHCIOVSELCR 0x408
724#define SDHCIOVSELCR_TGLEN 0x80000000
725#define SDHCIOVSELCR_VSELVAL 0x60000000
726#define SDHCIOVSELCR_SDHC_VS 0x00000001
727
728static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
729 struct mmc_ios *ios)
730{
731 struct sdhci_host *host = mmc_priv(mmc);
732 struct device_node *scfg_node;
733 void __iomem *scfg_base = NULL;
734 u32 sdhciovselcr;
735 u32 val;
736
737
738
739
740
741 if (host->version < SDHCI_SPEC_300)
742 return 0;
743
744 val = sdhci_readl(host, ESDHC_PROCTL);
745
746 switch (ios->signal_voltage) {
747 case MMC_SIGNAL_VOLTAGE_330:
748 val &= ~ESDHC_VOLT_SEL;
749 sdhci_writel(host, val, ESDHC_PROCTL);
750 return 0;
751 case MMC_SIGNAL_VOLTAGE_180:
752 scfg_node = of_find_matching_node(NULL, scfg_device_ids);
753 if (scfg_node)
754 scfg_base = of_iomap(scfg_node, 0);
755 if (scfg_base) {
756 sdhciovselcr = SDHCIOVSELCR_TGLEN |
757 SDHCIOVSELCR_VSELVAL;
758 iowrite32be(sdhciovselcr,
759 scfg_base + SCFG_SDHCIOVSELCR);
760
761 val |= ESDHC_VOLT_SEL;
762 sdhci_writel(host, val, ESDHC_PROCTL);
763 mdelay(5);
764
765 sdhciovselcr = SDHCIOVSELCR_TGLEN |
766 SDHCIOVSELCR_SDHC_VS;
767 iowrite32be(sdhciovselcr,
768 scfg_base + SCFG_SDHCIOVSELCR);
769 iounmap(scfg_base);
770 } else {
771 val |= ESDHC_VOLT_SEL;
772 sdhci_writel(host, val, ESDHC_PROCTL);
773 }
774 return 0;
775 default:
776 return 0;
777 }
778}
779
780static struct soc_device_attribute soc_fixup_tuning[] = {
781 { .family = "QorIQ T1040", .revision = "1.0", },
782 { .family = "QorIQ T2080", .revision = "1.0", },
783 { .family = "QorIQ T1023", .revision = "1.0", },
784 { .family = "QorIQ LS1021A", .revision = "1.0", },
785 { .family = "QorIQ LS1080A", .revision = "1.0", },
786 { .family = "QorIQ LS2080A", .revision = "1.0", },
787 { .family = "QorIQ LS1012A", .revision = "1.0", },
788 { .family = "QorIQ LS1043A", .revision = "1.*", },
789 { .family = "QorIQ LS1046A", .revision = "1.0", },
790 { },
791};
792
793static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
794{
795 u32 val;
796
797 esdhc_clock_enable(host, false);
798
799 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
800 val |= ESDHC_FLUSH_ASYNC_FIFO;
801 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
802
803 val = sdhci_readl(host, ESDHC_TBCTL);
804 if (enable)
805 val |= ESDHC_TB_EN;
806 else
807 val &= ~ESDHC_TB_EN;
808 sdhci_writel(host, val, ESDHC_TBCTL);
809
810 esdhc_clock_enable(host, true);
811}
812
813static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
814{
815 struct sdhci_host *host = mmc_priv(mmc);
816 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
818 bool hs400_tuning;
819 u32 val;
820 int ret;
821
822 if (esdhc->quirk_limited_clk_division &&
823 host->flags & SDHCI_HS400_TUNING)
824 esdhc_of_set_clock(host, host->clock);
825
826 esdhc_tuning_block_enable(host, true);
827
828 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
829 ret = sdhci_execute_tuning(mmc, opcode);
830
831 if (hs400_tuning) {
832 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
833 val |= ESDHC_FLW_CTL_BG;
834 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
835 }
836
837 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) {
838
839
840
841
842 val = sdhci_readl(host, ESDHC_TBPTR);
843 val = (val & ~((0x7f << 8) | 0x7f)) |
844 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8);
845 sdhci_writel(host, val, ESDHC_TBPTR);
846
847
848
849
850 val = sdhci_readl(host, ESDHC_TBCTL);
851 val |= 0x3;
852 sdhci_writel(host, val, ESDHC_TBCTL);
853 sdhci_execute_tuning(mmc, opcode);
854 }
855 return ret;
856}
857
858static void esdhc_set_uhs_signaling(struct sdhci_host *host,
859 unsigned int timing)
860{
861 if (timing == MMC_TIMING_MMC_HS400)
862 esdhc_tuning_block_enable(host, true);
863 else
864 sdhci_set_uhs_signaling(host, timing);
865}
866
867#ifdef CONFIG_PM_SLEEP
868static u32 esdhc_proctl;
869static int esdhc_of_suspend(struct device *dev)
870{
871 struct sdhci_host *host = dev_get_drvdata(dev);
872
873 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
874
875 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
876 mmc_retune_needed(host->mmc);
877
878 return sdhci_suspend_host(host);
879}
880
881static int esdhc_of_resume(struct device *dev)
882{
883 struct sdhci_host *host = dev_get_drvdata(dev);
884 int ret = sdhci_resume_host(host);
885
886 if (ret == 0) {
887
888 esdhc_of_enable_dma(host);
889 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
890 }
891 return ret;
892}
893#endif
894
895static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
896 esdhc_of_suspend,
897 esdhc_of_resume);
898
899static const struct sdhci_ops sdhci_esdhc_be_ops = {
900 .read_l = esdhc_be_readl,
901 .read_w = esdhc_be_readw,
902 .read_b = esdhc_be_readb,
903 .write_l = esdhc_be_writel,
904 .write_w = esdhc_be_writew,
905 .write_b = esdhc_be_writeb,
906 .set_clock = esdhc_of_set_clock,
907 .enable_dma = esdhc_of_enable_dma,
908 .get_max_clock = esdhc_of_get_max_clock,
909 .get_min_clock = esdhc_of_get_min_clock,
910 .adma_workaround = esdhc_of_adma_workaround,
911 .set_bus_width = esdhc_pltfm_set_bus_width,
912 .reset = esdhc_reset,
913 .set_uhs_signaling = esdhc_set_uhs_signaling,
914};
915
916static const struct sdhci_ops sdhci_esdhc_le_ops = {
917 .read_l = esdhc_le_readl,
918 .read_w = esdhc_le_readw,
919 .read_b = esdhc_le_readb,
920 .write_l = esdhc_le_writel,
921 .write_w = esdhc_le_writew,
922 .write_b = esdhc_le_writeb,
923 .set_clock = esdhc_of_set_clock,
924 .enable_dma = esdhc_of_enable_dma,
925 .get_max_clock = esdhc_of_get_max_clock,
926 .get_min_clock = esdhc_of_get_min_clock,
927 .adma_workaround = esdhc_of_adma_workaround,
928 .set_bus_width = esdhc_pltfm_set_bus_width,
929 .reset = esdhc_reset,
930 .set_uhs_signaling = esdhc_set_uhs_signaling,
931};
932
933static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
934 .quirks = ESDHC_DEFAULT_QUIRKS |
935#ifdef CONFIG_PPC
936 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
937#endif
938 SDHCI_QUIRK_NO_CARD_NO_RESET |
939 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
940 .ops = &sdhci_esdhc_be_ops,
941};
942
943static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
944 .quirks = ESDHC_DEFAULT_QUIRKS |
945 SDHCI_QUIRK_NO_CARD_NO_RESET |
946 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
947 .ops = &sdhci_esdhc_le_ops,
948};
949
950static struct soc_device_attribute soc_incorrect_hostver[] = {
951 { .family = "QorIQ T4240", .revision = "1.0", },
952 { .family = "QorIQ T4240", .revision = "2.0", },
953 { },
954};
955
956static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
957 { .family = "QorIQ LX2160A", .revision = "1.0", },
958 { },
959};
960
961static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
962 { .family = "QorIQ LX2160A", .revision = "1.0", },
963 { },
964};
965
966static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
967{
968 const struct of_device_id *match;
969 struct sdhci_pltfm_host *pltfm_host;
970 struct sdhci_esdhc *esdhc;
971 struct device_node *np;
972 struct clk *clk;
973 u32 val;
974 u16 host_ver;
975
976 pltfm_host = sdhci_priv(host);
977 esdhc = sdhci_pltfm_priv(pltfm_host);
978
979 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
980 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
981 SDHCI_VENDOR_VER_SHIFT;
982 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
983 if (soc_device_match(soc_incorrect_hostver))
984 esdhc->quirk_incorrect_hostver = true;
985 else
986 esdhc->quirk_incorrect_hostver = false;
987
988 if (soc_device_match(soc_fixup_sdhc_clkdivs))
989 esdhc->quirk_limited_clk_division = true;
990 else
991 esdhc->quirk_limited_clk_division = false;
992
993 if (soc_device_match(soc_unreliable_pulse_detection))
994 esdhc->quirk_unreliable_pulse_detection = true;
995 else
996 esdhc->quirk_unreliable_pulse_detection = false;
997
998 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
999 if (match)
1000 esdhc->clk_fixup = match->data;
1001 np = pdev->dev.of_node;
1002 clk = of_clk_get(np, 0);
1003 if (!IS_ERR(clk)) {
1004
1005
1006
1007
1008
1009
1010
1011 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
1012 esdhc->peripheral_clock = clk_get_rate(clk) / 2;
1013 else
1014 esdhc->peripheral_clock = clk_get_rate(clk);
1015
1016 clk_put(clk);
1017 }
1018
1019 if (esdhc->peripheral_clock) {
1020 esdhc_clock_enable(host, false);
1021 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1022 val |= ESDHC_PERIPHERAL_CLK_SEL;
1023 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
1024 esdhc_clock_enable(host, true);
1025 }
1026}
1027
1028static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
1029{
1030 esdhc_tuning_block_enable(mmc_priv(mmc), false);
1031 return 0;
1032}
1033
1034static int sdhci_esdhc_probe(struct platform_device *pdev)
1035{
1036 struct sdhci_host *host;
1037 struct device_node *np;
1038 struct sdhci_pltfm_host *pltfm_host;
1039 struct sdhci_esdhc *esdhc;
1040 int ret;
1041
1042 np = pdev->dev.of_node;
1043
1044 if (of_property_read_bool(np, "little-endian"))
1045 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
1046 sizeof(struct sdhci_esdhc));
1047 else
1048 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
1049 sizeof(struct sdhci_esdhc));
1050
1051 if (IS_ERR(host))
1052 return PTR_ERR(host);
1053
1054 host->mmc_host_ops.start_signal_voltage_switch =
1055 esdhc_signal_voltage_switch;
1056 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
1057 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
1058 host->tuning_delay = 1;
1059
1060 esdhc_init(pdev, host);
1061
1062 sdhci_get_of_property(pdev);
1063
1064 pltfm_host = sdhci_priv(host);
1065 esdhc = sdhci_pltfm_priv(pltfm_host);
1066 if (soc_device_match(soc_fixup_tuning))
1067 esdhc->quirk_fixup_tuning = true;
1068 else
1069 esdhc->quirk_fixup_tuning = false;
1070
1071 if (esdhc->vendor_ver == VENDOR_V_22)
1072 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
1073
1074 if (esdhc->vendor_ver > VENDOR_V_22)
1075 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1076
1077 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
1078 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
1079 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
1080 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
1081 of_device_is_compatible(np, "fsl,t1040-esdhc"))
1082 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1083
1084 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
1085 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1086
1087 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
1088
1089
1090
1091
1092 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
1093 }
1094
1095
1096 ret = mmc_of_parse(host->mmc);
1097 if (ret)
1098 goto err;
1099
1100 mmc_of_parse_voltage(np, &host->ocr_mask);
1101
1102 ret = sdhci_add_host(host);
1103 if (ret)
1104 goto err;
1105
1106 return 0;
1107 err:
1108 sdhci_pltfm_free(pdev);
1109 return ret;
1110}
1111
1112static struct platform_driver sdhci_esdhc_driver = {
1113 .driver = {
1114 .name = "sdhci-esdhc",
1115 .of_match_table = sdhci_esdhc_of_match,
1116 .pm = &esdhc_of_dev_pm_ops,
1117 },
1118 .probe = sdhci_esdhc_probe,
1119 .remove = sdhci_pltfm_unregister,
1120};
1121
1122module_platform_driver(sdhci_esdhc_driver);
1123
1124MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
1125MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
1126 "Anton Vorontsov <avorontsov@ru.mvista.com>");
1127MODULE_LICENSE("GPL v2");
1128