LXR linux/drivers/mtd/nand/raw/cs553x

   1/*
   2 * (C) 2005, 2006 Red Hat Inc.
   3 *
   4 * Author: David Woodhouse <dwmw2@infradead.org>
   5 *         Tom Sylla <tom.sylla@amd.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 *  Overview:
  12 *   This is a device driver for the NAND flash controller found on
  13 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
  14 *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
  15 *   where 0-3 reflects the chip select for NAND.
  16 *
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/slab.h>
  21#include <linux/init.h>
  22#include <linux/module.h>
  23#include <linux/delay.h>
  24#include <linux/mtd/mtd.h>
  25#include <linux/mtd/rawnand.h>
  26#include <linux/mtd/nand_ecc.h>
  27#include <linux/mtd/partitions.h>
  28
  29#include <asm/msr.h>
  30#include <asm/io.h>
  31
  32#define NR_CS553X_CONTROLLERS   4
  33
  34#define MSR_DIVIL_GLD_CAP       0x51400000      /* DIVIL capabilitiies */
  35#define CAP_CS5535              0x2df000ULL
  36#define CAP_CS5536              0x5df500ULL
  37
  38/* NAND Timing MSRs */
  39#define MSR_NANDF_DATA          0x5140001b      /* NAND Flash Data Timing MSR */
  40#define MSR_NANDF_CTL           0x5140001c      /* NAND Flash Control Timing */
  41#define MSR_NANDF_RSVD          0x5140001d      /* Reserved */
  42
  43/* NAND BAR MSRs */
  44#define MSR_DIVIL_LBAR_FLSH0    0x51400010      /* Flash Chip Select 0 */
  45#define MSR_DIVIL_LBAR_FLSH1    0x51400011      /* Flash Chip Select 1 */
  46#define MSR_DIVIL_LBAR_FLSH2    0x51400012      /* Flash Chip Select 2 */
  47#define MSR_DIVIL_LBAR_FLSH3    0x51400013      /* Flash Chip Select 3 */
  48        /* Each made up of... */
  49#define FLSH_LBAR_EN            (1ULL<<32)
  50#define FLSH_NOR_NAND           (1ULL<<33)      /* 1 for NAND */
  51#define FLSH_MEM_IO             (1ULL<<34)      /* 1 for MMIO */
  52        /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
  53        /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
  54
  55/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
  56#define MSR_DIVIL_BALL_OPTS     0x51400015
  57#define PIN_OPT_IDE             (1<<0)  /* 0 for flash, 1 for IDE */
  58
  59/* Registers within the NAND flash controller BAR -- memory mapped */
  60#define MM_NAND_DATA            0x00    /* 0 to 0x7ff, in fact */
  61#define MM_NAND_CTL             0x800   /* Any even address 0x800-0x80e */
  62#define MM_NAND_IO              0x801   /* Any odd address 0x801-0x80f */
  63#define MM_NAND_STS             0x810
  64#define MM_NAND_ECC_LSB         0x811
  65#define MM_NAND_ECC_MSB         0x812
  66#define MM_NAND_ECC_COL         0x813
  67#define MM_NAND_LAC             0x814
  68#define MM_NAND_ECC_CTL         0x815
  69
  70/* Registers within the NAND flash controller BAR -- I/O mapped */
  71#define IO_NAND_DATA            0x00    /* 0 to 3, in fact */
  72#define IO_NAND_CTL             0x04
  73#define IO_NAND_IO              0x05
  74#define IO_NAND_STS             0x06
  75#define IO_NAND_ECC_CTL         0x08
  76#define IO_NAND_ECC_LSB         0x09
  77#define IO_NAND_ECC_MSB         0x0a
  78#define IO_NAND_ECC_COL         0x0b
  79#define IO_NAND_LAC             0x0c
  80
  81#define CS_NAND_CTL_DIST_EN     (1<<4)  /* Enable NAND Distract interrupt */
  82#define CS_NAND_CTL_RDY_INT_MASK        (1<<3)  /* Enable RDY/BUSY# interrupt */
  83#define CS_NAND_CTL_ALE         (1<<2)
  84#define CS_NAND_CTL_CLE         (1<<1)
  85#define CS_NAND_CTL_CE          (1<<0)  /* Keep low; 1 to reset */
  86
  87#define CS_NAND_STS_FLASH_RDY   (1<<3)
  88#define CS_NAND_CTLR_BUSY       (1<<2)
  89#define CS_NAND_CMD_COMP        (1<<1)
  90#define CS_NAND_DIST_ST         (1<<0)
  91
  92#define CS_NAND_ECC_PARITY      (1<<2)
  93#define CS_NAND_ECC_CLRECC      (1<<1)
  94#define CS_NAND_ECC_ENECC       (1<<0)
  95
  96static void cs553x_read_buf(struct nand_chip *this, u_char *buf, int len)
  97{
  98        while (unlikely(len > 0x800)) {
  99                memcpy_fromio(buf, this->legacy.IO_ADDR_R, 0x800);
 100                buf += 0x800;
 101                len -= 0x800;
 102        }
 103        memcpy_fromio(buf, this->legacy.IO_ADDR_R, len);
 104}
 105
 106static void cs553x_write_buf(struct nand_chip *this, const u_char *buf, int len)
 107{
 108        while (unlikely(len > 0x800)) {
 109                memcpy_toio(this->legacy.IO_ADDR_R, buf, 0x800);
 110                buf += 0x800;
 111                len -= 0x800;
 112        }
 113        memcpy_toio(this->legacy.IO_ADDR_R, buf, len);
 114}
 115
 116static unsigned char cs553x_read_byte(struct nand_chip *this)
 117{
 118        return readb(this->legacy.IO_ADDR_R);
 119}
 120
 121static void cs553x_write_byte(struct nand_chip *this, u_char byte)
 122{
 123        int i = 100000;
 124
 125        while (i && readb(this->legacy.IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
 126                udelay(1);
 127                i--;
 128        }
 129        writeb(byte, this->legacy.IO_ADDR_W + 0x801);
 130}
 131
 132static void cs553x_hwcontrol(struct nand_chip *this, int cmd,
 133                             unsigned int ctrl)
 134{
 135        void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 136        if (ctrl & NAND_CTRL_CHANGE) {
 137                unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
 138                writeb(ctl, mmio_base + MM_NAND_CTL);
 139        }
 140        if (cmd != NAND_CMD_NONE)
 141                cs553x_write_byte(this, cmd);
 142}
 143
 144static int cs553x_device_ready(struct nand_chip *this)
 145{
 146        void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 147        unsigned char foo = readb(mmio_base + MM_NAND_STS);
 148
 149        return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
 150}
 151
 152static void cs_enable_hwecc(struct nand_chip *this, int mode)
 153{
 154        void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 155
 156        writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
 157}
 158
 159static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
 160                            u_char *ecc_code)
 161{
 162        uint32_t ecc;
 163        void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 164
 165        ecc = readl(mmio_base + MM_NAND_STS);
 166
 167        ecc_code[1] = ecc >> 8;
 168        ecc_code[0] = ecc >> 16;
 169        ecc_code[2] = ecc >> 24;
 170        return 0;
 171}
 172
 173static struct mtd_info *cs553x_mtd[4];
 174
 175static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 176{
 177        int err = 0;
 178        struct nand_chip *this;
 179        struct mtd_info *new_mtd;
 180
 181        pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",
 182                  cs, mmio ? "MM" : "P", adr);
 183
 184        if (!mmio) {
 185                pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
 186                return -ENXIO;
 187        }
 188
 189        /* Allocate memory for MTD device structure and private data */
 190        this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
 191        if (!this) {
 192                err = -ENOMEM;
 193                goto out;
 194        }
 195
 196        new_mtd = nand_to_mtd(this);
 197
 198        /* Link the private data with the MTD structure */
 199        new_mtd->owner = THIS_MODULE;
 200
 201        /* map physical address */
 202        this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = ioremap(adr, 4096);
 203        if (!this->legacy.IO_ADDR_R) {
 204                pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
 205                err = -EIO;
 206                goto out_mtd;
 207        }
 208
 209        this->legacy.cmd_ctrl = cs553x_hwcontrol;
 210        this->legacy.dev_ready = cs553x_device_ready;
 211        this->legacy.read_byte = cs553x_read_byte;
 212        this->legacy.read_buf = cs553x_read_buf;
 213        this->legacy.write_buf = cs553x_write_buf;
 214
 215        this->legacy.chip_delay = 0;
 216
 217        this->ecc.mode = NAND_ECC_HW;
 218        this->ecc.size = 256;
 219        this->ecc.bytes = 3;
 220        this->ecc.hwctl  = cs_enable_hwecc;
 221        this->ecc.calculate = cs_calculate_ecc;
 222        this->ecc.correct  = nand_correct_data;
 223        this->ecc.strength = 1;
 224
 225        /* Enable the following for a flash based bad block table */
 226        this->bbt_options = NAND_BBT_USE_FLASH;
 227
 228        new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
 229        if (!new_mtd->name) {
 230                err = -ENOMEM;
 231                goto out_ior;
 232        }
 233
 234        /* Scan to find existence of the device */
 235        err = nand_scan(this, 1);
 236        if (err)
 237                goto out_free;
 238
 239        cs553x_mtd[cs] = new_mtd;
 240        goto out;
 241
 242out_free:
 243        kfree(new_mtd->name);
 244out_ior:
 245        iounmap(this->legacy.IO_ADDR_R);
 246out_mtd:
 247        kfree(this);
 248out:
 249        return err;
 250}
 251
 252static int is_geode(void)
 253{
 254        /* These are the CPUs which will have a CS553[56] companion chip */
 255        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 256            boot_cpu_data.x86 == 5 &&
 257            boot_cpu_data.x86_model == 10)
 258                return 1; /* Geode LX */
 259
 260        if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
 261             boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
 262            boot_cpu_data.x86 == 5 &&
 263            boot_cpu_data.x86_model == 5)
 264                return 1; /* Geode GX (née GX2) */
 265
 266        return 0;
 267}
 268
 269static int __init cs553x_init(void)
 270{
 271        int err = -ENXIO;
 272        int i;
 273        uint64_t val;
 274
 275        /* If the CPU isn't a Geode GX or LX, abort */
 276        if (!is_geode())
 277                return -ENXIO;
 278
 279        /* If it doesn't have the CS553[56], abort */
 280        rdmsrl(MSR_DIVIL_GLD_CAP, val);
 281        val &= ~0xFFULL;
 282        if (val != CAP_CS5535 && val != CAP_CS5536)
 283                return -ENXIO;
 284
 285        /* If it doesn't have the NAND controller enabled, abort */
 286        rdmsrl(MSR_DIVIL_BALL_OPTS, val);
 287        if (val & PIN_OPT_IDE) {
 288                pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
 289                return -ENXIO;
 290        }
 291
 292        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 293                rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
 294
 295                if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
 296                        err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
 297        }
 298
 299        /* Register all devices together here. This means we can easily hack it to
 300           do mtdconcat etc. if we want to. */
 301        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 302                if (cs553x_mtd[i]) {
 303                        /* If any devices registered, return success. Else the last error. */
 304                        mtd_device_register(cs553x_mtd[i], NULL, 0);
 305                        err = 0;
 306                }
 307        }
 308
 309        return err;
 310}
 311
 312module_init(cs553x_init);
 313
 314static void __exit cs553x_cleanup(void)
 315{
 316        int i;
 317
 318        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 319                struct mtd_info *mtd = cs553x_mtd[i];
 320                struct nand_chip *this;
 321                void __iomem *mmio_base;
 322
 323                if (!mtd)
 324                        continue;
 325
 326                this = mtd_to_nand(mtd);
 327                mmio_base = this->legacy.IO_ADDR_R;
 328
 329                /* Release resources, unregister device */
 330                nand_release(this);
 331                kfree(mtd->name);
 332                cs553x_mtd[i] = NULL;
 333
 334                /* unmap physical address */
 335                iounmap(mmio_base);
 336
 337                /* Free the MTD device structure */
 338                kfree(this);
 339        }
 340}
 341
 342module_exit(cs553x_cleanup);
 343
 344MODULE_LICENSE("GPL");
 345MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 346MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
 347