LXR linux/drivers/mtd/nand/raw/nand

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   4 *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
   5 *
   6 *  Credits:
   7 *      David Woodhouse for adding multichip support
   8 *
   9 *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  10 *      rework for 2K page size chips
  11 *
  12 * This file contains all legacy helpers/code that should be removed
  13 * at some point.
  14 */
  15
  16#include <linux/delay.h>
  17#include <linux/io.h>
  18#include <linux/nmi.h>
  19
  20#include "internals.h"
  21
  22/**
  23 * nand_read_byte - [DEFAULT] read one byte from the chip
  24 * @chip: NAND chip object
  25 *
  26 * Default read function for 8bit buswidth
  27 */
  28static uint8_t nand_read_byte(struct nand_chip *chip)
  29{
  30        return readb(chip->legacy.IO_ADDR_R);
  31}
  32
  33/**
  34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  35 * @chip: NAND chip object
  36 *
  37 * Default read function for 16bit buswidth with endianness conversion.
  38 *
  39 */
  40static uint8_t nand_read_byte16(struct nand_chip *chip)
  41{
  42        return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
  43}
  44
  45/**
  46 * nand_select_chip - [DEFAULT] control CE line
  47 * @chip: NAND chip object
  48 * @chipnr: chipnumber to select, -1 for deselect
  49 *
  50 * Default select function for 1 chip devices.
  51 */
  52static void nand_select_chip(struct nand_chip *chip, int chipnr)
  53{
  54        switch (chipnr) {
  55        case -1:
  56                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
  57                                      0 | NAND_CTRL_CHANGE);
  58                break;
  59        case 0:
  60                break;
  61
  62        default:
  63                BUG();
  64        }
  65}
  66
  67/**
  68 * nand_write_byte - [DEFAULT] write single byte to chip
  69 * @chip: NAND chip object
  70 * @byte: value to write
  71 *
  72 * Default function to write a byte to I/O[7:0]
  73 */
  74static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
  75{
  76        chip->legacy.write_buf(chip, &byte, 1);
  77}
  78
  79/**
  80 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  81 * @chip: NAND chip object
  82 * @byte: value to write
  83 *
  84 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  85 */
  86static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
  87{
  88        uint16_t word = byte;
  89
  90        /*
  91         * It's not entirely clear what should happen to I/O[15:8] when writing
  92         * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  93         *
  94         *    When the host supports a 16-bit bus width, only data is
  95         *    transferred at the 16-bit width. All address and command line
  96         *    transfers shall use only the lower 8-bits of the data bus. During
  97         *    command transfers, the host may place any value on the upper
  98         *    8-bits of the data bus. During address transfers, the host shall
  99         *    set the upper 8-bits of the data bus to 00h.
 100         *
 101         * One user of the write_byte callback is nand_set_features. The
 102         * four parameters are specified to be written to I/O[7:0], but this is
 103         * neither an address nor a command transfer. Let's assume a 0 on the
 104         * upper I/O lines is OK.
 105         */
 106        chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
 107}
 108
 109/**
 110 * nand_write_buf - [DEFAULT] write buffer to chip
 111 * @chip: NAND chip object
 112 * @buf: data buffer
 113 * @len: number of bytes to write
 114 *
 115 * Default write function for 8bit buswidth.
 116 */
 117static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
 118{
 119        iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
 120}
 121
 122/**
 123 * nand_read_buf - [DEFAULT] read chip data into buffer
 124 * @chip: NAND chip object
 125 * @buf: buffer to store date
 126 * @len: number of bytes to read
 127 *
 128 * Default read function for 8bit buswidth.
 129 */
 130static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 131{
 132        ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
 133}
 134
 135/**
 136 * nand_write_buf16 - [DEFAULT] write buffer to chip
 137 * @chip: NAND chip object
 138 * @buf: data buffer
 139 * @len: number of bytes to write
 140 *
 141 * Default write function for 16bit buswidth.
 142 */
 143static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
 144                             int len)
 145{
 146        u16 *p = (u16 *) buf;
 147
 148        iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
 149}
 150
 151/**
 152 * nand_read_buf16 - [DEFAULT] read chip data into buffer
 153 * @chip: NAND chip object
 154 * @buf: buffer to store date
 155 * @len: number of bytes to read
 156 *
 157 * Default read function for 16bit buswidth.
 158 */
 159static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
 160{
 161        u16 *p = (u16 *) buf;
 162
 163        ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
 164}
 165
 166/**
 167 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 168 * @chip: NAND chip object
 169 * @timeo: Timeout
 170 *
 171 * Helper function for nand_wait_ready used when needing to wait in interrupt
 172 * context.
 173 */
 174static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
 175{
 176        int i;
 177
 178        /* Wait for the device to get ready */
 179        for (i = 0; i < timeo; i++) {
 180                if (chip->legacy.dev_ready(chip))
 181                        break;
 182                touch_softlockup_watchdog();
 183                mdelay(1);
 184        }
 185}
 186
 187/**
 188 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 189 * @chip: NAND chip object
 190 *
 191 * Wait for the ready pin after a command, and warn if a timeout occurs.
 192 */
 193void nand_wait_ready(struct nand_chip *chip)
 194{
 195        unsigned long timeo = 400;
 196
 197        if (in_interrupt() || oops_in_progress)
 198                return panic_nand_wait_ready(chip, timeo);
 199
 200        /* Wait until command is processed or timeout occurs */
 201        timeo = jiffies + msecs_to_jiffies(timeo);
 202        do {
 203                if (chip->legacy.dev_ready(chip))
 204                        return;
 205                cond_resched();
 206        } while (time_before(jiffies, timeo));
 207
 208        if (!chip->legacy.dev_ready(chip))
 209                pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
 210}
 211EXPORT_SYMBOL_GPL(nand_wait_ready);
 212
 213/**
 214 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 215 * @chip: NAND chip object
 216 * @timeo: Timeout in ms
 217 *
 218 * Wait for status ready (i.e. command done) or timeout.
 219 */
 220static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
 221{
 222        int ret;
 223
 224        timeo = jiffies + msecs_to_jiffies(timeo);
 225        do {
 226                u8 status;
 227
 228                ret = nand_read_data_op(chip, &status, sizeof(status), true);
 229                if (ret)
 230                        return;
 231
 232                if (status & NAND_STATUS_READY)
 233                        break;
 234                touch_softlockup_watchdog();
 235        } while (time_before(jiffies, timeo));
 236};
 237
 238/**
 239 * nand_command - [DEFAULT] Send command to NAND device
 240 * @chip: NAND chip object
 241 * @command: the command to be sent
 242 * @column: the column address for this command, -1 if none
 243 * @page_addr: the page address for this command, -1 if none
 244 *
 245 * Send command to NAND device. This function is used for small page devices
 246 * (512 Bytes per page).
 247 */
 248static void nand_command(struct nand_chip *chip, unsigned int command,
 249                         int column, int page_addr)
 250{
 251        struct mtd_info *mtd = nand_to_mtd(chip);
 252        int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 253
 254        /* Write out the command to the device */
 255        if (command == NAND_CMD_SEQIN) {
 256                int readcmd;
 257
 258                if (column >= mtd->writesize) {
 259                        /* OOB area */
 260                        column -= mtd->writesize;
 261                        readcmd = NAND_CMD_READOOB;
 262                } else if (column < 256) {
 263                        /* First 256 bytes --> READ0 */
 264                        readcmd = NAND_CMD_READ0;
 265                } else {
 266                        column -= 256;
 267                        readcmd = NAND_CMD_READ1;
 268                }
 269                chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
 270                ctrl &= ~NAND_CTRL_CHANGE;
 271        }
 272        if (command != NAND_CMD_NONE)
 273                chip->legacy.cmd_ctrl(chip, command, ctrl);
 274
 275        /* Address cycle, when necessary */
 276        ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 277        /* Serially input address */
 278        if (column != -1) {
 279                /* Adjust columns for 16 bit buswidth */
 280                if (chip->options & NAND_BUSWIDTH_16 &&
 281                                !nand_opcode_8bits(command))
 282                        column >>= 1;
 283                chip->legacy.cmd_ctrl(chip, column, ctrl);
 284                ctrl &= ~NAND_CTRL_CHANGE;
 285        }
 286        if (page_addr != -1) {
 287                chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
 288                ctrl &= ~NAND_CTRL_CHANGE;
 289                chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
 290                if (chip->options & NAND_ROW_ADDR_3)
 291                        chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
 292        }
 293        chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 294                              NAND_NCE | NAND_CTRL_CHANGE);
 295
 296        /*
 297         * Program and erase have their own busy handlers status and sequential
 298         * in needs no delay
 299         */
 300        switch (command) {
 301
 302        case NAND_CMD_NONE:
 303        case NAND_CMD_PAGEPROG:
 304        case NAND_CMD_ERASE1:
 305        case NAND_CMD_ERASE2:
 306        case NAND_CMD_SEQIN:
 307        case NAND_CMD_STATUS:
 308        case NAND_CMD_READID:
 309        case NAND_CMD_SET_FEATURES:
 310                return;
 311
 312        case NAND_CMD_RESET:
 313                if (chip->legacy.dev_ready)
 314                        break;
 315                udelay(chip->legacy.chip_delay);
 316                chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
 317                                      NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 318                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 319                                      NAND_NCE | NAND_CTRL_CHANGE);
 320                /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 321                nand_wait_status_ready(chip, 250);
 322                return;
 323
 324                /* This applies to read commands */
 325        case NAND_CMD_READ0:
 326                /*
 327                 * READ0 is sometimes used to exit GET STATUS mode. When this
 328                 * is the case no address cycles are requested, and we can use
 329                 * this information to detect that we should not wait for the
 330                 * device to be ready.
 331                 */
 332                if (column == -1 && page_addr == -1)
 333                        return;
 334                /* fall through */
 335
 336        default:
 337                /*
 338                 * If we don't have access to the busy pin, we apply the given
 339                 * command delay
 340                 */
 341                if (!chip->legacy.dev_ready) {
 342                        udelay(chip->legacy.chip_delay);
 343                        return;
 344                }
 345        }
 346        /*
 347         * Apply this short delay always to ensure that we do wait tWB in
 348         * any case on any machine.
 349         */
 350        ndelay(100);
 351
 352        nand_wait_ready(chip);
 353}
 354
 355static void nand_ccs_delay(struct nand_chip *chip)
 356{
 357        /*
 358         * The controller already takes care of waiting for tCCS when the RNDIN
 359         * or RNDOUT command is sent, return directly.
 360         */
 361        if (!(chip->options & NAND_WAIT_TCCS))
 362                return;
 363
 364        /*
 365         * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
 366         * (which should be safe for all NANDs).
 367         */
 368        if (nand_has_setup_data_iface(chip))
 369                ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
 370        else
 371                ndelay(500);
 372}
 373
 374/**
 375 * nand_command_lp - [DEFAULT] Send command to NAND large page device
 376 * @chip: NAND chip object
 377 * @command: the command to be sent
 378 * @column: the column address for this command, -1 if none
 379 * @page_addr: the page address for this command, -1 if none
 380 *
 381 * Send command to NAND device. This is the version for the new large page
 382 * devices. We don't have the separate regions as we have in the small page
 383 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 384 */
 385static void nand_command_lp(struct nand_chip *chip, unsigned int command,
 386                            int column, int page_addr)
 387{
 388        struct mtd_info *mtd = nand_to_mtd(chip);
 389
 390        /* Emulate NAND_CMD_READOOB */
 391        if (command == NAND_CMD_READOOB) {
 392                column += mtd->writesize;
 393                command = NAND_CMD_READ0;
 394        }
 395
 396        /* Command latch cycle */
 397        if (command != NAND_CMD_NONE)
 398                chip->legacy.cmd_ctrl(chip, command,
 399                                      NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 400
 401        if (column != -1 || page_addr != -1) {
 402                int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 403
 404                /* Serially input address */
 405                if (column != -1) {
 406                        /* Adjust columns for 16 bit buswidth */
 407                        if (chip->options & NAND_BUSWIDTH_16 &&
 408                                        !nand_opcode_8bits(command))
 409                                column >>= 1;
 410                        chip->legacy.cmd_ctrl(chip, column, ctrl);
 411                        ctrl &= ~NAND_CTRL_CHANGE;
 412
 413                        /* Only output a single addr cycle for 8bits opcodes. */
 414                        if (!nand_opcode_8bits(command))
 415                                chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
 416                }
 417                if (page_addr != -1) {
 418                        chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
 419                        chip->legacy.cmd_ctrl(chip, page_addr >> 8,
 420                                             NAND_NCE | NAND_ALE);
 421                        if (chip->options & NAND_ROW_ADDR_3)
 422                                chip->legacy.cmd_ctrl(chip, page_addr >> 16,
 423                                                      NAND_NCE | NAND_ALE);
 424                }
 425        }
 426        chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 427                              NAND_NCE | NAND_CTRL_CHANGE);
 428
 429        /*
 430         * Program and erase have their own busy handlers status, sequential
 431         * in and status need no delay.
 432         */
 433        switch (command) {
 434
 435        case NAND_CMD_NONE:
 436        case NAND_CMD_CACHEDPROG:
 437        case NAND_CMD_PAGEPROG:
 438        case NAND_CMD_ERASE1:
 439        case NAND_CMD_ERASE2:
 440        case NAND_CMD_SEQIN:
 441        case NAND_CMD_STATUS:
 442        case NAND_CMD_READID:
 443        case NAND_CMD_SET_FEATURES:
 444                return;
 445
 446        case NAND_CMD_RNDIN:
 447                nand_ccs_delay(chip);
 448                return;
 449
 450        case NAND_CMD_RESET:
 451                if (chip->legacy.dev_ready)
 452                        break;
 453                udelay(chip->legacy.chip_delay);
 454                chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
 455                                      NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 456                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 457                                      NAND_NCE | NAND_CTRL_CHANGE);
 458                /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 459                nand_wait_status_ready(chip, 250);
 460                return;
 461
 462        case NAND_CMD_RNDOUT:
 463                /* No ready / busy check necessary */
 464                chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
 465                                      NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 466                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 467                                      NAND_NCE | NAND_CTRL_CHANGE);
 468
 469                nand_ccs_delay(chip);
 470                return;
 471
 472        case NAND_CMD_READ0:
 473                /*
 474                 * READ0 is sometimes used to exit GET STATUS mode. When this
 475                 * is the case no address cycles are requested, and we can use
 476                 * this information to detect that READSTART should not be
 477                 * issued.
 478                 */
 479                if (column == -1 && page_addr == -1)
 480                        return;
 481
 482                chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
 483                                      NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 484                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
 485                                      NAND_NCE | NAND_CTRL_CHANGE);
 486
 487                /* fall through - This applies to read commands */
 488        default:
 489                /*
 490                 * If we don't have access to the busy pin, we apply the given
 491                 * command delay.
 492                 */
 493                if (!chip->legacy.dev_ready) {
 494                        udelay(chip->legacy.chip_delay);
 495                        return;
 496                }
 497        }
 498
 499        /*
 500         * Apply this short delay always to ensure that we do wait tWB in
 501         * any case on any machine.
 502         */
 503        ndelay(100);
 504
 505        nand_wait_ready(chip);
 506}
 507
 508/**
 509 * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
 510 * @chip: nand chip info structure
 511 * @addr: feature address.
 512 * @subfeature_param: the subfeature parameters, a four bytes array.
 513 *
 514 * Should be used by NAND controller drivers that do not support the SET/GET
 515 * FEATURES operations.
 516 */
 517int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
 518                                  u8 *subfeature_param)
 519{
 520        return -ENOTSUPP;
 521}
 522EXPORT_SYMBOL(nand_get_set_features_notsupp);
 523
 524/**
 525 * nand_wait - [DEFAULT] wait until the command is done
 526 * @chip: NAND chip structure
 527 *
 528 * Wait for command done. This applies to erase and program only.
 529 */
 530static int nand_wait(struct nand_chip *chip)
 531{
 532
 533        unsigned long timeo = 400;
 534        u8 status;
 535        int ret;
 536
 537        /*
 538         * Apply this short delay always to ensure that we do wait tWB in any
 539         * case on any machine.
 540         */
 541        ndelay(100);
 542
 543        ret = nand_status_op(chip, NULL);
 544        if (ret)
 545                return ret;
 546
 547        if (in_interrupt() || oops_in_progress)
 548                panic_nand_wait(chip, timeo);
 549        else {
 550                timeo = jiffies + msecs_to_jiffies(timeo);
 551                do {
 552                        if (chip->legacy.dev_ready) {
 553                                if (chip->legacy.dev_ready(chip))
 554                                        break;
 555                        } else {
 556                                ret = nand_read_data_op(chip, &status,
 557                                                        sizeof(status), true);
 558                                if (ret)
 559                                        return ret;
 560
 561                                if (status & NAND_STATUS_READY)
 562                                        break;
 563                        }
 564                        cond_resched();
 565                } while (time_before(jiffies, timeo));
 566        }
 567
 568        ret = nand_read_data_op(chip, &status, sizeof(status), true);
 569        if (ret)
 570                return ret;
 571
 572        /* This can happen if in case of timeout or buggy dev_ready */
 573        WARN_ON(!(status & NAND_STATUS_READY));
 574        return status;
 575}
 576
 577void nand_legacy_set_defaults(struct nand_chip *chip)
 578{
 579        unsigned int busw = chip->options & NAND_BUSWIDTH_16;
 580
 581        if (nand_has_exec_op(chip))
 582                return;
 583
 584        /* check for proper chip_delay setup, set 20us if not */
 585        if (!chip->legacy.chip_delay)
 586                chip->legacy.chip_delay = 20;
 587
 588        /* check, if a user supplied command function given */
 589        if (!chip->legacy.cmdfunc)
 590                chip->legacy.cmdfunc = nand_command;
 591
 592        /* check, if a user supplied wait function given */
 593        if (chip->legacy.waitfunc == NULL)
 594                chip->legacy.waitfunc = nand_wait;
 595
 596        if (!chip->legacy.select_chip)
 597                chip->legacy.select_chip = nand_select_chip;
 598
 599        /* If called twice, pointers that depend on busw may need to be reset */
 600        if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
 601                chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
 602        if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
 603                chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
 604        if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
 605                chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
 606        if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
 607                chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
 608}
 609
 610void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
 611{
 612        struct mtd_info *mtd = nand_to_mtd(chip);
 613
 614        /* Do not replace user supplied command function! */
 615        if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
 616                chip->legacy.cmdfunc = nand_command_lp;
 617}
 618
 619int nand_legacy_check_hooks(struct nand_chip *chip)
 620{
 621        /*
 622         * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
 623         * not populated.
 624         */
 625        if (nand_has_exec_op(chip))
 626                return 0;
 627
 628        /*
 629         * Default functions assigned for ->legacy.cmdfunc() and
 630         * ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
 631         *  populated.
 632         */
 633        if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
 634            !chip->legacy.cmd_ctrl) {
 635                pr_err("->legacy.cmd_ctrl() should be provided\n");
 636                return -EINVAL;
 637        }
 638
 639        return 0;
 640}
 641