linux/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
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   1/*
   2 * Copyright (C) 1999 - 2010 Intel Corporation.
   3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   4 *
   5 * This code was derived from the Intel e1000e Linux driver.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; version 2 of the License.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "pch_gbe.h"
  21#include "pch_gbe_phy.h"
  22
  23#define PHY_MAX_REG_ADDRESS   0x1F      /* 5 bit address bus (0-0x1F) */
  24
  25/* PHY 1000 MII Register/Bit Definitions */
  26/* PHY Registers defined by IEEE */
  27#define PHY_CONTROL           0x00  /* Control Register */
  28#define PHY_STATUS            0x01  /* Status Regiser */
  29#define PHY_ID1               0x02  /* Phy Id Register (word 1) */
  30#define PHY_ID2               0x03  /* Phy Id Register (word 2) */
  31#define PHY_AUTONEG_ADV       0x04  /* Autoneg Advertisement */
  32#define PHY_LP_ABILITY        0x05  /* Link Partner Ability (Base Page) */
  33#define PHY_AUTONEG_EXP       0x06  /* Autoneg Expansion Register */
  34#define PHY_NEXT_PAGE_TX      0x07  /* Next Page TX */
  35#define PHY_LP_NEXT_PAGE      0x08  /* Link Partner Next Page */
  36#define PHY_1000T_CTRL        0x09  /* 1000Base-T Control Register */
  37#define PHY_1000T_STATUS      0x0A  /* 1000Base-T Status Register */
  38#define PHY_EXT_STATUS        0x0F  /* Extended Status Register */
  39#define PHY_PHYSP_CONTROL     0x10  /* PHY Specific Control Register */
  40#define PHY_EXT_PHYSP_CONTROL 0x14  /* Extended PHY Specific Control Register */
  41#define PHY_LED_CONTROL       0x18  /* LED Control Register */
  42#define PHY_EXT_PHYSP_STATUS  0x1B  /* Extended PHY Specific Status Register */
  43
  44/* PHY Control Register */
  45#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
  46#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
  47#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
  48#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
  49#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
  50#define MII_CR_POWER_DOWN       0x0800  /* Power down */
  51#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
  52#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
  53#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
  54#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
  55#define MII_CR_SPEED_1000       0x0040
  56#define MII_CR_SPEED_100        0x2000
  57#define MII_CR_SPEED_10         0x0000
  58
  59/* PHY Status Register */
  60#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
  61#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
  62#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
  63#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
  64#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
  65#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
  66#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
  67#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
  68#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
  69#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
  70#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
  71#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
  72#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
  73#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
  74#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
  75
  76/* AR8031 PHY Debug Registers */
  77#define PHY_AR803X_ID           0x00001374
  78#define PHY_AR8031_DBG_OFF      0x1D
  79#define PHY_AR8031_DBG_DAT      0x1E
  80#define PHY_AR8031_SERDES       0x05
  81#define PHY_AR8031_HIBERNATE    0x0B
  82#define PHY_AR8031_SERDES_TX_CLK_DLY   0x0100 /* TX clock delay of 2.0ns */
  83#define PHY_AR8031_PS_HIB_EN           0x8000 /* Hibernate enable */
  84
  85/* Phy Id Register (word 2) */
  86#define PHY_REVISION_MASK        0x000F
  87
  88/* PHY Specific Control Register */
  89#define PHYSP_CTRL_ASSERT_CRS_TX  0x0800
  90
  91
  92/* Default value of PHY register */
  93#define PHY_CONTROL_DEFAULT         0x1140 /* Control Register */
  94#define PHY_AUTONEG_ADV_DEFAULT     0x01e0 /* Autoneg Advertisement */
  95#define PHY_NEXT_PAGE_TX_DEFAULT    0x2001 /* Next Page TX */
  96#define PHY_1000T_CTRL_DEFAULT      0x0300 /* 1000Base-T Control Register */
  97#define PHY_PHYSP_CONTROL_DEFAULT   0x01EE /* PHY Specific Control Register */
  98
  99/**
 100 * pch_gbe_phy_get_id - Retrieve the PHY ID and revision
 101 * @hw:        Pointer to the HW structure
 102 * Returns
 103 *      0:                      Successful.
 104 *      Negative value:         Failed.
 105 */
 106s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw)
 107{
 108        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 109        struct pch_gbe_phy_info *phy = &hw->phy;
 110        s32 ret;
 111        u16 phy_id1;
 112        u16 phy_id2;
 113
 114        ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID1, &phy_id1);
 115        if (ret)
 116                return ret;
 117        ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID2, &phy_id2);
 118        if (ret)
 119                return ret;
 120        /*
 121         * PHY_ID1: [bit15-0:ID(21-6)]
 122         * PHY_ID2: [bit15-10:ID(5-0)][bit9-4:Model][bit3-0:revision]
 123         */
 124        phy->id = (u32)phy_id1;
 125        phy->id = ((phy->id << 6) | ((phy_id2 & 0xFC00) >> 10));
 126        phy->revision = (u32) (phy_id2 & 0x000F);
 127        netdev_dbg(adapter->netdev,
 128                   "phy->id : 0x%08x  phy->revision : 0x%08x\n",
 129                   phy->id, phy->revision);
 130        return 0;
 131}
 132
 133/**
 134 * pch_gbe_phy_read_reg_miic - Read MII control register
 135 * @hw:      Pointer to the HW structure
 136 * @offset:  Register offset to be read
 137 * @data:    Pointer to the read data
 138 * Returns
 139 *      0:              Successful.
 140 *      -EINVAL:        Invalid argument.
 141 */
 142s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data)
 143{
 144        struct pch_gbe_phy_info *phy = &hw->phy;
 145
 146        if (offset > PHY_MAX_REG_ADDRESS) {
 147                struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 148
 149                netdev_err(adapter->netdev, "PHY Address %d is out of range\n",
 150                           offset);
 151                return -EINVAL;
 152        }
 153        *data = pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_READ,
 154                                      offset, (u16)0);
 155        return 0;
 156}
 157
 158/**
 159 * pch_gbe_phy_write_reg_miic - Write MII control register
 160 * @hw:      Pointer to the HW structure
 161 * @offset:  Register offset to be read
 162 * @data:    data to write to register at offset
 163 * Returns
 164 *      0:              Successful.
 165 *      -EINVAL:        Invalid argument.
 166 */
 167s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data)
 168{
 169        struct pch_gbe_phy_info *phy = &hw->phy;
 170
 171        if (offset > PHY_MAX_REG_ADDRESS) {
 172                struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 173
 174                netdev_err(adapter->netdev, "PHY Address %d is out of range\n",
 175                           offset);
 176                return -EINVAL;
 177        }
 178        pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_WRITE,
 179                                 offset, data);
 180        return 0;
 181}
 182
 183/**
 184 * pch_gbe_phy_sw_reset - PHY software reset
 185 * @hw:             Pointer to the HW structure
 186 */
 187static void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw)
 188{
 189        u16 phy_ctrl;
 190
 191        pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &phy_ctrl);
 192        phy_ctrl |= MII_CR_RESET;
 193        pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl);
 194        udelay(1);
 195}
 196
 197/**
 198 * pch_gbe_phy_hw_reset - PHY hardware reset
 199 * @hw:    Pointer to the HW structure
 200 */
 201void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw)
 202{
 203        pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT);
 204        pch_gbe_phy_write_reg_miic(hw, PHY_AUTONEG_ADV,
 205                                        PHY_AUTONEG_ADV_DEFAULT);
 206        pch_gbe_phy_write_reg_miic(hw, PHY_NEXT_PAGE_TX,
 207                                        PHY_NEXT_PAGE_TX_DEFAULT);
 208        pch_gbe_phy_write_reg_miic(hw, PHY_1000T_CTRL, PHY_1000T_CTRL_DEFAULT);
 209        pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL,
 210                                        PHY_PHYSP_CONTROL_DEFAULT);
 211}
 212
 213/**
 214 * pch_gbe_phy_power_up - restore link in case the phy was powered down
 215 * @hw:    Pointer to the HW structure
 216 */
 217void pch_gbe_phy_power_up(struct pch_gbe_hw *hw)
 218{
 219        u16 mii_reg;
 220
 221        mii_reg = 0;
 222        /* Just clear the power down bit to wake the phy back up */
 223        /* according to the manual, the phy will retain its
 224         * settings across a power-down/up cycle */
 225        pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg);
 226        mii_reg &= ~MII_CR_POWER_DOWN;
 227        pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg);
 228}
 229
 230/**
 231 * pch_gbe_phy_power_down - Power down PHY
 232 * @hw:    Pointer to the HW structure
 233 */
 234void pch_gbe_phy_power_down(struct pch_gbe_hw *hw)
 235{
 236        u16 mii_reg;
 237
 238        mii_reg = 0;
 239        /* Power down the PHY so no link is implied when interface is down *
 240         * The PHY cannot be powered down if any of the following is TRUE *
 241         * (a) WoL is enabled
 242         * (b) AMT is active
 243         */
 244        pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg);
 245        mii_reg |= MII_CR_POWER_DOWN;
 246        pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg);
 247        mdelay(1);
 248}
 249
 250/**
 251 * pch_gbe_phy_set_rgmii - RGMII interface setting
 252 * @hw:             Pointer to the HW structure
 253 */
 254void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw)
 255{
 256        pch_gbe_phy_sw_reset(hw);
 257}
 258
 259/**
 260 * pch_gbe_phy_tx_clk_delay - Setup TX clock delay via the PHY
 261 * @hw:             Pointer to the HW structure
 262 * Returns
 263 *      0:              Successful.
 264 *      -EINVAL:        Invalid argument.
 265 */
 266static int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw)
 267{
 268        /* The RGMII interface requires a ~2ns TX clock delay. This is typically
 269         * done in layout with a longer trace or via PHY strapping, but can also
 270         * be done via PHY configuration registers.
 271         */
 272        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 273        u16 mii_reg;
 274        int ret = 0;
 275
 276        switch (hw->phy.id) {
 277        case PHY_AR803X_ID:
 278                netdev_dbg(adapter->netdev,
 279                           "Configuring AR803X PHY for 2ns TX clock delay\n");
 280                pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_OFF, &mii_reg);
 281                ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
 282                                                 PHY_AR8031_SERDES);
 283                if (ret)
 284                        break;
 285
 286                pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg);
 287                mii_reg |= PHY_AR8031_SERDES_TX_CLK_DLY;
 288                ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
 289                                                 mii_reg);
 290                break;
 291        default:
 292                netdev_err(adapter->netdev,
 293                           "Unknown PHY (%x), could not set TX clock delay\n",
 294                           hw->phy.id);
 295                return -EINVAL;
 296        }
 297
 298        if (ret)
 299                netdev_err(adapter->netdev,
 300                           "Could not configure tx clock delay for PHY\n");
 301        return ret;
 302}
 303
 304/**
 305 * pch_gbe_phy_init_setting - PHY initial setting
 306 * @hw:             Pointer to the HW structure
 307 */
 308void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw)
 309{
 310        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 311        struct ethtool_cmd     cmd = { .cmd = ETHTOOL_GSET };
 312        int ret;
 313        u16 mii_reg;
 314
 315        ret = mii_ethtool_gset(&adapter->mii, &cmd);
 316        if (ret)
 317                netdev_err(adapter->netdev, "Error: mii_ethtool_gset\n");
 318
 319        ethtool_cmd_speed_set(&cmd, hw->mac.link_speed);
 320        cmd.duplex = hw->mac.link_duplex;
 321        cmd.advertising = hw->phy.autoneg_advertised;
 322        cmd.autoneg = hw->mac.autoneg;
 323        pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET);
 324        ret = mii_ethtool_sset(&adapter->mii, &cmd);
 325        if (ret)
 326                netdev_err(adapter->netdev, "Error: mii_ethtool_sset\n");
 327
 328        pch_gbe_phy_sw_reset(hw);
 329
 330        pch_gbe_phy_read_reg_miic(hw, PHY_PHYSP_CONTROL, &mii_reg);
 331        mii_reg |= PHYSP_CTRL_ASSERT_CRS_TX;
 332        pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg);
 333
 334        /* Setup a TX clock delay on certain platforms */
 335        if (adapter->pdata && adapter->pdata->phy_tx_clk_delay)
 336                pch_gbe_phy_tx_clk_delay(hw);
 337}
 338
 339/**
 340 * pch_gbe_phy_disable_hibernate - Disable the PHY low power state
 341 * @hw:             Pointer to the HW structure
 342 * Returns
 343 *      0:              Successful.
 344 *      -EINVAL:        Invalid argument.
 345 */
 346int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw)
 347{
 348        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 349        u16 mii_reg;
 350        int ret = 0;
 351
 352        switch (hw->phy.id) {
 353        case PHY_AR803X_ID:
 354                netdev_dbg(adapter->netdev,
 355                           "Disabling hibernation for AR803X PHY\n");
 356                ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
 357                                                 PHY_AR8031_HIBERNATE);
 358                if (ret)
 359                        break;
 360
 361                pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg);
 362                mii_reg &= ~PHY_AR8031_PS_HIB_EN;
 363                ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
 364                                                 mii_reg);
 365                break;
 366        default:
 367                netdev_err(adapter->netdev,
 368                           "Unknown PHY (%x), could not disable hibernation\n",
 369                           hw->phy.id);
 370                return -EINVAL;
 371        }
 372
 373        if (ret)
 374                netdev_err(adapter->netdev,
 375                           "Could not disable PHY hibernation\n");
 376        return ret;
 377}
 378