LXR linux/drivers/net/ethernet/smsc/smc91x.h

   1/*------------------------------------------------------------------------
   2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
   3 .
   4 . Copyright (C) 1996 by Erik Stahlman
   5 . Copyright (C) 2001 Standard Microsystems Corporation
   6 .      Developed by Simple Network Magic Corporation
   7 . Copyright (C) 2003 Monta Vista Software, Inc.
   8 .      Unified SMC91x driver by Nicolas Pitre
   9 .
  10 . This program is free software; you can redistribute it and/or modify
  11 . it under the terms of the GNU General Public License as published by
  12 . the Free Software Foundation; either version 2 of the License, or
  13 . (at your option) any later version.
  14 .
  15 . This program is distributed in the hope that it will be useful,
  16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 . GNU General Public License for more details.
  19 .
  20 . You should have received a copy of the GNU General Public License
  21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
  22 .
  23 . Information contained in this file was obtained from the LAN91C111
  24 . manual from SMC.  To get a copy, if you really want one, you can find
  25 . information under www.smsc.com.
  26 .
  27 . Authors
  28 .      Erik Stahlman           <erik@vt.edu>
  29 .      Daris A Nevil           <dnevil@snmc.com>
  30 .      Nicolas Pitre           <nico@fluxnic.net>
  31 .
  32 ---------------------------------------------------------------------------*/
  33#ifndef _SMC91X_H_
  34#define _SMC91X_H_
  35
  36#include <linux/dmaengine.h>
  37#include <linux/smc91x.h>
  38
  39/*
  40 * Any 16-bit access is performed with two 8-bit accesses if the hardware
  41 * can't do it directly. Most registers are 16-bit so those are mandatory.
  42 */
  43#define SMC_outw_b(x, a, r)                                             \
  44        do {                                                            \
  45                unsigned int __val16 = (x);                             \
  46                unsigned int __reg = (r);                               \
  47                SMC_outb(__val16, a, __reg);                            \
  48                SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
  49        } while (0)
  50
  51#define SMC_inw_b(a, r)                                                 \
  52        ({                                                              \
  53                unsigned int __val16;                                   \
  54                unsigned int __reg = r;                                 \
  55                __val16  = SMC_inb(a, __reg);                           \
  56                __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
  57                __val16;                                                \
  58        })
  59
  60/*
  61 * Define your architecture specific bus configuration parameters here.
  62 */
  63
  64#if defined(CONFIG_ARM)
  65
  66#include <asm/mach-types.h>
  67
  68/* Now the bus width is specified in the platform data
  69 * pretend here to support all I/O access types
  70 */
  71#define SMC_CAN_USE_8BIT        1
  72#define SMC_CAN_USE_16BIT       1
  73#define SMC_CAN_USE_32BIT       1
  74#define SMC_NOWAIT              1
  75
  76#define SMC_IO_SHIFT            (lp->io_shift)
  77
  78#define SMC_inb(a, r)           readb((a) + (r))
  79#define SMC_inw(a, r)                                                   \
  80        ({                                                              \
  81                unsigned int __smc_r = r;                               \
  82                SMC_16BIT(lp) ? readw((a) + __smc_r) :                  \
  83                SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) :                  \
  84                ({ BUG(); 0; });                                        \
  85        })
  86
  87#define SMC_inl(a, r)           readl((a) + (r))
  88#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
  89#define SMC_outw(lp, v, a, r)                                           \
  90        do {                                                            \
  91                unsigned int __v = v, __smc_r = r;                      \
  92                if (SMC_16BIT(lp))                                      \
  93                        __SMC_outw(lp, __v, a, __smc_r);                \
  94                else if (SMC_8BIT(lp))                                  \
  95                        SMC_outw_b(__v, a, __smc_r);                    \
  96                else                                                    \
  97                        BUG();                                          \
  98        } while (0)
  99
 100#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 101#define SMC_insb(a, r, p, l)    readsb((a) + (r), p, l)
 102#define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, l)
 103#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 104#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 105#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 106#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 107#define SMC_IRQ_FLAGS           (-1)    /* from resource */
 108
 109/* We actually can't write halfwords properly if not word aligned */
 110static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg,
 111                                    bool use_align4_workaround)
 112{
 113        if (use_align4_workaround) {
 114                unsigned int v = val << 16;
 115                v |= readl(ioaddr + (reg & ~2)) & 0xffff;
 116                writel(v, ioaddr + (reg & ~2));
 117        } else {
 118                writew(val, ioaddr + reg);
 119        }
 120}
 121
 122#define __SMC_outw(lp, v, a, r)                                         \
 123        _SMC_outw_align4((v), (a), (r),                                 \
 124                         IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) &&    \
 125                         (lp)->cfg.pxa_u16_align4)
 126
 127
 128#elif   defined(CONFIG_SH_SH4202_MICRODEV)
 129
 130#define SMC_CAN_USE_8BIT        0
 131#define SMC_CAN_USE_16BIT       1
 132#define SMC_CAN_USE_32BIT       0
 133
 134#define SMC_inb(a, r)           inb((a) + (r) - 0xa0000000)
 135#define SMC_inw(a, r)           inw((a) + (r) - 0xa0000000)
 136#define SMC_inl(a, r)           inl((a) + (r) - 0xa0000000)
 137#define SMC_outb(v, a, r)       outb(v, (a) + (r) - 0xa0000000)
 138#define SMC_outw(lp, v, a, r)   outw(v, (a) + (r) - 0xa0000000)
 139#define SMC_outl(v, a, r)       outl(v, (a) + (r) - 0xa0000000)
 140#define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
 141#define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
 142#define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
 143#define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
 144
 145#define SMC_IRQ_FLAGS           (0)
 146
 147#elif defined(CONFIG_ATARI)
 148
 149#define SMC_CAN_USE_8BIT        1
 150#define SMC_CAN_USE_16BIT       1
 151#define SMC_CAN_USE_32BIT       1
 152#define SMC_NOWAIT              1
 153
 154#define SMC_inb(a, r)           readb((a) + (r))
 155#define SMC_inw(a, r)           readw((a) + (r))
 156#define SMC_inl(a, r)           readl((a) + (r))
 157#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 158#define SMC_outw(lp, v, a, r)   writew(v, (a) + (r))
 159#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 160#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 161#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 162#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 163#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 164
 165#define RPC_LSA_DEFAULT         RPC_LED_100_10
 166#define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 167
 168#elif defined(CONFIG_COLDFIRE)
 169
 170#define SMC_CAN_USE_8BIT        0
 171#define SMC_CAN_USE_16BIT       1
 172#define SMC_CAN_USE_32BIT       0
 173#define SMC_NOWAIT              1
 174
 175static inline void mcf_insw(void *a, unsigned char *p, int l)
 176{
 177        u16 *wp = (u16 *) p;
 178        while (l-- > 0)
 179                *wp++ = readw(a);
 180}
 181
 182static inline void mcf_outsw(void *a, unsigned char *p, int l)
 183{
 184        u16 *wp = (u16 *) p;
 185        while (l-- > 0)
 186                writew(*wp++, a);
 187}
 188
 189#define SMC_inw(a, r)           _swapw(readw((a) + (r)))
 190#define SMC_outw(lp, v, a, r)   writew(_swapw(v), (a) + (r))
 191#define SMC_insw(a, r, p, l)    mcf_insw(a + r, p, l)
 192#define SMC_outsw(a, r, p, l)   mcf_outsw(a + r, p, l)
 193
 194#define SMC_IRQ_FLAGS           0
 195
 196#elif defined(CONFIG_H8300)
 197#define SMC_CAN_USE_8BIT        1
 198#define SMC_CAN_USE_16BIT       0
 199#define SMC_CAN_USE_32BIT       0
 200#define SMC_NOWAIT              0
 201
 202#define SMC_inb(a, r)           ioread8((a) + (r))
 203#define SMC_outb(v, a, r)       iowrite8(v, (a) + (r))
 204#define SMC_insb(a, r, p, l)    ioread8_rep((a) + (r), p, l)
 205#define SMC_outsb(a, r, p, l)   iowrite8_rep((a) + (r), p, l)
 206
 207#else
 208
 209/*
 210 * Default configuration
 211 */
 212
 213#define SMC_CAN_USE_8BIT        1
 214#define SMC_CAN_USE_16BIT       1
 215#define SMC_CAN_USE_32BIT       1
 216#define SMC_NOWAIT              1
 217
 218#define SMC_IO_SHIFT            (lp->io_shift)
 219
 220#define SMC_inb(a, r)           ioread8((a) + (r))
 221#define SMC_inw(a, r)           ioread16((a) + (r))
 222#define SMC_inl(a, r)           ioread32((a) + (r))
 223#define SMC_outb(v, a, r)       iowrite8(v, (a) + (r))
 224#define SMC_outw(lp, v, a, r)   iowrite16(v, (a) + (r))
 225#define SMC_outl(v, a, r)       iowrite32(v, (a) + (r))
 226#define SMC_insw(a, r, p, l)    ioread16_rep((a) + (r), p, l)
 227#define SMC_outsw(a, r, p, l)   iowrite16_rep((a) + (r), p, l)
 228#define SMC_insl(a, r, p, l)    ioread32_rep((a) + (r), p, l)
 229#define SMC_outsl(a, r, p, l)   iowrite32_rep((a) + (r), p, l)
 230
 231#define RPC_LSA_DEFAULT         RPC_LED_100_10
 232#define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 233
 234#endif
 235
 236
 237/* store this information for the driver.. */
 238struct smc_local {
 239        /*
 240         * If I have to wait until memory is available to send a
 241         * packet, I will store the skbuff here, until I get the
 242         * desired memory.  Then, I'll send it out and free it.
 243         */
 244        struct sk_buff *pending_tx_skb;
 245        struct tasklet_struct tx_task;
 246
 247        struct gpio_desc *power_gpio;
 248        struct gpio_desc *reset_gpio;
 249
 250        /* version/revision of the SMC91x chip */
 251        int     version;
 252
 253        /* Contains the current active transmission mode */
 254        int     tcr_cur_mode;
 255
 256        /* Contains the current active receive mode */
 257        int     rcr_cur_mode;
 258
 259        /* Contains the current active receive/phy mode */
 260        int     rpc_cur_mode;
 261        int     ctl_rfduplx;
 262        int     ctl_rspeed;
 263
 264        u32     msg_enable;
 265        u32     phy_type;
 266        struct mii_if_info mii;
 267
 268        /* work queue */
 269        struct work_struct phy_configure;
 270        struct net_device *dev;
 271        int     work_pending;
 272
 273        spinlock_t lock;
 274
 275#ifdef CONFIG_ARCH_PXA
 276        /* DMA needs the physical address of the chip */
 277        u_long physaddr;
 278        struct device *device;
 279#endif
 280        struct dma_chan *dma_chan;
 281        void __iomem *base;
 282        void __iomem *datacs;
 283
 284        /* the low address lines on some platforms aren't connected... */
 285        int     io_shift;
 286        /* on some platforms a u16 write must be 4-bytes aligned */
 287        bool    half_word_align4;
 288
 289        struct smc91x_platdata cfg;
 290};
 291
 292#define SMC_8BIT(p)     ((p)->cfg.flags & SMC91X_USE_8BIT)
 293#define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
 294#define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
 295
 296#ifdef CONFIG_ARCH_PXA
 297/*
 298 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
 299 * always happening in irq context so no need to worry about races.  TX is
 300 * different and probably not worth it for that reason, and not as critical
 301 * as RX which can overrun memory and lose packets.
 302 */
 303#include <linux/dma-mapping.h>
 304
 305#ifdef SMC_insl
 306#undef SMC_insl
 307#define SMC_insl(a, r, p, l) \
 308        smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 309static inline void
 310smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
 311{
 312        dma_addr_t dmabuf;
 313        struct dma_async_tx_descriptor *tx;
 314        dma_cookie_t cookie;
 315        enum dma_status status;
 316        struct dma_tx_state state;
 317
 318        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 319        tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
 320                                         DMA_DEV_TO_MEM, 0);
 321        if (tx) {
 322                cookie = dmaengine_submit(tx);
 323                dma_async_issue_pending(lp->dma_chan);
 324                do {
 325                        status = dmaengine_tx_status(lp->dma_chan, cookie,
 326                                                     &state);
 327                        cpu_relax();
 328                } while (status != DMA_COMPLETE && status != DMA_ERROR &&
 329                         state.residue);
 330                dmaengine_terminate_all(lp->dma_chan);
 331        }
 332        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 333}
 334
 335static inline void
 336smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 337                 u_char *buf, int len)
 338{
 339        struct dma_slave_config config;
 340        int ret;
 341
 342        /* fallback if no DMA available */
 343        if (!lp->dma_chan) {
 344                readsl(ioaddr + reg, buf, len);
 345                return;
 346        }
 347
 348        /* 64 bit alignment is required for memory to memory DMA */
 349        if ((long)buf & 4) {
 350                *((u32 *)buf) = SMC_inl(ioaddr, reg);
 351                buf += 4;
 352                len--;
 353        }
 354
 355        memset(&config, 0, sizeof(config));
 356        config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 357        config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 358        config.src_addr = lp->physaddr + reg;
 359        config.dst_addr = lp->physaddr + reg;
 360        config.src_maxburst = 32;
 361        config.dst_maxburst = 32;
 362        ret = dmaengine_slave_config(lp->dma_chan, &config);
 363        if (ret) {
 364                dev_err(lp->device, "dma channel configuration failed: %d\n",
 365                        ret);
 366                return;
 367        }
 368
 369        len *= 4;
 370        smc_pxa_dma_inpump(lp, buf, len);
 371}
 372#endif
 373
 374#ifdef SMC_insw
 375#undef SMC_insw
 376#define SMC_insw(a, r, p, l) \
 377        smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 378static inline void
 379smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 380                 u_char *buf, int len)
 381{
 382        struct dma_slave_config config;
 383        int ret;
 384
 385        /* fallback if no DMA available */
 386        if (!lp->dma_chan) {
 387                readsw(ioaddr + reg, buf, len);
 388                return;
 389        }
 390
 391        /* 64 bit alignment is required for memory to memory DMA */
 392        while ((long)buf & 6) {
 393                *((u16 *)buf) = SMC_inw(ioaddr, reg);
 394                buf += 2;
 395                len--;
 396        }
 397
 398        memset(&config, 0, sizeof(config));
 399        config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 400        config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 401        config.src_addr = lp->physaddr + reg;
 402        config.dst_addr = lp->physaddr + reg;
 403        config.src_maxburst = 32;
 404        config.dst_maxburst = 32;
 405        ret = dmaengine_slave_config(lp->dma_chan, &config);
 406        if (ret) {
 407                dev_err(lp->device, "dma channel configuration failed: %d\n",
 408                        ret);
 409                return;
 410        }
 411
 412        len *= 2;
 413        smc_pxa_dma_inpump(lp, buf, len);
 414}
 415#endif
 416
 417#endif  /* CONFIG_ARCH_PXA */
 418
 419
 420/*
 421 * Everything a particular hardware setup needs should have been defined
 422 * at this point.  Add stubs for the undefined cases, mainly to avoid
 423 * compilation warnings since they'll be optimized away, or to prevent buggy
 424 * use of them.
 425 */
 426
 427#if ! SMC_CAN_USE_32BIT
 428#define SMC_inl(ioaddr, reg)            ({ BUG(); 0; })
 429#define SMC_outl(x, ioaddr, reg)        BUG()
 430#define SMC_insl(a, r, p, l)            BUG()
 431#define SMC_outsl(a, r, p, l)           BUG()
 432#endif
 433
 434#if !defined(SMC_insl) || !defined(SMC_outsl)
 435#define SMC_insl(a, r, p, l)            BUG()
 436#define SMC_outsl(a, r, p, l)           BUG()
 437#endif
 438
 439#if ! SMC_CAN_USE_16BIT
 440
 441#define SMC_outw(lp, x, ioaddr, reg)    SMC_outw_b(x, ioaddr, reg)
 442#define SMC_inw(ioaddr, reg)            SMC_inw_b(ioaddr, reg)
 443#define SMC_insw(a, r, p, l)            BUG()
 444#define SMC_outsw(a, r, p, l)           BUG()
 445
 446#endif
 447
 448#if !defined(SMC_insw) || !defined(SMC_outsw)
 449#define SMC_insw(a, r, p, l)            BUG()
 450#define SMC_outsw(a, r, p, l)           BUG()
 451#endif
 452
 453#if ! SMC_CAN_USE_8BIT
 454#undef SMC_inb
 455#define SMC_inb(ioaddr, reg)            ({ BUG(); 0; })
 456#undef SMC_outb
 457#define SMC_outb(x, ioaddr, reg)        BUG()
 458#define SMC_insb(a, r, p, l)            BUG()
 459#define SMC_outsb(a, r, p, l)           BUG()
 460#endif
 461
 462#if !defined(SMC_insb) || !defined(SMC_outsb)
 463#define SMC_insb(a, r, p, l)            BUG()
 464#define SMC_outsb(a, r, p, l)           BUG()
 465#endif
 466
 467#ifndef SMC_CAN_USE_DATACS
 468#define SMC_CAN_USE_DATACS      0
 469#endif
 470
 471#ifndef SMC_IO_SHIFT
 472#define SMC_IO_SHIFT    0
 473#endif
 474
 475#ifndef SMC_IRQ_FLAGS
 476#define SMC_IRQ_FLAGS           IRQF_TRIGGER_RISING
 477#endif
 478
 479#ifndef SMC_INTERRUPT_PREAMBLE
 480#define SMC_INTERRUPT_PREAMBLE
 481#endif
 482
 483
 484/* Because of bank switching, the LAN91x uses only 16 I/O ports */
 485#define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
 486#define SMC_DATA_EXTENT (4)
 487
 488/*
 489 . Bank Select Register:
 490 .
 491 .              yyyy yyyy 0000 00xx
 492 .              xx              = bank number
 493 .              yyyy yyyy       = 0x33, for identification purposes.
 494*/
 495#define BANK_SELECT             (14 << SMC_IO_SHIFT)
 496
 497
 498// Transmit Control Register
 499/* BANK 0  */
 500#define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
 501#define TCR_ENABLE      0x0001  // When 1 we can transmit
 502#define TCR_LOOP        0x0002  // Controls output pin LBK
 503#define TCR_FORCOL      0x0004  // When 1 will force a collision
 504#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
 505#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
 506#define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
 507#define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
 508#define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
 509#define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
 510#define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
 511
 512#define TCR_CLEAR       0       /* do NOTHING */
 513/* the default settings for the TCR register : */
 514#define TCR_DEFAULT     (TCR_ENABLE | TCR_PAD_EN)
 515
 516
 517// EPH Status Register
 518/* BANK 0  */
 519#define EPH_STATUS_REG(lp)      SMC_REG(lp, 0x0002, 0)
 520#define ES_TX_SUC       0x0001  // Last TX was successful
 521#define ES_SNGL_COL     0x0002  // Single collision detected for last tx
 522#define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
 523#define ES_LTX_MULT     0x0008  // Last tx was a multicast
 524#define ES_16COL        0x0010  // 16 Collisions Reached
 525#define ES_SQET         0x0020  // Signal Quality Error Test
 526#define ES_LTXBRD       0x0040  // Last tx was a broadcast
 527#define ES_TXDEFR       0x0080  // Transmit Deferred
 528#define ES_LATCOL       0x0200  // Late collision detected on last tx
 529#define ES_LOSTCARR     0x0400  // Lost Carrier Sense
 530#define ES_EXC_DEF      0x0800  // Excessive Deferral
 531#define ES_CTR_ROL      0x1000  // Counter Roll Over indication
 532#define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
 533#define ES_TXUNRN       0x8000  // Tx Underrun
 534
 535
 536// Receive Control Register
 537/* BANK 0  */
 538#define RCR_REG(lp)             SMC_REG(lp, 0x0004, 0)
 539#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
 540#define RCR_PRMS        0x0002  // Enable promiscuous mode
 541#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
 542#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
 543#define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
 544#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
 545#define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
 546#define RCR_SOFTRST     0x8000  // resets the chip
 547
 548/* the normal settings for the RCR register : */
 549#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
 550#define RCR_CLEAR       0x0     // set it to a base state
 551
 552
 553// Counter Register
 554/* BANK 0  */
 555#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
 556
 557
 558// Memory Information Register
 559/* BANK 0  */
 560#define MIR_REG(lp)             SMC_REG(lp, 0x0008, 0)
 561
 562
 563// Receive/Phy Control Register
 564/* BANK 0  */
 565#define RPC_REG(lp)             SMC_REG(lp, 0x000A, 0)
 566#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 567#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 568#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 569#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 570#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 571
 572#ifndef RPC_LSA_DEFAULT
 573#define RPC_LSA_DEFAULT RPC_LED_100
 574#endif
 575#ifndef RPC_LSB_DEFAULT
 576#define RPC_LSB_DEFAULT RPC_LED_FD
 577#endif
 578
 579#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 580
 581
 582/* Bank 0 0x0C is reserved */
 583
 584// Bank Select Register
 585/* All Banks */
 586#define BSR_REG         0x000E
 587
 588
 589// Configuration Reg
 590/* BANK 1 */
 591#define CONFIG_REG(lp)  SMC_REG(lp, 0x0000,     1)
 592#define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
 593#define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
 594#define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
 595#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
 596
 597// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
 598#define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
 599
 600
 601// Base Address Register
 602/* BANK 1 */
 603#define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
 604
 605
 606// Individual Address Registers
 607/* BANK 1 */
 608#define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
 609#define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
 610#define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
 611
 612
 613// General Purpose Register
 614/* BANK 1 */
 615#define GP_REG(lp)              SMC_REG(lp, 0x000A, 1)
 616
 617
 618// Control Register
 619/* BANK 1 */
 620#define CTL_REG(lp)             SMC_REG(lp, 0x000C, 1)
 621#define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
 622#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 623#define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
 624#define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
 625#define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
 626#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
 627#define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
 628#define CTL_STORE       0x0001 // When set stores registers into EEPROM
 629
 630
 631// MMU Command Register
 632/* BANK 2 */
 633#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
 634#define MC_BUSY         1       // When 1 the last release has not completed
 635#define MC_NOP          (0<<5)  // No Op
 636#define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
 637#define MC_RESET        (2<<5)  // Reset MMU to initial state
 638#define MC_REMOVE       (3<<5)  // Remove the current rx packet
 639#define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
 640#define MC_FREEPKT      (5<<5)  // Release packet in PNR register
 641#define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
 642#define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
 643
 644
 645// Packet Number Register
 646/* BANK 2 */
 647#define PN_REG(lp)              SMC_REG(lp, 0x0002, 2)
 648
 649
 650// Allocation Result Register
 651/* BANK 2 */
 652#define AR_REG(lp)              SMC_REG(lp, 0x0003, 2)
 653#define AR_FAILED       0x80    // Alocation Failed
 654
 655
 656// TX FIFO Ports Register
 657/* BANK 2 */
 658#define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
 659#define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
 660
 661// RX FIFO Ports Register
 662/* BANK 2 */
 663#define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
 664#define RXFIFO_REMPTY   0x80    // RX FIFO Empty
 665
 666#define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
 667
 668// Pointer Register
 669/* BANK 2 */
 670#define PTR_REG(lp)             SMC_REG(lp, 0x0006, 2)
 671#define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
 672#define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
 673#define PTR_READ        0x2000 // When 1 the operation is a read
 674
 675
 676// Data Register
 677/* BANK 2 */
 678#define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
 679
 680
 681// Interrupt Status/Acknowledge Register
 682/* BANK 2 */
 683#define INT_REG(lp)             SMC_REG(lp, 0x000C, 2)
 684
 685
 686// Interrupt Mask Register
 687/* BANK 2 */
 688#define IM_REG(lp)              SMC_REG(lp, 0x000D, 2)
 689#define IM_MDINT        0x80 // PHY MI Register 18 Interrupt
 690#define IM_ERCV_INT     0x40 // Early Receive Interrupt
 691#define IM_EPH_INT      0x20 // Set by Ethernet Protocol Handler section
 692#define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
 693#define IM_ALLOC_INT    0x08 // Set when allocation request is completed
 694#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
 695#define IM_TX_INT       0x02 // Transmit Interrupt
 696#define IM_RCV_INT      0x01 // Receive Interrupt
 697
 698
 699// Multicast Table Registers
 700/* BANK 3 */
 701#define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
 702#define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
 703#define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
 704#define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
 705
 706
 707// Management Interface Register (MII)
 708/* BANK 3 */
 709#define MII_REG(lp)             SMC_REG(lp, 0x0008, 3)
 710#define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 711#define MII_MDOE        0x0008 // MII Output Enable
 712#define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 713#define MII_MDI         0x0002 // MII Input, pin MDI
 714#define MII_MDO         0x0001 // MII Output, pin MDO
 715
 716
 717// Revision Register
 718/* BANK 3 */
 719/* ( hi: chip id   low: rev # ) */
 720#define REV_REG(lp)             SMC_REG(lp, 0x000A, 3)
 721
 722
 723// Early RCV Register
 724/* BANK 3 */
 725/* this is NOT on SMC9192 */
 726#define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
 727#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
 728#define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
 729
 730
 731// External Register
 732/* BANK 7 */
 733#define EXT_REG(lp)             SMC_REG(lp, 0x0000, 7)
 734
 735
 736#define CHIP_9192       3
 737#define CHIP_9194       4
 738#define CHIP_9195       5
 739#define CHIP_9196       6
 740#define CHIP_91100      7
 741#define CHIP_91100FD    8
 742#define CHIP_91111FD    9
 743
 744static const char * chip_ids[ 16 ] =  {
 745        NULL, NULL, NULL,
 746        /* 3 */ "SMC91C90/91C92",
 747        /* 4 */ "SMC91C94",
 748        /* 5 */ "SMC91C95",
 749        /* 6 */ "SMC91C96",
 750        /* 7 */ "SMC91C100",
 751        /* 8 */ "SMC91C100FD",
 752        /* 9 */ "SMC91C11xFD",
 753        NULL, NULL, NULL,
 754        NULL, NULL, NULL};
 755
 756
 757/*
 758 . Receive status bits
 759*/
 760#define RS_ALGNERR      0x8000
 761#define RS_BRODCAST     0x4000
 762#define RS_BADCRC       0x2000
 763#define RS_ODDFRAME     0x1000
 764#define RS_TOOLONG      0x0800
 765#define RS_TOOSHORT     0x0400
 766#define RS_MULTICAST    0x0001
 767#define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 768
 769
 770/*
 771 * PHY IDs
 772 *  LAN83C183 == LAN91C111 Internal PHY
 773 */
 774#define PHY_LAN83C183   0x0016f840
 775#define PHY_LAN83C180   0x02821c50
 776
 777/*
 778 * PHY Register Addresses (LAN91C111 Internal PHY)
 779 *
 780 * Generic PHY registers can be found in <linux/mii.h>
 781 *
 782 * These phy registers are specific to our on-board phy.
 783 */
 784
 785// PHY Configuration Register 1
 786#define PHY_CFG1_REG            0x10
 787#define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 788#define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 789#define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 790#define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 791#define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 792#define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 793#define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 794#define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 795#define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 796#define PHY_CFG1_TLVL_MASK      0x003C
 797#define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 798
 799
 800// PHY Configuration Register 2
 801#define PHY_CFG2_REG            0x11
 802#define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 803#define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 804#define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 805#define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 806
 807// PHY Status Output (and Interrupt status) Register
 808#define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 809#define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 810#define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 811#define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 812#define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 813#define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 814#define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 815#define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 816#define PHY_INT_JAB             0x0100  // 1=Jabber detected
 817#define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 818#define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 819
 820// PHY Interrupt/Status Mask Register
 821#define PHY_MASK_REG            0x13    // Interrupt Mask
 822// Uses the same bit definitions as PHY_INT_REG
 823
 824
 825/*
 826 * SMC91C96 ethernet config and status registers.
 827 * These are in the "attribute" space.
 828 */
 829#define ECOR                    0x8000
 830#define ECOR_RESET              0x80
 831#define ECOR_LEVEL_IRQ          0x40
 832#define ECOR_WR_ATTRIB          0x04
 833#define ECOR_ENABLE             0x01
 834
 835#define ECSR                    0x8002
 836#define ECSR_IOIS8              0x20
 837#define ECSR_PWRDWN             0x04
 838#define ECSR_INT                0x02
 839
 840#define ATTRIB_SIZE             ((64*1024) << SMC_IO_SHIFT)
 841
 842
 843/*
 844 * Macros to abstract register access according to the data bus
 845 * capabilities.  Please use those and not the in/out primitives.
 846 * Note: the following macros do *not* select the bank -- this must
 847 * be done separately as needed in the main code.  The SMC_REG() macro
 848 * only uses the bank argument for debugging purposes (when enabled).
 849 *
 850 * Note: despite inline functions being safer, everything leading to this
 851 * should preferably be macros to let BUG() display the line number in
 852 * the core source code since we're interested in the top call site
 853 * not in any inline function location.
 854 */
 855
 856#if SMC_DEBUG > 0
 857#define SMC_REG(lp, reg, bank)                                  \
 858        ({                                                              \
 859                int __b = SMC_CURRENT_BANK(lp);                 \
 860                if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
 861                        pr_err("%s: bank reg screwed (0x%04x)\n",       \
 862                               CARDNAME, __b);                          \
 863                        BUG();                                          \
 864                }                                                       \
 865                reg<<SMC_IO_SHIFT;                                      \
 866        })
 867#else
 868#define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
 869#endif
 870
 871/*
 872 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 873 * aligned to a 32 bit boundary.  I tell you that does exist!
 874 * Fortunately the affected register accesses can be easily worked around
 875 * since we can write zeroes to the preceding 16 bits without adverse
 876 * effects and use a 32-bit access.
 877 *
 878 * Enforce it on any 32-bit capable setup for now.
 879 */
 880#define SMC_MUST_ALIGN_WRITE(lp)        SMC_32BIT(lp)
 881
 882#define SMC_GET_PN(lp)                                          \
 883        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
 884                                : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
 885
 886#define SMC_SET_PN(lp, x)                                               \
 887        do {                                                            \
 888                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 889                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
 890                else if (SMC_8BIT(lp))                          \
 891                        SMC_outb(x, ioaddr, PN_REG(lp));                \
 892                else                                                    \
 893                        SMC_outw(lp, x, ioaddr, PN_REG(lp));            \
 894        } while (0)
 895
 896#define SMC_GET_AR(lp)                                          \
 897        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
 898                                : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
 899
 900#define SMC_GET_TXFIFO(lp)                                              \
 901        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
 902                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
 903
 904#define SMC_GET_RXFIFO(lp)                                              \
 905        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
 906                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
 907
 908#define SMC_GET_INT(lp)                                         \
 909        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
 910                                : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
 911
 912#define SMC_ACK_INT(lp, x)                                              \
 913        do {                                                            \
 914                if (SMC_8BIT(lp))                                       \
 915                        SMC_outb(x, ioaddr, INT_REG(lp));               \
 916                else {                                                  \
 917                        unsigned long __flags;                          \
 918                        int __mask;                                     \
 919                        local_irq_save(__flags);                        \
 920                        __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
 921                        SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
 922                        local_irq_restore(__flags);                     \
 923                }                                                       \
 924        } while (0)
 925
 926#define SMC_GET_INT_MASK(lp)                                            \
 927        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
 928                                : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
 929
 930#define SMC_SET_INT_MASK(lp, x)                                 \
 931        do {                                                            \
 932                if (SMC_8BIT(lp))                                       \
 933                        SMC_outb(x, ioaddr, IM_REG(lp));                \
 934                else                                                    \
 935                        SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp));    \
 936        } while (0)
 937
 938#define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
 939
 940#define SMC_SELECT_BANK(lp, x)                                  \
 941        do {                                                            \
 942                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 943                        SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
 944                else                                                    \
 945                        SMC_outw(lp, x, ioaddr, BANK_SELECT);           \
 946        } while (0)
 947
 948#define SMC_GET_BASE(lp)                SMC_inw(ioaddr, BASE_REG(lp))
 949
 950#define SMC_SET_BASE(lp, x)     SMC_outw(lp, x, ioaddr, BASE_REG(lp))
 951
 952#define SMC_GET_CONFIG(lp)      SMC_inw(ioaddr, CONFIG_REG(lp))
 953
 954#define SMC_SET_CONFIG(lp, x)   SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
 955
 956#define SMC_GET_COUNTER(lp)     SMC_inw(ioaddr, COUNTER_REG(lp))
 957
 958#define SMC_GET_CTL(lp)         SMC_inw(ioaddr, CTL_REG(lp))
 959
 960#define SMC_SET_CTL(lp, x)      SMC_outw(lp, x, ioaddr, CTL_REG(lp))
 961
 962#define SMC_GET_MII(lp)         SMC_inw(ioaddr, MII_REG(lp))
 963
 964#define SMC_GET_GP(lp)          SMC_inw(ioaddr, GP_REG(lp))
 965
 966#define SMC_SET_GP(lp, x)                                               \
 967        do {                                                            \
 968                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 969                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
 970                else                                                    \
 971                        SMC_outw(lp, x, ioaddr, GP_REG(lp));            \
 972        } while (0)
 973
 974#define SMC_SET_MII(lp, x)      SMC_outw(lp, x, ioaddr, MII_REG(lp))
 975
 976#define SMC_GET_MIR(lp)         SMC_inw(ioaddr, MIR_REG(lp))
 977
 978#define SMC_SET_MIR(lp, x)      SMC_outw(lp, x, ioaddr, MIR_REG(lp))
 979
 980#define SMC_GET_MMU_CMD(lp)     SMC_inw(ioaddr, MMU_CMD_REG(lp))
 981
 982#define SMC_SET_MMU_CMD(lp, x)  SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
 983
 984#define SMC_GET_FIFO(lp)        SMC_inw(ioaddr, FIFO_REG(lp))
 985
 986#define SMC_GET_PTR(lp)         SMC_inw(ioaddr, PTR_REG(lp))
 987
 988#define SMC_SET_PTR(lp, x)                                              \
 989        do {                                                            \
 990                if (SMC_MUST_ALIGN_WRITE(lp))                           \
 991                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
 992                else                                                    \
 993                        SMC_outw(lp, x, ioaddr, PTR_REG(lp));           \
 994        } while (0)
 995
 996#define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
 997
 998#define SMC_GET_RCR(lp)         SMC_inw(ioaddr, RCR_REG(lp))
 999
1000#define SMC_SET_RCR(lp, x)              SMC_outw(lp, x, ioaddr, RCR_REG(lp))

1001
1002#define SMC_GET_REV(lp)         SMC_inw(ioaddr, REV_REG(lp))
1003
1004#define SMC_GET_RPC(lp)         SMC_inw(ioaddr, RPC_REG(lp))
1005
1006#define SMC_SET_RPC(lp, x)                                              \
1007        do {                                                            \
1008                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1009                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
1010                else                                                    \
1011                        SMC_outw(lp, x, ioaddr, RPC_REG(lp));           \
1012        } while (0)
1013
1014#define SMC_GET_TCR(lp)         SMC_inw(ioaddr, TCR_REG(lp))
1015
1016#define SMC_SET_TCR(lp, x)      SMC_outw(lp, x, ioaddr, TCR_REG(lp))
1017
1018#ifndef SMC_GET_MAC_ADDR
1019#define SMC_GET_MAC_ADDR(lp, addr)                                      \
1020        do {                                                            \
1021                unsigned int __v;                                       \
1022                __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
1023                addr[0] = __v; addr[1] = __v >> 8;                      \
1024                __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
1025                addr[2] = __v; addr[3] = __v >> 8;                      \
1026                __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
1027                addr[4] = __v; addr[5] = __v >> 8;                      \
1028        } while (0)
1029#endif
1030
1031#define SMC_SET_MAC_ADDR(lp, addr)                                      \
1032        do {                                                            \
1033                SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1034                SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1035                SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1036        } while (0)
1037
1038#define SMC_SET_MCAST(lp, x)                                            \
1039        do {                                                            \
1040                const unsigned char *mt = (x);                          \
1041                SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1042                SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1043                SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1044                SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1045        } while (0)
1046
1047#define SMC_PUT_PKT_HDR(lp, status, length)                             \
1048        do {                                                            \
1049                if (SMC_32BIT(lp))                                      \
1050                        SMC_outl((status) | (length)<<16, ioaddr,       \
1051                                 DATA_REG(lp));                 \
1052                else {                                                  \
1053                        SMC_outw(lp, status, ioaddr, DATA_REG(lp));     \
1054                        SMC_outw(lp, length, ioaddr, DATA_REG(lp));     \
1055                }                                                       \
1056        } while (0)
1057
1058#define SMC_GET_PKT_HDR(lp, status, length)                             \
1059        do {                                                            \
1060                if (SMC_32BIT(lp)) {                            \
1061                        unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1062                        (status) = __val & 0xffff;                      \
1063                        (length) = __val >> 16;                         \
1064                } else {                                                \
1065                        (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
1066                        (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
1067                }                                                       \
1068        } while (0)
1069
1070#define SMC_PUSH_DATA(lp, p, l)                                 \
1071        do {                                                            \
1072                if (SMC_32BIT(lp)) {                            \
1073                        void *__ptr = (p);                              \
1074                        int __len = (l);                                \
1075                        void __iomem *__ioaddr = ioaddr;                \
1076                        if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1077                                __len -= 2;                             \
1078                                SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1079                                __ptr += 2;                             \
1080                        }                                               \
1081                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1082                                __ioaddr = lp->datacs;                  \
1083                        SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1084                        if (__len & 2) {                                \
1085                                __ptr += (__len & ~3);                  \
1086                                SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1087                        }                                               \
1088                } else if (SMC_16BIT(lp))                               \
1089                        SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1090                else if (SMC_8BIT(lp))                          \
1091                        SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1092        } while (0)
1093
1094#define SMC_PULL_DATA(lp, p, l)                                 \
1095        do {                                                            \
1096                if (SMC_32BIT(lp)) {                            \
1097                        void *__ptr = (p);                              \
1098                        int __len = (l);                                \
1099                        void __iomem *__ioaddr = ioaddr;                \
1100                        if ((unsigned long)__ptr & 2) {                 \
1101                                /*                                      \
1102                                 * We want 32bit alignment here.        \
1103                                 * Since some buses perform a full      \
1104                                 * 32bit fetch even for 16bit data      \
1105                                 * we can't use SMC_inw() here.         \
1106                                 * Back both source (on-chip) and       \
1107                                 * destination pointers of 2 bytes.     \
1108                                 * This is possible since the call to   \
1109                                 * SMC_GET_PKT_HDR() already advanced   \
1110                                 * the source pointer of 4 bytes, and   \
1111                                 * the skb_reserve(skb, 2) advanced     \
1112                                 * the destination pointer of 2 bytes.  \
1113                                 */                                     \
1114                                __ptr -= 2;                             \
1115                                __len += 2;                             \
1116                                SMC_SET_PTR(lp,                 \
1117                                        2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1118                        }                                               \
1119                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1120                                __ioaddr = lp->datacs;                  \
1121                        __len += 2;                                     \
1122                        SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1123                } else if (SMC_16BIT(lp))                               \
1124                        SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1125                else if (SMC_8BIT(lp))                          \
1126                        SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
1127        } while (0)
1128
1129#endif  /* _SMC91X_H_ */
1130