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8#ifndef _CORE_H_
9#define _CORE_H_
10
11#include <linux/completion.h>
12#include <linux/if_ether.h>
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/uuid.h>
16#include <linux/time.h>
17
18#include "htt.h"
19#include "htc.h"
20#include "hw.h"
21#include "targaddrs.h"
22#include "wmi.h"
23#include "../ath.h"
24#include "../regd.h"
25#include "../dfs_pattern_detector.h"
26#include "spectral.h"
27#include "thermal.h"
28#include "wow.h"
29#include "swap.h"
30
31#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
32#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
33#define WO(_f) ((_f##_OFFSET) >> 2)
34
35#define ATH10K_SCAN_ID 0
36#define ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10
37#define WMI_READY_TIMEOUT (5 * HZ)
38#define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ)
39#define ATH10K_CONNECTION_LOSS_HZ (3 * HZ)
40#define ATH10K_NUM_CHANS 41
41#define ATH10K_MAX_5G_CHAN 173
42
43
44#define ATH10K_DEFAULT_NOISE_FLOOR -95
45
46#define ATH10K_INVALID_RSSI 128
47
48#define ATH10K_MAX_NUM_MGMT_PENDING 128
49
50
51#define ATH10K_KICKOUT_THRESHOLD (20 * 16)
52
53
54
55
56
57
58#define ATH10K_KEEPALIVE_MIN_IDLE 3747
59#define ATH10K_KEEPALIVE_MAX_IDLE 3895
60#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
61
62
63#define ATH10K_NAPI_BUDGET 64
64
65
66#define ATH10K_SMBIOS_BDF_EXT_TYPE 0xF8
67
68
69#define ATH10K_SMBIOS_BDF_EXT_LENGTH 0x9
70
71
72#define ATH10K_SMBIOS_BDF_EXT_OFFSET 0x8
73
74
75
76
77#define ATH10K_SMBIOS_BDF_EXT_STR_LENGTH 0x20
78
79
80#define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_"
81
82
83#define ATH10K_AIRTIME_WEIGHT_MULTIPLIER 4
84
85struct ath10k;
86
87static inline const char *ath10k_bus_str(enum ath10k_bus bus)
88{
89 switch (bus) {
90 case ATH10K_BUS_PCI:
91 return "pci";
92 case ATH10K_BUS_AHB:
93 return "ahb";
94 case ATH10K_BUS_SDIO:
95 return "sdio";
96 case ATH10K_BUS_USB:
97 return "usb";
98 case ATH10K_BUS_SNOC:
99 return "snoc";
100 }
101
102 return "unknown";
103}
104
105enum ath10k_skb_flags {
106 ATH10K_SKB_F_NO_HWCRYPT = BIT(0),
107 ATH10K_SKB_F_DTIM_ZERO = BIT(1),
108 ATH10K_SKB_F_DELIVER_CAB = BIT(2),
109 ATH10K_SKB_F_MGMT = BIT(3),
110 ATH10K_SKB_F_QOS = BIT(4),
111 ATH10K_SKB_F_RAW_TX = BIT(5),
112};
113
114struct ath10k_skb_cb {
115 dma_addr_t paddr;
116 u8 flags;
117 u8 eid;
118 u16 msdu_id;
119 u16 airtime_est;
120 struct ieee80211_vif *vif;
121 struct ieee80211_txq *txq;
122} __packed;
123
124struct ath10k_skb_rxcb {
125 dma_addr_t paddr;
126 struct hlist_node hlist;
127};
128
129static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
130{
131 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
132 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
133 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
134}
135
136static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
137{
138 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
139 return (struct ath10k_skb_rxcb *)skb->cb;
140}
141
142#define ATH10K_RXCB_SKB(rxcb) \
143 container_of((void *)rxcb, struct sk_buff, cb)
144
145static inline u32 host_interest_item_address(u32 item_offset)
146{
147 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
148}
149
150struct ath10k_bmi {
151 bool done_sent;
152};
153
154struct ath10k_mem_chunk {
155 void *vaddr;
156 dma_addr_t paddr;
157 u32 len;
158 u32 req_id;
159};
160
161struct ath10k_wmi {
162 enum ath10k_htc_ep_id eid;
163 struct completion service_ready;
164 struct completion unified_ready;
165 struct completion barrier;
166 struct completion radar_confirm;
167 wait_queue_head_t tx_credits_wq;
168 DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
169 struct wmi_cmd_map *cmd;
170 struct wmi_vdev_param_map *vdev_param;
171 struct wmi_pdev_param_map *pdev_param;
172 const struct wmi_ops *ops;
173 const struct wmi_peer_flags_map *peer_flags;
174
175 u32 mgmt_max_num_pending_tx;
176
177
178 struct idr mgmt_pending_tx;
179
180 u32 num_mem_chunks;
181 u32 rx_decap_mode;
182 struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
183};
184
185struct ath10k_fw_stats_peer {
186 struct list_head list;
187
188 u8 peer_macaddr[ETH_ALEN];
189 u32 peer_rssi;
190 u32 peer_tx_rate;
191 u32 peer_rx_rate;
192 u64 rx_duration;
193};
194
195struct ath10k_fw_extd_stats_peer {
196 struct list_head list;
197
198 u8 peer_macaddr[ETH_ALEN];
199 u32 rx_duration;
200};
201
202struct ath10k_fw_stats_vdev {
203 struct list_head list;
204
205 u32 vdev_id;
206 u32 beacon_snr;
207 u32 data_snr;
208 u32 num_tx_frames[4];
209 u32 num_rx_frames;
210 u32 num_tx_frames_retries[4];
211 u32 num_tx_frames_failures[4];
212 u32 num_rts_fail;
213 u32 num_rts_success;
214 u32 num_rx_err;
215 u32 num_rx_discard;
216 u32 num_tx_not_acked;
217 u32 tx_rate_history[10];
218 u32 beacon_rssi_history[10];
219};
220
221struct ath10k_fw_stats_vdev_extd {
222 struct list_head list;
223
224 u32 vdev_id;
225 u32 ppdu_aggr_cnt;
226 u32 ppdu_noack;
227 u32 mpdu_queued;
228 u32 ppdu_nonaggr_cnt;
229 u32 mpdu_sw_requeued;
230 u32 mpdu_suc_retry;
231 u32 mpdu_suc_multitry;
232 u32 mpdu_fail_retry;
233 u32 tx_ftm_suc;
234 u32 tx_ftm_suc_retry;
235 u32 tx_ftm_fail;
236 u32 rx_ftmr_cnt;
237 u32 rx_ftmr_dup_cnt;
238 u32 rx_iftmr_cnt;
239 u32 rx_iftmr_dup_cnt;
240};
241
242struct ath10k_fw_stats_pdev {
243 struct list_head list;
244
245
246 s32 ch_noise_floor;
247 u32 tx_frame_count;
248 u32 rx_frame_count;
249 u32 rx_clear_count;
250 u32 cycle_count;
251 u32 phy_err_count;
252 u32 chan_tx_power;
253 u32 ack_rx_bad;
254 u32 rts_bad;
255 u32 rts_good;
256 u32 fcs_bad;
257 u32 no_beacons;
258 u32 mib_int_count;
259
260
261 s32 comp_queued;
262 s32 comp_delivered;
263 s32 msdu_enqued;
264 s32 mpdu_enqued;
265 s32 wmm_drop;
266 s32 local_enqued;
267 s32 local_freed;
268 s32 hw_queued;
269 s32 hw_reaped;
270 s32 underrun;
271 u32 hw_paused;
272 s32 tx_abort;
273 s32 mpdus_requed;
274 u32 tx_ko;
275 u32 data_rc;
276 u32 self_triggers;
277 u32 sw_retry_failure;
278 u32 illgl_rate_phy_err;
279 u32 pdev_cont_xretry;
280 u32 pdev_tx_timeout;
281 u32 pdev_resets;
282 u32 phy_underrun;
283 u32 txop_ovf;
284 u32 seq_posted;
285 u32 seq_failed_queueing;
286 u32 seq_completed;
287 u32 seq_restarted;
288 u32 mu_seq_posted;
289 u32 mpdus_sw_flush;
290 u32 mpdus_hw_filter;
291 u32 mpdus_truncated;
292 u32 mpdus_ack_failed;
293 u32 mpdus_expired;
294
295
296 s32 mid_ppdu_route_change;
297 s32 status_rcvd;
298 s32 r0_frags;
299 s32 r1_frags;
300 s32 r2_frags;
301 s32 r3_frags;
302 s32 htt_msdus;
303 s32 htt_mpdus;
304 s32 loc_msdus;
305 s32 loc_mpdus;
306 s32 oversize_amsdu;
307 s32 phy_errs;
308 s32 phy_err_drop;
309 s32 mpdu_errs;
310 s32 rx_ovfl_errs;
311};
312
313struct ath10k_fw_stats {
314 bool extended;
315 struct list_head pdevs;
316 struct list_head vdevs;
317 struct list_head peers;
318 struct list_head peers_extd;
319};
320
321#define ATH10K_TPC_TABLE_TYPE_FLAG 1
322#define ATH10K_TPC_PREAM_TABLE_END 0xFFFF
323
324struct ath10k_tpc_table {
325 u32 pream_idx[WMI_TPC_RATE_MAX];
326 u8 rate_code[WMI_TPC_RATE_MAX];
327 char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
328};
329
330struct ath10k_tpc_stats {
331 u32 reg_domain;
332 u32 chan_freq;
333 u32 phy_mode;
334 u32 twice_antenna_reduction;
335 u32 twice_max_rd_power;
336 s32 twice_antenna_gain;
337 u32 power_limit;
338 u32 num_tx_chain;
339 u32 ctl;
340 u32 rate_max;
341 u8 flag[WMI_TPC_FLAG];
342 struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
343};
344
345struct ath10k_tpc_table_final {
346 u32 pream_idx[WMI_TPC_FINAL_RATE_MAX];
347 u8 rate_code[WMI_TPC_FINAL_RATE_MAX];
348 char tpc_value[WMI_TPC_FINAL_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
349};
350
351struct ath10k_tpc_stats_final {
352 u32 reg_domain;
353 u32 chan_freq;
354 u32 phy_mode;
355 u32 twice_antenna_reduction;
356 u32 twice_max_rd_power;
357 s32 twice_antenna_gain;
358 u32 power_limit;
359 u32 num_tx_chain;
360 u32 ctl;
361 u32 rate_max;
362 u8 flag[WMI_TPC_FLAG];
363 struct ath10k_tpc_table_final tpc_table_final[WMI_TPC_FLAG];
364};
365
366struct ath10k_dfs_stats {
367 u32 phy_errors;
368 u32 pulses_total;
369 u32 pulses_detected;
370 u32 pulses_discarded;
371 u32 radar_detected;
372};
373
374enum ath10k_radar_confirmation_state {
375 ATH10K_RADAR_CONFIRMATION_IDLE = 0,
376 ATH10K_RADAR_CONFIRMATION_INPROGRESS,
377 ATH10K_RADAR_CONFIRMATION_STOPPED,
378};
379
380struct ath10k_radar_found_info {
381 u32 pri_min;
382 u32 pri_max;
383 u32 width_min;
384 u32 width_max;
385 u32 sidx_min;
386 u32 sidx_max;
387};
388
389#define ATH10K_MAX_NUM_PEER_IDS (1 << 11)
390
391struct ath10k_peer {
392 struct list_head list;
393 struct ieee80211_vif *vif;
394 struct ieee80211_sta *sta;
395
396 bool removed;
397 int vdev_id;
398 u8 addr[ETH_ALEN];
399 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
400
401
402 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
403};
404
405struct ath10k_txq {
406 struct list_head list;
407 unsigned long num_fw_queued;
408 unsigned long num_push_allowed;
409};
410
411enum ath10k_pkt_rx_err {
412 ATH10K_PKT_RX_ERR_FCS,
413 ATH10K_PKT_RX_ERR_TKIP,
414 ATH10K_PKT_RX_ERR_CRYPT,
415 ATH10K_PKT_RX_ERR_PEER_IDX_INVAL,
416 ATH10K_PKT_RX_ERR_MAX,
417};
418
419enum ath10k_ampdu_subfrm_num {
420 ATH10K_AMPDU_SUBFRM_NUM_10,
421 ATH10K_AMPDU_SUBFRM_NUM_20,
422 ATH10K_AMPDU_SUBFRM_NUM_30,
423 ATH10K_AMPDU_SUBFRM_NUM_40,
424 ATH10K_AMPDU_SUBFRM_NUM_50,
425 ATH10K_AMPDU_SUBFRM_NUM_60,
426 ATH10K_AMPDU_SUBFRM_NUM_MORE,
427 ATH10K_AMPDU_SUBFRM_NUM_MAX,
428};
429
430enum ath10k_amsdu_subfrm_num {
431 ATH10K_AMSDU_SUBFRM_NUM_1,
432 ATH10K_AMSDU_SUBFRM_NUM_2,
433 ATH10K_AMSDU_SUBFRM_NUM_3,
434 ATH10K_AMSDU_SUBFRM_NUM_4,
435 ATH10K_AMSDU_SUBFRM_NUM_MORE,
436 ATH10K_AMSDU_SUBFRM_NUM_MAX,
437};
438
439struct ath10k_sta_tid_stats {
440 unsigned long rx_pkt_from_fw;
441 unsigned long rx_pkt_unchained;
442 unsigned long rx_pkt_drop_chained;
443 unsigned long rx_pkt_drop_filter;
444 unsigned long rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
445 unsigned long rx_pkt_queued_for_mac;
446 unsigned long rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
447 unsigned long rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
448};
449
450enum ath10k_counter_type {
451 ATH10K_COUNTER_TYPE_BYTES,
452 ATH10K_COUNTER_TYPE_PKTS,
453 ATH10K_COUNTER_TYPE_MAX,
454};
455
456enum ath10k_stats_type {
457 ATH10K_STATS_TYPE_SUCC,
458 ATH10K_STATS_TYPE_FAIL,
459 ATH10K_STATS_TYPE_RETRY,
460 ATH10K_STATS_TYPE_AMPDU,
461 ATH10K_STATS_TYPE_MAX,
462};
463
464struct ath10k_htt_data_stats {
465 u64 legacy[ATH10K_COUNTER_TYPE_MAX][ATH10K_LEGACY_NUM];
466 u64 ht[ATH10K_COUNTER_TYPE_MAX][ATH10K_HT_MCS_NUM];
467 u64 vht[ATH10K_COUNTER_TYPE_MAX][ATH10K_VHT_MCS_NUM];
468 u64 bw[ATH10K_COUNTER_TYPE_MAX][ATH10K_BW_NUM];
469 u64 nss[ATH10K_COUNTER_TYPE_MAX][ATH10K_NSS_NUM];
470 u64 gi[ATH10K_COUNTER_TYPE_MAX][ATH10K_GI_NUM];
471 u64 rate_table[ATH10K_COUNTER_TYPE_MAX][ATH10K_RATE_TABLE_NUM];
472};
473
474struct ath10k_htt_tx_stats {
475 struct ath10k_htt_data_stats stats[ATH10K_STATS_TYPE_MAX];
476 u64 tx_duration;
477 u64 ba_fails;
478 u64 ack_fails;
479};
480
481struct ath10k_sta {
482 struct ath10k_vif *arvif;
483
484
485 u32 changed;
486 u32 bw;
487 u32 nss;
488 u32 smps;
489 u16 peer_id;
490 struct rate_info txrate;
491 struct ieee80211_tx_info tx_info;
492 u32 last_tx_bitrate;
493
494 struct work_struct update_wk;
495 u64 rx_duration;
496 struct ath10k_htt_tx_stats *tx_stats;
497
498#ifdef CONFIG_MAC80211_DEBUGFS
499
500 bool aggr_mode;
501
502
503 struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1];
504#endif
505
506 u32 peer_ps_state;
507};
508
509#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
510
511enum ath10k_beacon_state {
512 ATH10K_BEACON_SCHEDULED = 0,
513 ATH10K_BEACON_SENDING,
514 ATH10K_BEACON_SENT,
515};
516
517struct ath10k_vif {
518 struct list_head list;
519
520 u32 vdev_id;
521 u16 peer_id;
522 enum wmi_vdev_type vdev_type;
523 enum wmi_vdev_subtype vdev_subtype;
524 u32 beacon_interval;
525 u32 dtim_period;
526 struct sk_buff *beacon;
527
528 enum ath10k_beacon_state beacon_state;
529 void *beacon_buf;
530 dma_addr_t beacon_paddr;
531 unsigned long tx_paused;
532
533 struct ath10k *ar;
534 struct ieee80211_vif *vif;
535
536 bool is_started;
537 bool is_up;
538 bool spectral_enabled;
539 bool ps;
540 u32 aid;
541 u8 bssid[ETH_ALEN];
542
543 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
544 s8 def_wep_key_idx;
545
546 u16 tx_seq_no;
547
548 union {
549 struct {
550 u32 uapsd;
551 } sta;
552 struct {
553
554 u8 tim_bitmap[64];
555 u8 tim_len;
556 u32 ssid_len;
557 u8 ssid[IEEE80211_MAX_SSID_LEN];
558 bool hidden_ssid;
559
560 u32 noa_len;
561 u8 *noa_data;
562 } ap;
563 } u;
564
565 bool use_cts_prot;
566 bool nohwcrypt;
567 int num_legacy_stations;
568 int txpower;
569 bool ftm_responder;
570 struct wmi_wmm_params_all_arg wmm_params;
571 struct work_struct ap_csa_work;
572 struct delayed_work connection_loss_work;
573 struct cfg80211_bitrate_mask bitrate_mask;
574};
575
576struct ath10k_vif_iter {
577 u32 vdev_id;
578 struct ath10k_vif *arvif;
579};
580
581
582struct ath10k_ce_crash_data {
583 __le32 base_addr;
584 __le32 src_wr_idx;
585 __le32 src_r_idx;
586 __le32 dst_wr_idx;
587 __le32 dst_r_idx;
588};
589
590struct ath10k_ce_crash_hdr {
591 __le32 ce_count;
592 __le32 reserved[3];
593 struct ath10k_ce_crash_data entries[];
594};
595
596#define MAX_MEM_DUMP_TYPE 5
597
598
599struct ath10k_fw_crash_data {
600 guid_t guid;
601 struct timespec64 timestamp;
602 __le32 registers[REG_DUMP_COUNT_QCA988X];
603 struct ath10k_ce_crash_data ce_crash_data[CE_COUNT_MAX];
604
605 u8 *ramdump_buf;
606 size_t ramdump_buf_len;
607};
608
609struct ath10k_debug {
610 struct dentry *debugfs_phy;
611
612 struct ath10k_fw_stats fw_stats;
613 struct completion fw_stats_complete;
614 bool fw_stats_done;
615
616 unsigned long htt_stats_mask;
617 struct delayed_work htt_stats_dwork;
618 struct ath10k_dfs_stats dfs_stats;
619 struct ath_dfs_pool_stats dfs_pool_stats;
620
621
622 struct ath10k_tpc_stats *tpc_stats;
623 struct ath10k_tpc_stats_final *tpc_stats_final;
624
625 struct completion tpc_complete;
626
627
628 u64 fw_dbglog_mask;
629 u32 fw_dbglog_level;
630 u32 reg_addr;
631 u32 nf_cal_period;
632 void *cal_data;
633 u32 enable_extd_tx_stats;
634};
635
636enum ath10k_state {
637 ATH10K_STATE_OFF = 0,
638 ATH10K_STATE_ON,
639
640
641
642
643
644
645
646
647
648
649 ATH10K_STATE_RESTARTING,
650 ATH10K_STATE_RESTARTED,
651
652
653
654
655
656
657 ATH10K_STATE_WEDGED,
658
659
660 ATH10K_STATE_UTF,
661};
662
663enum ath10k_firmware_mode {
664
665 ATH10K_FIRMWARE_MODE_NORMAL,
666
667
668 ATH10K_FIRMWARE_MODE_UTF,
669};
670
671enum ath10k_fw_features {
672
673 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
674
675
676 ATH10K_FW_FEATURE_WMI_10X = 1,
677
678
679 ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
680
681
682 ATH10K_FW_FEATURE_NO_P2P = 3,
683
684
685
686
687
688 ATH10K_FW_FEATURE_WMI_10_2 = 4,
689
690
691
692
693
694 ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
695
696
697
698
699
700 ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
701
702
703 ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
704
705
706
707
708 ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
709
710
711 ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
712
713
714
715
716 ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
717
718
719 ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
720
721
722 ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
723
724
725
726
727
728
729
730
731 ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13,
732
733
734
735
736
737
738 ATH10K_FW_FEATURE_BTCOEX_PARAM = 14,
739
740
741
742
743 ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15,
744
745
746
747
748
749
750 ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST = 16,
751
752
753 ATH10K_FW_FEATURE_NO_PS = 17,
754
755
756 ATH10K_FW_FEATURE_MGMT_TX_BY_REF = 18,
757
758
759 ATH10K_FW_FEATURE_NON_BMI = 19,
760
761
762 ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL = 20,
763
764
765 ATH10K_FW_FEATURE_COUNT,
766};
767
768enum ath10k_dev_flags {
769
770 ATH10K_CAC_RUNNING,
771 ATH10K_FLAG_CORE_REGISTERED,
772
773
774
775
776 ATH10K_FLAG_CRASH_FLUSH,
777
778
779
780
781
782 ATH10K_FLAG_RAW_MODE,
783
784
785 ATH10K_FLAG_HW_CRYPTO_DISABLED,
786
787
788 ATH10K_FLAG_BTCOEX,
789
790
791 ATH10K_FLAG_PEER_STATS,
792};
793
794enum ath10k_cal_mode {
795 ATH10K_CAL_MODE_FILE,
796 ATH10K_CAL_MODE_OTP,
797 ATH10K_CAL_MODE_DT,
798 ATH10K_PRE_CAL_MODE_FILE,
799 ATH10K_PRE_CAL_MODE_DT,
800 ATH10K_CAL_MODE_EEPROM,
801};
802
803enum ath10k_crypt_mode {
804
805 ATH10K_CRYPT_MODE_HW,
806
807 ATH10K_CRYPT_MODE_SW,
808};
809
810static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
811{
812 switch (mode) {
813 case ATH10K_CAL_MODE_FILE:
814 return "file";
815 case ATH10K_CAL_MODE_OTP:
816 return "otp";
817 case ATH10K_CAL_MODE_DT:
818 return "dt";
819 case ATH10K_PRE_CAL_MODE_FILE:
820 return "pre-cal-file";
821 case ATH10K_PRE_CAL_MODE_DT:
822 return "pre-cal-dt";
823 case ATH10K_CAL_MODE_EEPROM:
824 return "eeprom";
825 }
826
827 return "unknown";
828}
829
830enum ath10k_scan_state {
831 ATH10K_SCAN_IDLE,
832 ATH10K_SCAN_STARTING,
833 ATH10K_SCAN_RUNNING,
834 ATH10K_SCAN_ABORTING,
835};
836
837static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
838{
839 switch (state) {
840 case ATH10K_SCAN_IDLE:
841 return "idle";
842 case ATH10K_SCAN_STARTING:
843 return "starting";
844 case ATH10K_SCAN_RUNNING:
845 return "running";
846 case ATH10K_SCAN_ABORTING:
847 return "aborting";
848 }
849
850 return "unknown";
851}
852
853enum ath10k_tx_pause_reason {
854 ATH10K_TX_PAUSE_Q_FULL,
855 ATH10K_TX_PAUSE_MAX,
856};
857
858struct ath10k_fw_file {
859 const struct firmware *firmware;
860
861 char fw_version[ETHTOOL_FWVERS_LEN];
862
863 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
864
865 enum ath10k_fw_wmi_op_version wmi_op_version;
866 enum ath10k_fw_htt_op_version htt_op_version;
867
868 const void *firmware_data;
869 size_t firmware_len;
870
871 const void *otp_data;
872 size_t otp_len;
873
874 const void *codeswap_data;
875 size_t codeswap_len;
876
877
878
879
880
881
882
883
884 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
885};
886
887struct ath10k_fw_components {
888 const struct firmware *board;
889 const void *board_data;
890 size_t board_len;
891 const struct firmware *ext_board;
892 const void *ext_board_data;
893 size_t ext_board_len;
894
895 struct ath10k_fw_file fw_file;
896};
897
898struct ath10k_per_peer_tx_stats {
899 u32 succ_bytes;
900 u32 retry_bytes;
901 u32 failed_bytes;
902 u8 ratecode;
903 u8 flags;
904 u16 peer_id;
905 u16 succ_pkts;
906 u16 retry_pkts;
907 u16 failed_pkts;
908 u16 duration;
909 u32 reserved1;
910 u32 reserved2;
911};
912
913enum ath10k_dev_type {
914 ATH10K_DEV_TYPE_LL,
915 ATH10K_DEV_TYPE_HL,
916};
917
918struct ath10k_bus_params {
919 u32 chip_id;
920 enum ath10k_dev_type dev_type;
921 bool link_can_suspend;
922};
923
924struct ath10k {
925 struct ath_common ath_common;
926 struct ieee80211_hw *hw;
927 struct ieee80211_ops *ops;
928 struct device *dev;
929 u8 mac_addr[ETH_ALEN];
930
931 enum ath10k_hw_rev hw_rev;
932 u16 dev_id;
933 u32 chip_id;
934 enum ath10k_dev_type dev_type;
935 u32 target_version;
936 u8 fw_version_major;
937 u32 fw_version_minor;
938 u16 fw_version_release;
939 u16 fw_version_build;
940 u32 fw_stats_req_mask;
941 u32 phy_capability;
942 u32 hw_min_tx_power;
943 u32 hw_max_tx_power;
944 u32 hw_eeprom_rd;
945 u32 ht_cap_info;
946 u32 vht_cap_info;
947 u32 num_rf_chains;
948 u32 max_spatial_stream;
949
950 u32 low_5ghz_chan;
951 u32 high_5ghz_chan;
952 bool ani_enabled;
953
954 u8 ps_state_enable;
955
956 bool nlo_enabled;
957 bool p2p;
958
959 struct {
960 enum ath10k_bus bus;
961 const struct ath10k_hif_ops *ops;
962 } hif;
963
964 struct completion target_suspend;
965 struct completion driver_recovery;
966
967 const struct ath10k_hw_regs *regs;
968 const struct ath10k_hw_ce_regs *hw_ce_regs;
969 const struct ath10k_hw_values *hw_values;
970 struct ath10k_bmi bmi;
971 struct ath10k_wmi wmi;
972 struct ath10k_htc htc;
973 struct ath10k_htt htt;
974
975 struct ath10k_hw_params hw_params;
976
977
978 struct ath10k_fw_components normal_mode_fw;
979
980
981
982
983 const struct ath10k_fw_components *running_fw;
984
985 const struct firmware *pre_cal_file;
986 const struct firmware *cal_file;
987
988 struct {
989 u32 vendor;
990 u32 device;
991 u32 subsystem_vendor;
992 u32 subsystem_device;
993
994 bool bmi_ids_valid;
995 bool qmi_ids_valid;
996 u32 qmi_board_id;
997 u8 bmi_board_id;
998 u8 bmi_eboard_id;
999 u8 bmi_chip_id;
1000 bool ext_bid_supported;
1001
1002 char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH];
1003 } id;
1004
1005 int fw_api;
1006 int bd_api;
1007 enum ath10k_cal_mode cal_mode;
1008
1009 struct {
1010 struct completion started;
1011 struct completion completed;
1012 struct completion on_channel;
1013 struct delayed_work timeout;
1014 enum ath10k_scan_state state;
1015 bool is_roc;
1016 int vdev_id;
1017 int roc_freq;
1018 bool roc_notify;
1019 } scan;
1020
1021 struct {
1022 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
1023 } mac;
1024
1025
1026 struct ieee80211_channel *rx_channel;
1027
1028
1029 struct ieee80211_channel *scan_channel;
1030
1031
1032 struct cfg80211_chan_def chandef;
1033
1034
1035 struct ieee80211_channel *tgt_oper_chan;
1036
1037 unsigned long long free_vdev_map;
1038 struct ath10k_vif *monitor_arvif;
1039 bool monitor;
1040 int monitor_vdev_id;
1041 bool monitor_started;
1042 unsigned int filter_flags;
1043 unsigned long dev_flags;
1044 bool dfs_block_radar_events;
1045
1046
1047 bool radar_enabled;
1048 int num_started_vdevs;
1049
1050
1051 u8 cfg_tx_chainmask;
1052 u8 cfg_rx_chainmask;
1053
1054 struct completion install_key_done;
1055
1056 int last_wmi_vdev_start_status;
1057 struct completion vdev_setup_done;
1058
1059 struct workqueue_struct *workqueue;
1060
1061 struct workqueue_struct *workqueue_aux;
1062
1063
1064 struct mutex conf_mutex;
1065
1066
1067 struct mutex dump_mutex;
1068
1069
1070 spinlock_t data_lock;
1071
1072 struct list_head arvifs;
1073 struct list_head peers;
1074 struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
1075 wait_queue_head_t peer_mapping_wq;
1076
1077
1078 int num_peers;
1079 int num_stations;
1080
1081 int max_num_peers;
1082 int max_num_stations;
1083 int max_num_vdevs;
1084 int max_num_tdls_vdevs;
1085 int num_active_peers;
1086 int num_tids;
1087
1088 struct work_struct svc_rdy_work;
1089 struct sk_buff *svc_rdy_skb;
1090
1091 struct work_struct offchan_tx_work;
1092 struct sk_buff_head offchan_tx_queue;
1093 struct completion offchan_tx_completed;
1094 struct sk_buff *offchan_tx_skb;
1095
1096 struct work_struct wmi_mgmt_tx_work;
1097 struct sk_buff_head wmi_mgmt_tx_queue;
1098
1099 enum ath10k_state state;
1100
1101 struct work_struct register_work;
1102 struct work_struct restart_work;
1103
1104
1105
1106
1107 u32 survey_last_rx_clear_count;
1108 u32 survey_last_cycle_count;
1109 struct survey_info survey[ATH10K_NUM_CHANS];
1110
1111
1112
1113
1114
1115
1116
1117 bool ch_info_can_report_survey;
1118 struct completion bss_survey_done;
1119
1120 struct dfs_pattern_detector *dfs_detector;
1121
1122 unsigned long tx_paused;
1123
1124#ifdef CONFIG_ATH10K_DEBUGFS
1125 struct ath10k_debug debug;
1126 struct {
1127
1128 struct rchan *rfs_chan_spec_scan;
1129
1130
1131 enum ath10k_spectral_mode mode;
1132 struct ath10k_spec_scan config;
1133 } spectral;
1134#endif
1135
1136 u32 pktlog_filter;
1137
1138#ifdef CONFIG_DEV_COREDUMP
1139 struct {
1140 struct ath10k_fw_crash_data *fw_crash_data;
1141 } coredump;
1142#endif
1143
1144 struct {
1145
1146 struct ath10k_fw_components utf_mode_fw;
1147
1148
1149 bool utf_monitor;
1150 } testmode;
1151
1152 struct {
1153
1154 u32 fw_crash_counter;
1155 u32 fw_warm_reset_counter;
1156 u32 fw_cold_reset_counter;
1157 } stats;
1158
1159 struct ath10k_thermal thermal;
1160 struct ath10k_wow wow;
1161 struct ath10k_per_peer_tx_stats peer_tx_stats;
1162
1163
1164 struct net_device napi_dev;
1165 struct napi_struct napi;
1166
1167 struct work_struct set_coverage_class_work;
1168
1169 struct {
1170
1171 s16 coverage_class;
1172
1173 u32 reg_phyclk;
1174 u32 reg_slottime_conf;
1175 u32 reg_slottime_orig;
1176 u32 reg_ack_cts_timeout_conf;
1177 u32 reg_ack_cts_timeout_orig;
1178 } fw_coverage;
1179
1180 u32 ampdu_reference;
1181
1182 const u8 *wmi_key_cipher;
1183 void *ce_priv;
1184
1185 u32 sta_tid_stats_mask;
1186
1187
1188 enum ath10k_radar_confirmation_state radar_conf_state;
1189 struct ath10k_radar_found_info last_radar_info;
1190 struct work_struct radar_confirmation_work;
1191 struct ath10k_bus_params bus_param;
1192
1193
1194 u8 drv_priv[0] __aligned(sizeof(void *));
1195};
1196
1197static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
1198{
1199 if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) &&
1200 test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map))
1201 return true;
1202
1203 return false;
1204}
1205
1206extern unsigned long ath10k_coredump_mask;
1207
1208struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
1209 enum ath10k_bus bus,
1210 enum ath10k_hw_rev hw_rev,
1211 const struct ath10k_hif_ops *hif_ops);
1212void ath10k_core_destroy(struct ath10k *ar);
1213void ath10k_core_get_fw_features_str(struct ath10k *ar,
1214 char *buf,
1215 size_t max_len);
1216int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1217 struct ath10k_fw_file *fw_file);
1218
1219int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
1220 const struct ath10k_fw_components *fw_components);
1221int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
1222void ath10k_core_stop(struct ath10k *ar);
1223int ath10k_core_register(struct ath10k *ar,
1224 const struct ath10k_bus_params *bus_params);
1225void ath10k_core_unregister(struct ath10k *ar);
1226int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type);
1227void ath10k_core_free_board_files(struct ath10k *ar);
1228
1229#endif
1230