1
2
3
4#ifndef __RTL92C_DEF_H__
5#define __RTL92C_DEF_H__
6
7#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
8#define HAL_PRIME_CHNL_OFFSET_LOWER 1
9#define HAL_PRIME_CHNL_OFFSET_UPPER 2
10
11#define RX_MPDU_QUEUE 0
12#define RX_CMD_QUEUE 1
13
14#define C2H_RX_CMD_HDR_LEN 8
15#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
16 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
17#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
18 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
19#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
20 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
21#define GET_C2H_CMD_CONTINUE(__prxhdr) \
22 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
23#define GET_C2H_CMD_CONTENT(__prxhdr) \
24 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
25
26#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
27 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
28#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
29 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
30#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
31 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
32#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
33 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
34#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
35 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
36#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
37 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
38#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
39 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
40#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
41 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
42#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
43 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
44
45#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
46
47
48
49
50
51
52
53#define CHIP_8723 BIT(0)
54#define CHIP_92D BIT(1)
55#define NORMAL_CHIP BIT(3)
56#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
57#define RF_TYPE_1T2R BIT(4)
58#define RF_TYPE_2T2R BIT(5)
59#define CHIP_VENDOR_UMC BIT(7)
60#define B_CUT_VERSION BIT(12)
61#define C_CUT_VERSION BIT(13)
62#define D_CUT_VERSION ((BIT(12)|BIT(13)))
63#define E_CUT_VERSION BIT(14)
64
65
66#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
67#define CHIP_TYPE_MASK BIT(3)
68#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
69#define MANUFACTUER_MASK BIT(7)
70#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
71#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
72
73
74#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
75#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
76#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
77#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
78#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
79#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
80
81#define IS_81XXC(version) \
82 ((GET_CVID_IC_TYPE(version) == 0) ? true : false)
83#define IS_8723_SERIES(version) \
84 ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
85#define IS_92D(version) \
86 ((GET_CVID_IC_TYPE(version) == CHIP_92D) ? true : false)
87
88#define IS_NORMAL_CHIP(version) \
89 ((GET_CVID_CHIP_TYPE(version)) ? true : false)
90#define IS_NORMAL_CHIP92D(version) \
91 ((GET_CVID_CHIP_TYPE(version)) ? true : false)
92
93#define IS_1T1R(version) \
94 ((GET_CVID_RF_TYPE(version)) ? false : true)
95#define IS_1T2R(version) \
96 ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
97#define IS_2T2R(version) \
98 ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
99#define IS_CHIP_VENDOR_UMC(version) \
100 ((GET_CVID_MANUFACTUER(version)) ? true : false)
101
102#define IS_92C_SERIAL(version) \
103 ((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
104#define IS_81XXC_VENDOR_UMC_B_CUT(version) \
105 (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
106 ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true \
107 : false) : false) : false)
108
109enum version_8188e {
110 VERSION_TEST_CHIP_88E = 0x00,
111 VERSION_NORMAL_CHIP_88E = 0x01,
112 VERSION_UNKNOWN = 0xFF,
113};
114
115enum rtl819x_loopback_e {
116 RTL819X_NO_LOOPBACK = 0,
117 RTL819X_MAC_LOOPBACK = 1,
118 RTL819X_DMA_LOOPBACK = 2,
119 RTL819X_CCK_LOOPBACK = 3,
120};
121
122enum rf_optype {
123 RF_OP_BY_SW_3WIRE = 0,
124 RF_OP_BY_FW,
125 RF_OP_MAX
126};
127
128enum rf_power_state {
129 RF_ON,
130 RF_OFF,
131 RF_SLEEP,
132 RF_SHUT_DOWN,
133};
134
135enum power_save_mode {
136 POWER_SAVE_MODE_ACTIVE,
137 POWER_SAVE_MODE_SAVE,
138};
139
140enum power_polocy_config {
141 POWERCFG_MAX_POWER_SAVINGS,
142 POWERCFG_GLOBAL_POWER_SAVINGS,
143 POWERCFG_LOCAL_POWER_SAVINGS,
144 POWERCFG_LENOVO,
145};
146
147enum interface_select_pci {
148 INTF_SEL1_MINICARD = 0,
149 INTF_SEL0_PCIE = 1,
150 INTF_SEL2_RSV = 2,
151 INTF_SEL3_RSV = 3,
152};
153
154enum rtl_desc_qsel {
155 QSLT_BK = 0x2,
156 QSLT_BE = 0x0,
157 QSLT_VI = 0x5,
158 QSLT_VO = 0x7,
159 QSLT_BEACON = 0x10,
160 QSLT_HIGH = 0x11,
161 QSLT_MGNT = 0x12,
162 QSLT_CMD = 0x13,
163};
164
165enum rtl_desc92c_rate {
166 DESC92C_RATE1M = 0x00,
167 DESC92C_RATE2M = 0x01,
168 DESC92C_RATE5_5M = 0x02,
169 DESC92C_RATE11M = 0x03,
170
171 DESC92C_RATE6M = 0x04,
172 DESC92C_RATE9M = 0x05,
173 DESC92C_RATE12M = 0x06,
174 DESC92C_RATE18M = 0x07,
175 DESC92C_RATE24M = 0x08,
176 DESC92C_RATE36M = 0x09,
177 DESC92C_RATE48M = 0x0a,
178 DESC92C_RATE54M = 0x0b,
179
180 DESC92C_RATEMCS0 = 0x0c,
181 DESC92C_RATEMCS1 = 0x0d,
182 DESC92C_RATEMCS2 = 0x0e,
183 DESC92C_RATEMCS3 = 0x0f,
184 DESC92C_RATEMCS4 = 0x10,
185 DESC92C_RATEMCS5 = 0x11,
186 DESC92C_RATEMCS6 = 0x12,
187 DESC92C_RATEMCS7 = 0x13,
188 DESC92C_RATEMCS8 = 0x14,
189 DESC92C_RATEMCS9 = 0x15,
190 DESC92C_RATEMCS10 = 0x16,
191 DESC92C_RATEMCS11 = 0x17,
192 DESC92C_RATEMCS12 = 0x18,
193 DESC92C_RATEMCS13 = 0x19,
194 DESC92C_RATEMCS14 = 0x1a,
195 DESC92C_RATEMCS15 = 0x1b,
196 DESC92C_RATEMCS15_SG = 0x1c,
197 DESC92C_RATEMCS32 = 0x20,
198};
199
200struct phy_sts_cck_8192s_t {
201 u8 adc_pwdb_X[4];
202 u8 sq_rpt;
203 u8 cck_agc_rpt;
204};
205
206struct h2c_cmd_8192c {
207 u8 element_id;
208 u32 cmd_len;
209 u8 *p_cmdbuffer;
210};
211
212#endif
213
