LXR linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2009-2010  Realtek Corporation.*/
   3
   4#ifndef __RTL8821AE_PWRSEQ_H__
   5#define __RTL8821AE_PWRSEQ_H__
   6
   7#include "../pwrseqcmd.h"
   8#include "../btcoexist/halbt_precomp.h"
   9
  10#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS      15
  11#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS      15
  12#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS      15
  13#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS      15
  14#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS      25
  15#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS      15
  16#define RTL8812_TRANS_ACT_TO_LPS_STEPS          15
  17#define RTL8812_TRANS_LPS_TO_ACT_STEPS          15
  18#define RTL8812_TRANS_END_STEPS                 1
  19
  20/* The following macros have the following format:
  21 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
  22 *   comments },
  23 */
  24#define RTL8812_TRANS_CARDEMU_TO_ACT                                    \
  25        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  26        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
  27        /* disable SW LPS 0x04[10]=0*/},        \
  28        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  29        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
  30        /* wait till 0x04[17] = 1    power ready*/},    \
  31        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  32        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
  33        /* disable HWPDN 0x04[15]=0*/}, \
  34        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  35        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
  36        /* disable WL suspend*/},       \
  37        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  38        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
  39        /* polling until return 0*/},   \
  40        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  41        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
  42
  43#define RTL8812_TRANS_ACT_TO_CARDEMU                                                                                                    \
  44        {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  45        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
  46         /* 0xc00[7:0] = 4      turn off 3-wire */},    \
  47        {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  48        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
  49         /* 0xe00[7:0] = 4      turn off 3-wire */},    \
  50        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  51        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
  52         /* 0x2[0] = 0   RESET BB, CLOSE RF */},        \
  53        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  54        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
  55        /*Delay 1us*/}, \
  56        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
  57        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
  58          /* Whole BB is reset*/},                      \
  59        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  60        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
  61         /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/},  \
  62        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
  63        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
  64        /*0x8[1] = 0 ANA clk =500k */}, \
  65        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  66        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
  67         /*0x04[9] = 1 turn off MAC by HW state machine*/},     \
  68        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  69        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
  70         /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
  71
  72#define RTL8812_TRANS_CARDEMU_TO_SUS                                    \
  73        {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
  74        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \
  75        {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
  76        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \
  77        {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  78        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
  79        /* gpio11 input mode, gpio10~8 output mode */}, \
  80        {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  81        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
  82        /* gpio 0~7 output same value as input ?? */},  \
  83        {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  84        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
  85        /* gpio0~7 output mode */},     \
  86        {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  87        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
  88        /* 0x47[7:0] = 00 gpio mode */},        \
  89        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
  90        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
  91        /* suspend option all off */},  \
  92        {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  93        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
  94        /*0x14[7] = 1 turn on ZCD */},  \
  95        {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  96        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
  97        /* 0x15[0] =1 trun on ZCD */},  \
  98        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
  99        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
 100        /*0x23[4] = 1 hpon LDO sleep mode */},  \
 101        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 102        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
 103        /*0x8[1] = 0 ANA clk =500k */}, \
 104        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 105        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
 106        /*0x04[11] = 2b'11 enable WL suspend for PCIe*/},
 107
 108#define RTL8812_TRANS_SUS_TO_CARDEMU                                    \
 109        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 110        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
 111        /*0x04[11] = 2b'01enable WL suspend*/},   \
 112        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 113        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
 114        /*0x23[4] = 0 hpon LDO sleep mode leave */},    \
 115        {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 116        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
 117        /* 0x15[0] =0 trun off ZCD */}, \
 118        {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 119        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
 120        /*0x14[7] = 0 turn off ZCD */}, \
 121        {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 122        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 123        /* gpio0~7 input mode */},      \
 124        {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 125        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 126        /* gpio11 input mode, gpio10~8 input mode */},
 127
 128#define RTL8812_TRANS_CARDEMU_TO_CARDDIS                                \
 129        {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 130        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
 131        /*0x03[2] = 0, reset 8051*/},   \
 132        {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 133        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
 134        /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/}, \
 135        {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 136        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
 137        {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 138        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
 139        {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 140        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
 141        /* gpio11 input mode, gpio10~8 output mode */}, \
 142        {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 143        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 144        /* gpio 0~7 output same value as input ?? */},  \
 145        {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 146        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
 147        /* gpio0~7 output mode */},     \
 148        {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 149        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 150        /* 0x47[7:0] = 00 gpio mode */},        \
 151        {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 152        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
 153        /*0x14[7] = 1 turn on ZCD */},  \
 154        {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 155        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
 156        /* 0x15[0] =1 trun on ZCD */},  \
 157        {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 158        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
 159        /*0x12[0] = 0 force PFM mode */},       \
 160        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 161        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
 162        /*0x23[4] = 1 hpon LDO sleep mode */},  \
 163        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 164        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
 165        /*0x8[1] = 0 ANA clk =500k */}, \
 166        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 167        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
 168         /*0x07=0x20 , SOP option to disable BG/MB*/},  \
 169        {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 170        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 171         /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */},   \
 172        {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 173        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 174         /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */},        \
 175        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 176        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
 177         /*0x04[11] = 2b'01 enable WL suspend*/},
 178
 179#define RTL8812_TRANS_CARDDIS_TO_CARDEMU                                \
 180        {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 181        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 182        /*0x12[0] = 1 force PWM mode */},       \
 183        {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 184        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
 185        /*0x14[7] = 0 turn off ZCD */}, \
 186        {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 187        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
 188        /* 0x15[0] =0 trun off ZCD */}, \
 189        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 190        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
 191        /*0x23[4] = 0 hpon LDO leave sleep mode */},    \
 192        {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 193        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 194        /* gpio0~7 input mode */},      \
 195        {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 196        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 197        /* gpio11 input mode, gpio10~8 input mode */}, \
 198        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 199        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
 200         /*0x04[10] = 0, enable SW LPS PCIE only*/},    \
 201        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 202        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
 203         /*0x04[11] = 2b'01enable WL suspend*/},        \
 204        {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 205        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
 206         /*0x03[2] = 1, enable 8051*/}, \
 207        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 208        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 209        /*PCIe DMA start*/},
 210
 211#define RTL8812_TRANS_CARDEMU_TO_PDN            \
 212        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 213        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
 214        /* 0x04[15] = 1*/},
 215
 216#define RTL8812_TRANS_PDN_TO_CARDEMU                    \
 217        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 218        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
 219        /* 0x04[15] = 0*/},
 220
 221#define RTL8812_TRANS_ACT_TO_LPS                \
 222        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 223        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
 224        /*PCIe DMA stop*/},     \
 225        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 226        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
 227        /*Tx Pause*/},          \
 228        {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 229        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 230        /*Should be zero if no packet is transmitting*/},       \
 231        {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 232        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 233        /*Should be zero if no packet is transmitting*/},       \
 234        {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 235        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 236        /*Should be zero if no packet is transmitting*/},       \
 237        {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 238        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 239        /*Should be zero if no packet is transmitting*/},       \
 240        {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 241        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
 242         /* 0xc00[7:0] = 4      turn off 3-wire */},    \
 243        {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 244        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
 245         /* 0xe00[7:0] = 4      turn off 3-wire */},    \
 246        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 247        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 248        /*CCK and OFDM are disabled,and clock are gated,and RF closed*/},       \
 249        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 250        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
 251        /*Delay 1us*/}, \
 252        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 253        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 254          /* Whole BB is reset*/},                      \
 255        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 256        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
 257        /*Reset MAC TRX*/},                     \
 258        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 259        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 260        /*check if removed later*/},            \
 261        {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 262        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
 263        /*Respond TxOK to scheduler*/},
 264
 265#define RTL8812_TRANS_LPS_TO_ACT                                        \
 266        {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 267        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
 268         /*SDIO RPWM*/},        \
 269        {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 270        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
 271         /*USB RPWM*/}, \
 272        {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 273        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
 274         /*PCIe RPWM*/},        \
 275        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 276        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
 277         /*Delay*/},    \
 278        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 279        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
 280         /*.    0x08[4] = 0              switch TSF to 40M*/},  \
 281        {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 282        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
 283         /*Polling 0x109[7]=0  TSF in 40M*/},                   \
 284        {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 285        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
 286         /*.    0x29[7:6] = 2b'00        enable BB clock*/},    \
 287        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 288        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 289         /*.    0x101[1] = 1*/},                                        \
 290        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 291        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
 292         /*.    0x100[7:0] = 0xFF        enable WMAC TRX*/},    \
 293        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 294        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
 295         /*.    0x02[1:0] = 2b'11        enable BB macro*/},    \
 296        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 297        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 298         /*.    0x522 = 0*/},
 299
 300#define RTL8812_TRANS_END                                       \
 301        {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
 302        0, PWR_CMD_END, 0, 0},
 303
 304extern struct wlan_pwr_cfg  rtl8812_power_on_flow
 305                [RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
 306                 RTL8812_TRANS_END_STEPS];
 307extern struct wlan_pwr_cfg  rtl8812_radio_off_flow
 308                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 309                 RTL8812_TRANS_END_STEPS];
 310extern struct wlan_pwr_cfg  rtl8812_card_disable_flow
 311                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 312                 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
 313                 RTL8812_TRANS_END_STEPS];
 314extern struct wlan_pwr_cfg  rtl8812_card_enable_flow
 315                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 316                 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
 317                 RTL8812_TRANS_END_STEPS];
 318extern struct wlan_pwr_cfg  rtl8812_suspend_flow
 319                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 320                 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
 321                 RTL8812_TRANS_END_STEPS];
 322extern struct wlan_pwr_cfg  rtl8812_resume_flow
 323                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 324                 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
 325                 RTL8812_TRANS_END_STEPS];
 326extern struct wlan_pwr_cfg  rtl8812_hwpdn_flow
 327                [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
 328                 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
 329                 RTL8812_TRANS_END_STEPS];
 330extern struct wlan_pwr_cfg  rtl8812_enter_lps_flow
 331                [RTL8812_TRANS_ACT_TO_LPS_STEPS +
 332                 RTL8812_TRANS_END_STEPS];
 333extern struct wlan_pwr_cfg  rtl8812_leave_lps_flow
 334                [RTL8812_TRANS_LPS_TO_ACT_STEPS +
 335                 RTL8812_TRANS_END_STEPS];
 336
 337/* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
 338 *      There are 6 HW Power States:
 339 *      0: POFF--Power Off
 340 *      1: PDN--Power Down
 341 *      2: CARDEMU--Card Emulation
 342 *      3: ACT--Active Mode
 343 *      4: LPS--Low Power State
 344 *      5: SUS--Suspend
 345 *
 346 *      The transision from different states are defined below
 347 *      TRANS_CARDEMU_TO_ACT
 348 *      TRANS_ACT_TO_CARDEMU
 349 *      TRANS_CARDEMU_TO_SUS
 350 *      TRANS_SUS_TO_CARDEMU
 351 *      TRANS_CARDEMU_TO_PDN
 352 *      TRANS_ACT_TO_LPS
 353 *      TRANS_LPS_TO_ACT
 354 *
 355 *      TRANS_END
 356 */
 357#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS     25
 358#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS     15
 359#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS     15
 360#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS     15
 361#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
 362#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS     15
 363#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS     15
 364#define RTL8821A_TRANS_ACT_TO_LPS_STEPS         15
 365#define RTL8821A_TRANS_LPS_TO_ACT_STEPS         15
 366#define RTL8821A_TRANS_END_STEPS                1
 367
 368#define RTL8821A_TRANS_CARDEMU_TO_ACT                                   \
 369        {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 370         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 371        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 372         /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/},   \
 373        {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,              \
 374         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 375        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
 376         /*0x67[0] = 0 to disable BT_GPS_SEL pins*/},   \
 377        {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 378         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 379        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
 380        /*Delay 1ms*/},   \
 381        {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 382         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 383        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
 384         /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/},   \
 385        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 386        PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
 387        /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/},     \
 388        {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 389        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
 390        /* Disable USB suspend */},     \
 391        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 392        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
 393        /* wait till 0x04[17] = 1    power ready*/},    \
 394        {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 395        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
 396        /* Enable USB suspend */},      \
 397        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 398        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 399        /* release WLON reset  0x04[16]=1*/},   \
 400        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 401        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
 402        /* disable HWPDN 0x04[15]=0*/}, \
 403        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 404        PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
 405        /* disable WL suspend*/},       \
 406        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 407        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 408        /* polling until return 0*/},   \
 409        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 410        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
 411        /**/},  \
 412        {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 413        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 414        /*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\
 415        {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 416        PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
 417        /*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A      \
 418         from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\
 419        {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 420        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
 421        /*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\
 422        {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 423        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 424        /*Enable falling edge triggering interrupt*/},\
 425        {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 426        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 427        /*Enable GPIO9 interrupt mode*/},\
 428        {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 429        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 430        /*Enable GPIO9 input mode*/},\
 431        {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 432        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
 433        /*Enable HSISR GPIO[C:0] interrupt*/},\
 434        {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 435        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 436        /*Enable HSISR GPIO9 interrupt*/},\
 437        {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 438        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
 439        /*0x7A = 0x3A start BT*/},\
 440        {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 441        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82  \
 442        /* 0x2C[23:12]=0x820 ; XTAL trim */}, \
 443        {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 444        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6  \
 445        /* 0x10[6]=1  */},
 446
 447#define RTL8821A_TRANS_ACT_TO_CARDEMU                                   \
 448        {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 449        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 450        /*0x1F[7:0] = 0 turn off RF*/}, \
 451        {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 452        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 453        /*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from         \
 454         register 0x65[2] */},\
 455        {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 456        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 457        /*Enable rising edge triggering interrupt*/}, \
 458        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 459        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 460         /*0x04[9] = 1 turn off MAC by HW state machine*/},     \
 461        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 462        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
 463         /*wait till 0x04[9] = 0 polling until return 0 to disable*/},  \
 464        {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
 465         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 466        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
 467         /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/},   \
 468        {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,              \
 469         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 470        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 471         /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/},
 472
 473#define RTL8821A_TRANS_CARDEMU_TO_SUS                                   \
 474        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 475        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
 476         /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},   \
 477        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,              \
 478         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 479        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
 480         /*0x04[12:11] = 2b'01 enable WL suspend*/},    \
 481        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 482        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
 483         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
 484        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 485        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
 486         /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/},   \
 487        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 488        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
 489         /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},   \
 490        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 491        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
 492         /*Set SDIO suspend local register*/},  \
 493        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 494        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
 495         /*wait power state to suspend*/},
 496
 497#define RTL8821A_TRANS_SUS_TO_CARDEMU                                   \
 498        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 499        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
 500         /*clear suspend enable and power down enable*/},       \
 501        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 502        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
 503         /*Set SDIO suspend local register*/},  \
 504        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 505        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
 506         /*wait power state to suspend*/},\
 507        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 508        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
 509         /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
 510        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 511        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
 512         /*0x04[12:11] = 2b'00 disable WL suspend*/},
 513
 514#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS                               \
 515        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 516        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
 517         /*0x07=0x20 , SOP option to disable BG/MB*/},  \
 518        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,              \
 519         PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
 520        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
 521         /*0x04[12:11] = 2b'01 enable WL suspend*/},    \
 522        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 523        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
 524         /*0x04[10] = 1, enable SW LPS*/},      \
 525        {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 526        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
 527         /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/},   \
 528        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 529        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
 530         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
 531        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 532        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
 533         /*Set SDIO suspend local register*/},  \
 534        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 535        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
 536         /*wait power state to suspend*/},
 537
 538#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU                               \
 539        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 540        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
 541         /*clear suspend enable and power down enable*/},       \
 542        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 543        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
 544         /*Set SDIO suspend local register*/},  \
 545        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 546        PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
 547         /*wait power state to suspend*/},\
 548        {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 549        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 550         /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/},   \
 551        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 552        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
 553         /*0x04[12:11] = 2b'00 disable WL suspend*/},\
 554        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 555        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
 556         /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
 557        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 558        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 559        /*PCIe DMA start*/},
 560
 561#define RTL8821A_TRANS_CARDEMU_TO_PDN                                   \
 562        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 563        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
 564         /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
 565        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,              \
 566         PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\
 567        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
 568         /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/},   \
 569        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 570        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 571        /* 0x04[16] = 0*/},\
 572        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 573        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
 574        /* 0x04[15] = 1*/},
 575
 576#define RTL8821A_TRANS_PDN_TO_CARDEMU                           \
 577        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 578        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
 579        /* 0x04[15] = 0*/},
 580
 581#define RTL8821A_TRANS_ACT_TO_LPS                                       \
 582        {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 583        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
 584        /*PCIe DMA stop*/},     \
 585        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 586        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
 587        /*Tx Pause*/},  \
 588        {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 589        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 590        /*Should be zero if no packet is transmitting*/},       \
 591        {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 592        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 593        /*Should be zero if no packet is transmitting*/},       \
 594        {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 595        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 596        /*Should be zero if no packet is transmitting*/},       \
 597        {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 598        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
 599        /*Should be zero if no packet is transmitting*/},       \
 600        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 601        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
 602        /*CCK and OFDM are disabled,and clock are gated*/},     \
 603        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 604        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
 605        /*Delay 1us*/}, \
 606        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 607        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 608        /*Whole BB is reset*/}, \
 609        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 610        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
 611        /*Reset MAC TRX*/},     \
 612        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 613        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
 614        /*check if removed later*/},    \
 615        {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 616        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
 617        /*When driver enter Sus/ Disable, enable LOP for BT*/}, \
 618        {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 619        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
 620        /*Respond TxOK to scheduler*/},
 621
 622#define RTL8821A_TRANS_LPS_TO_ACT                                       \
 623        {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
 624        PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
 625         /*SDIO RPWM*/},\
 626        {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
 627        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
 628         /*USB RPWM*/},\
 629        {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
 630        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
 631         /*PCIe RPWM*/},\
 632        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 633        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
 634         /*Delay*/},\
 635        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 636        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
 637         /*.    0x08[4] = 0              switch TSF to 40M*/},\
 638        {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 639        PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
 640         /*Polling 0x109[7]=0  TSF in 40M*/},\
 641        {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 642        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
 643         /*.    0x29[7:6] = 2b'00        enable BB clock*/},\
 644        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 645        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
 646         /*.    0x101[1] = 1*/},\
 647        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 648        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
 649         /*.    0x100[7:0] = 0xFF        enable WMAC TRX*/},\
 650        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 651        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
 652         /*.    0x02[1:0] = 2b'11        enable BB macro*/},\
 653        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 654        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
 655         /*.    0x522 = 0*/},
 656
 657#define RTL8821A_TRANS_END                                      \
 658        {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
 659        0, PWR_CMD_END, 0, 0},
 660
 661extern struct wlan_pwr_cfg rtl8821A_power_on_flow
 662                [RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
 663                 RTL8821A_TRANS_END_STEPS];
 664extern struct wlan_pwr_cfg rtl8821A_radio_off_flow
 665                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 666                 RTL8821A_TRANS_END_STEPS];
 667extern struct wlan_pwr_cfg rtl8821A_card_disable_flow
 668                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 669                 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
 670                 RTL8821A_TRANS_END_STEPS];
 671extern struct wlan_pwr_cfg rtl8821A_card_enable_flow
 672                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 673                 RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
 674                 RTL8821A_TRANS_END_STEPS];
 675extern struct wlan_pwr_cfg rtl8821A_suspend_flow
 676                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 677                 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
 678                 RTL8821A_TRANS_END_STEPS];
 679extern struct wlan_pwr_cfg rtl8821A_resume_flow
 680                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 681                 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
 682                 RTL8821A_TRANS_END_STEPS];
 683extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow
 684                [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
 685                 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
 686                 RTL8821A_TRANS_END_STEPS];
 687extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow
 688                [RTL8821A_TRANS_ACT_TO_LPS_STEPS +
 689                 RTL8821A_TRANS_END_STEPS];
 690extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow
 691                [RTL8821A_TRANS_LPS_TO_ACT_STEPS +
 692                 RTL8821A_TRANS_END_STEPS];
 693
 694/*RTL8812 Power Configuration CMDs for PCIe interface*/
 695#define RTL8812_NIC_PWR_ON_FLOW                 rtl8812_power_on_flow
 696#define RTL8812_NIC_RF_OFF_FLOW                 rtl8812_radio_off_flow
 697#define RTL8812_NIC_DISABLE_FLOW                rtl8812_card_disable_flow
 698#define RTL8812_NIC_ENABLE_FLOW                 rtl8812_card_enable_flow
 699#define RTL8812_NIC_SUSPEND_FLOW                rtl8812_suspend_flow
 700#define RTL8812_NIC_RESUME_FLOW                 rtl8812_resume_flow
 701#define RTL8812_NIC_PDN_FLOW                    rtl8812_hwpdn_flow
 702#define RTL8812_NIC_LPS_ENTER_FLOW              rtl8812_enter_lps_flow
 703#define RTL8812_NIC_LPS_LEAVE_FLOW              rtl8812_leave_lps_flow
 704
 705/* RTL8821 Power Configuration CMDs for PCIe interface */
 706#define RTL8821A_NIC_PWR_ON_FLOW                rtl8821A_power_on_flow
 707#define RTL8821A_NIC_RF_OFF_FLOW                rtl8821A_radio_off_flow
 708#define RTL8821A_NIC_DISABLE_FLOW               rtl8821A_card_disable_flow
 709#define RTL8821A_NIC_ENABLE_FLOW                rtl8821A_card_enable_flow
 710#define RTL8821A_NIC_SUSPEND_FLOW               rtl8821A_suspend_flow
 711#define RTL8821A_NIC_RESUME_FLOW                rtl8821A_resume_flow
 712#define RTL8821A_NIC_PDN_FLOW                   rtl8821A_hwpdn_flow
 713#define RTL8821A_NIC_LPS_ENTER_FLOW             rtl8821A_enter_lps_flow
 714#define RTL8821A_NIC_LPS_LEAVE_FLOW             rtl8821A_leave_lps_flow
 715
 716#endif
 717