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6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27
28#define SW_RESET BIT(0)
29
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36
37#define PHYSTATUS BIT(6)
38
39#define PCS_READY BIT(0)
40
41
42
43#define SW_DPPHY_RESET BIT(0)
44
45#define SW_DPPHY_RESET_MUX BIT(1)
46
47#define SW_USB3PHY_RESET BIT(2)
48
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51
52#define USB3_MODE BIT(0)
53#define DP_MODE BIT(1)
54
55
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60
61#define IRQ_CLEAR BIT(0)
62
63
64#define RCVR_DETECT BIT(0)
65
66
67#define CLAMP_EN BIT(0)
68
69#define PHY_INIT_COMPLETE_TIMEOUT 1000
70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
75
76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
77
78struct qmp_phy_init_tbl {
79 unsigned int offset;
80 unsigned int val;
81
82
83
84
85 int in_layout;
86};
87
88#define QMP_PHY_INIT_CFG(o, v) \
89 { \
90 .offset = o, \
91 .val = v, \
92 }
93
94#define QMP_PHY_INIT_CFG_L(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .in_layout = 1, \
99 }
100
101
102enum qphy_reg_layout {
103
104 QPHY_COM_SW_RESET,
105 QPHY_COM_POWER_DOWN_CONTROL,
106 QPHY_COM_START_CONTROL,
107 QPHY_COM_PCS_READY_STATUS,
108
109 QPHY_PLL_LOCK_CHK_DLY_TIME,
110 QPHY_FLL_CNTRL1,
111 QPHY_FLL_CNTRL2,
112 QPHY_FLL_CNT_VAL_L,
113 QPHY_FLL_CNT_VAL_H_TOL,
114 QPHY_FLL_MAN_CODE,
115 QPHY_SW_RESET,
116 QPHY_START_CTRL,
117 QPHY_PCS_READY_STATUS,
118 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
119 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
120 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
121};
122
123static const unsigned int pciephy_regs_layout[] = {
124 [QPHY_COM_SW_RESET] = 0x400,
125 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
126 [QPHY_COM_START_CONTROL] = 0x408,
127 [QPHY_COM_PCS_READY_STATUS] = 0x448,
128 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
129 [QPHY_FLL_CNTRL1] = 0xc4,
130 [QPHY_FLL_CNTRL2] = 0xc8,
131 [QPHY_FLL_CNT_VAL_L] = 0xcc,
132 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
133 [QPHY_FLL_MAN_CODE] = 0xd4,
134 [QPHY_SW_RESET] = 0x00,
135 [QPHY_START_CTRL] = 0x08,
136 [QPHY_PCS_READY_STATUS] = 0x174,
137};
138
139static const unsigned int usb3phy_regs_layout[] = {
140 [QPHY_FLL_CNTRL1] = 0xc0,
141 [QPHY_FLL_CNTRL2] = 0xc4,
142 [QPHY_FLL_CNT_VAL_L] = 0xc8,
143 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
144 [QPHY_FLL_MAN_CODE] = 0xd0,
145 [QPHY_SW_RESET] = 0x00,
146 [QPHY_START_CTRL] = 0x08,
147 [QPHY_PCS_READY_STATUS] = 0x17c,
148 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
149 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
150 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
151};
152
153static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
154 [QPHY_SW_RESET] = 0x00,
155 [QPHY_START_CTRL] = 0x08,
156 [QPHY_PCS_READY_STATUS] = 0x174,
157 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
158 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
159 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
160};
161
162static const unsigned int sdm845_ufsphy_regs_layout[] = {
163 [QPHY_START_CTRL] = 0x00,
164 [QPHY_PCS_READY_STATUS] = 0x160,
165};
166
167static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
168 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
169 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
170 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
171 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
172 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
173 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
174 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
175 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
176 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
177 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
178 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
179 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
180 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
181 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
182 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
183 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
184 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
185 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
187 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
188 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
189 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
190 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
191 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
192 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
193 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
194 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
195 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
196 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
197 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
198 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
199 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
200 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
201 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
203 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
204 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
205 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
206 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
207 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
208 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
209 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
210 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
211};
212
213static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
214 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
215 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
216};
217
218static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
219 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
220 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
221 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
222 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
223 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
224 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
225 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
226 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
227 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
228 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
229};
230
231static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
232 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
233 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
234 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
235
236 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
237
238 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
239 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
240 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
241 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
242 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
243};
244
245static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
246 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
247 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
248 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
249 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
250 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
251 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
252 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
253 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
254 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
255
256 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
257 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
258 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
259 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
260 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
261 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
262 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
263 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
264 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
265 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
266 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
267 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
268 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
269 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
270 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
271 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
272
273 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
274 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
275 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
276 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
277 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
278 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
279 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
280};
281
282static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
283 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
284 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
285 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
286};
287
288static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
289 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
290 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
291 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
292 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
293 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
294 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
295 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
296 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
297 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
298 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
299};
300
301static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
302
303 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
304 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
305 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
306 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
307 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
308
309
310 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
311 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
312 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
313 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
314};
315
316static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
317 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
318 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
319 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
321 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
322 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
323 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
324 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
325 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
326 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
328 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
329 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
330 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
331 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
332 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
333 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
334 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
335 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
336 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
337 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
338 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
339 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
340 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
341 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
342 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
343 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
344 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
345 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
346 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
347 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
348 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
349 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
352 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
353 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
354 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
355 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
357 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
358 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
359};
360
361static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
362 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
363 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
364 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
365 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
366};
367
368static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
369 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
370 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
371 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
372 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
373 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
374 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
375 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
376 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
377};
378
379static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
380 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
381 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
382 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
383 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
384 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
385 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
386 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
387 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
388 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
389 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
390 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
391 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
392 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
393};
394
395static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
432};
433
434static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
435 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
436 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
437 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
438 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
439 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
440};
441
442static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
452};
453
454static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
455
456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
461
462
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
467
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
487
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
499};
500
501static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
538};
539
540static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
541 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
542 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
543 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
544 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
545 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
546};
547
548static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
560};
561
562static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
563
564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
569
570
571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
575
576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
595
596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
607
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
610};
611
612static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
616 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
617 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
618 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
623 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
624 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
625 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
626 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
627 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
628 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
629 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
630 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
631 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
632 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
633 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
634 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
635 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
636 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
637 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
638 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
639 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
640 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
641 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
642 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
643 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
644 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
645 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
646 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
647 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
648 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
649
650
651 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
652};
653
654static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
655 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
656 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
657 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
658};
659
660static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
661 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
662 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
663 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
664 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
665 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
666 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
667 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
668 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
669 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
670 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
671 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
672 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
673 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
674 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
675 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
676 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
677};
678
679static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
684 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
685 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
686 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
687 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
688};
689
690static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
691 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
692 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
693 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
694 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
695 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
696 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
697 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
698 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
699 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
700 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
701 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
702 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
703 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
704 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
705 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
706 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
707 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
708 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
709 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
710 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
711 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
712 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
713 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
714 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
715 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
716 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
717 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
718 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
719 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
720 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
721 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
722 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
723 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
724 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
725 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
726 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
727 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
728 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
729};
730
731static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
732 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
733 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
734 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
735 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
736};
737
738static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
739 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
740 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
741 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
742 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
743 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
744 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
745 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
746 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
747 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
748 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
749 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
750 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
751 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
752 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
753 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
754 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
755 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
756};
757
758static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
759 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
760 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
761 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
762 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
763 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
764 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
765 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
766 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
767 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
768 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
769 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
770 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
771 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
772 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
773 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
774 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
777 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
778 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
779 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
780 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
781 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
782 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
783 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
784 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
785 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
786 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
787 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
788 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
789 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
790 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
791 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
792 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
793 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
794 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
795 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
796 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
797};
798
799
800
801struct qmp_phy_cfg {
802
803 unsigned int type;
804
805 int nlanes;
806
807
808 const struct qmp_phy_init_tbl *serdes_tbl;
809 int serdes_tbl_num;
810 const struct qmp_phy_init_tbl *tx_tbl;
811 int tx_tbl_num;
812 const struct qmp_phy_init_tbl *rx_tbl;
813 int rx_tbl_num;
814 const struct qmp_phy_init_tbl *pcs_tbl;
815 int pcs_tbl_num;
816
817
818 const char * const *clk_list;
819 int num_clks;
820
821 const char * const *reset_list;
822 int num_resets;
823
824 const char * const *vreg_list;
825 int num_vregs;
826
827
828 const unsigned int *regs;
829
830 unsigned int start_ctrl;
831 unsigned int pwrdn_ctrl;
832 unsigned int mask_pcs_ready;
833 unsigned int mask_com_pcs_ready;
834
835
836 bool has_phy_com_ctrl;
837
838 bool has_lane_rst;
839
840 bool has_pwrdn_delay;
841
842 int pwrdn_delay_min;
843 int pwrdn_delay_max;
844
845
846 bool has_phy_dp_com_ctrl;
847
848 bool is_dual_lane_phy;
849
850
851 bool no_pcs_sw_reset;
852};
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869struct qmp_phy {
870 struct phy *phy;
871 void __iomem *tx;
872 void __iomem *rx;
873 void __iomem *pcs;
874 void __iomem *tx2;
875 void __iomem *rx2;
876 void __iomem *pcs_misc;
877 struct clk *pipe_clk;
878 unsigned int index;
879 struct qcom_qmp *qmp;
880 struct reset_control *lane_rst;
881};
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901struct qcom_qmp {
902 struct device *dev;
903 void __iomem *serdes;
904 void __iomem *dp_com;
905
906 struct clk_bulk_data *clks;
907 struct reset_control **resets;
908 struct regulator_bulk_data *vregs;
909
910 const struct qmp_phy_cfg *cfg;
911 struct qmp_phy **phys;
912
913 struct mutex phy_mutex;
914 int init_count;
915 bool phy_initialized;
916 enum phy_mode mode;
917};
918
919static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
920{
921 u32 reg;
922
923 reg = readl(base + offset);
924 reg |= val;
925 writel(reg, base + offset);
926
927
928 readl(base + offset);
929}
930
931static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
932{
933 u32 reg;
934
935 reg = readl(base + offset);
936 reg &= ~val;
937 writel(reg, base + offset);
938
939
940 readl(base + offset);
941}
942
943
944static const char * const msm8996_phy_clk_l[] = {
945 "aux", "cfg_ahb", "ref",
946};
947
948static const char * const qmp_v3_phy_clk_l[] = {
949 "aux", "cfg_ahb", "ref", "com_aux",
950};
951
952static const char * const sdm845_ufs_phy_clk_l[] = {
953 "ref", "ref_aux",
954};
955
956
957static const char * const msm8996_pciephy_reset_l[] = {
958 "phy", "common", "cfg",
959};
960
961static const char * const msm8996_usb3phy_reset_l[] = {
962 "phy", "common",
963};
964
965
966static const char * const qmp_phy_vreg_l[] = {
967 "vdda-phy", "vdda-pll",
968};
969
970static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
971 .type = PHY_TYPE_PCIE,
972 .nlanes = 3,
973
974 .serdes_tbl = msm8996_pcie_serdes_tbl,
975 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
976 .tx_tbl = msm8996_pcie_tx_tbl,
977 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
978 .rx_tbl = msm8996_pcie_rx_tbl,
979 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
980 .pcs_tbl = msm8996_pcie_pcs_tbl,
981 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
982 .clk_list = msm8996_phy_clk_l,
983 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
984 .reset_list = msm8996_pciephy_reset_l,
985 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
986 .vreg_list = qmp_phy_vreg_l,
987 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
988 .regs = pciephy_regs_layout,
989
990 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
991 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
992 .mask_com_pcs_ready = PCS_READY,
993
994 .has_phy_com_ctrl = true,
995 .has_lane_rst = true,
996 .has_pwrdn_delay = true,
997 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
998 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
999};
1000
1001static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1002 .type = PHY_TYPE_USB3,
1003 .nlanes = 1,
1004
1005 .serdes_tbl = msm8996_usb3_serdes_tbl,
1006 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1007 .tx_tbl = msm8996_usb3_tx_tbl,
1008 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1009 .rx_tbl = msm8996_usb3_rx_tbl,
1010 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1011 .pcs_tbl = msm8996_usb3_pcs_tbl,
1012 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1013 .clk_list = msm8996_phy_clk_l,
1014 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1015 .reset_list = msm8996_usb3phy_reset_l,
1016 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1017 .vreg_list = qmp_phy_vreg_l,
1018 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1019 .regs = usb3phy_regs_layout,
1020
1021 .start_ctrl = SERDES_START | PCS_START,
1022 .pwrdn_ctrl = SW_PWRDN,
1023 .mask_pcs_ready = PHYSTATUS,
1024};
1025
1026
1027static const char * const ipq8074_pciephy_reset_l[] = {
1028 "phy", "common",
1029};
1030
1031static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1032 .type = PHY_TYPE_PCIE,
1033 .nlanes = 1,
1034
1035 .serdes_tbl = ipq8074_pcie_serdes_tbl,
1036 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1037 .tx_tbl = ipq8074_pcie_tx_tbl,
1038 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1039 .rx_tbl = ipq8074_pcie_rx_tbl,
1040 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1041 .pcs_tbl = ipq8074_pcie_pcs_tbl,
1042 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1043 .clk_list = NULL,
1044 .num_clks = 0,
1045 .reset_list = ipq8074_pciephy_reset_l,
1046 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1047 .vreg_list = NULL,
1048 .num_vregs = 0,
1049 .regs = pciephy_regs_layout,
1050
1051 .start_ctrl = SERDES_START | PCS_START,
1052 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1053 .mask_pcs_ready = PHYSTATUS,
1054
1055 .has_phy_com_ctrl = false,
1056 .has_lane_rst = false,
1057 .has_pwrdn_delay = true,
1058 .pwrdn_delay_min = 995,
1059 .pwrdn_delay_max = 1005,
1060};
1061
1062static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1063 .type = PHY_TYPE_USB3,
1064 .nlanes = 1,
1065
1066 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1067 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1068 .tx_tbl = qmp_v3_usb3_tx_tbl,
1069 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1070 .rx_tbl = qmp_v3_usb3_rx_tbl,
1071 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1072 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1073 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1074 .clk_list = qmp_v3_phy_clk_l,
1075 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1076 .reset_list = msm8996_usb3phy_reset_l,
1077 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1078 .vreg_list = qmp_phy_vreg_l,
1079 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1080 .regs = qmp_v3_usb3phy_regs_layout,
1081
1082 .start_ctrl = SERDES_START | PCS_START,
1083 .pwrdn_ctrl = SW_PWRDN,
1084 .mask_pcs_ready = PHYSTATUS,
1085
1086 .has_pwrdn_delay = true,
1087 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1088 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1089
1090 .has_phy_dp_com_ctrl = true,
1091 .is_dual_lane_phy = true,
1092};
1093
1094static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1095 .type = PHY_TYPE_USB3,
1096 .nlanes = 1,
1097
1098 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1099 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1100 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1101 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1102 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1103 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1104 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1105 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1106 .clk_list = qmp_v3_phy_clk_l,
1107 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1108 .reset_list = msm8996_usb3phy_reset_l,
1109 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1110 .vreg_list = qmp_phy_vreg_l,
1111 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1112 .regs = qmp_v3_usb3phy_regs_layout,
1113
1114 .start_ctrl = SERDES_START | PCS_START,
1115 .pwrdn_ctrl = SW_PWRDN,
1116 .mask_pcs_ready = PHYSTATUS,
1117
1118 .has_pwrdn_delay = true,
1119 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1120 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1121};
1122
1123static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1124 .type = PHY_TYPE_UFS,
1125 .nlanes = 2,
1126
1127 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
1128 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1129 .tx_tbl = sdm845_ufsphy_tx_tbl,
1130 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1131 .rx_tbl = sdm845_ufsphy_rx_tbl,
1132 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1133 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
1134 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1135 .clk_list = sdm845_ufs_phy_clk_l,
1136 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1137 .vreg_list = qmp_phy_vreg_l,
1138 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1139 .regs = sdm845_ufsphy_regs_layout,
1140
1141 .start_ctrl = SERDES_START,
1142 .pwrdn_ctrl = SW_PWRDN,
1143 .mask_pcs_ready = PCS_READY,
1144
1145 .is_dual_lane_phy = true,
1146 .no_pcs_sw_reset = true,
1147};
1148
1149static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1150 .type = PHY_TYPE_USB3,
1151 .nlanes = 1,
1152
1153 .serdes_tbl = msm8998_usb3_serdes_tbl,
1154 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1155 .tx_tbl = msm8998_usb3_tx_tbl,
1156 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1157 .rx_tbl = msm8998_usb3_rx_tbl,
1158 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1159 .pcs_tbl = msm8998_usb3_pcs_tbl,
1160 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1161 .clk_list = msm8996_phy_clk_l,
1162 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1163 .reset_list = msm8996_usb3phy_reset_l,
1164 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1165 .vreg_list = qmp_phy_vreg_l,
1166 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1167 .regs = qmp_v3_usb3phy_regs_layout,
1168
1169 .start_ctrl = SERDES_START | PCS_START,
1170 .pwrdn_ctrl = SW_PWRDN,
1171 .mask_pcs_ready = PHYSTATUS,
1172
1173 .is_dual_lane_phy = true,
1174};
1175
1176static void qcom_qmp_phy_configure(void __iomem *base,
1177 const unsigned int *regs,
1178 const struct qmp_phy_init_tbl tbl[],
1179 int num)
1180{
1181 int i;
1182 const struct qmp_phy_init_tbl *t = tbl;
1183
1184 if (!t)
1185 return;
1186
1187 for (i = 0; i < num; i++, t++) {
1188 if (t->in_layout)
1189 writel(t->val, base + regs[t->offset]);
1190 else
1191 writel(t->val, base + t->offset);
1192 }
1193}
1194
1195static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1196{
1197 struct qcom_qmp *qmp = qphy->qmp;
1198 const struct qmp_phy_cfg *cfg = qmp->cfg;
1199 void __iomem *serdes = qmp->serdes;
1200 void __iomem *pcs = qphy->pcs;
1201 void __iomem *dp_com = qmp->dp_com;
1202 int ret, i;
1203
1204 mutex_lock(&qmp->phy_mutex);
1205 if (qmp->init_count++) {
1206 mutex_unlock(&qmp->phy_mutex);
1207 return 0;
1208 }
1209
1210
1211 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1212 if (ret) {
1213 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1214 goto err_reg_enable;
1215 }
1216
1217 for (i = 0; i < cfg->num_resets; i++) {
1218 ret = reset_control_assert(qmp->resets[i]);
1219 if (ret) {
1220 dev_err(qmp->dev, "%s reset assert failed\n",
1221 cfg->reset_list[i]);
1222 goto err_rst_assert;
1223 }
1224 }
1225
1226 for (i = cfg->num_resets - 1; i >= 0; i--) {
1227 ret = reset_control_deassert(qmp->resets[i]);
1228 if (ret) {
1229 dev_err(qmp->dev, "%s reset deassert failed\n",
1230 qmp->cfg->reset_list[i]);
1231 goto err_rst;
1232 }
1233 }
1234
1235 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1236 if (ret) {
1237 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1238 goto err_rst;
1239 }
1240
1241 if (cfg->has_phy_dp_com_ctrl) {
1242 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1243 SW_PWRDN);
1244
1245 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1246 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1247 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1248
1249 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1250 USB3_MODE | DP_MODE);
1251
1252
1253 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1254 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1255 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1256 }
1257
1258 if (cfg->has_phy_com_ctrl)
1259 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1260 SW_PWRDN);
1261 else
1262 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1263
1264
1265 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1266 cfg->serdes_tbl_num);
1267
1268 if (cfg->has_phy_com_ctrl) {
1269 void __iomem *status;
1270 unsigned int mask, val;
1271
1272 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1273 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1274 SERDES_START | PCS_START);
1275
1276 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1277 mask = cfg->mask_com_pcs_ready;
1278
1279 ret = readl_poll_timeout(status, val, (val & mask), 10,
1280 PHY_INIT_COMPLETE_TIMEOUT);
1281 if (ret) {
1282 dev_err(qmp->dev,
1283 "phy common block init timed-out\n");
1284 goto err_com_init;
1285 }
1286 }
1287
1288 mutex_unlock(&qmp->phy_mutex);
1289
1290 return 0;
1291
1292err_com_init:
1293 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1294err_rst:
1295 while (++i < cfg->num_resets)
1296 reset_control_assert(qmp->resets[i]);
1297err_rst_assert:
1298 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1299err_reg_enable:
1300 mutex_unlock(&qmp->phy_mutex);
1301
1302 return ret;
1303}
1304
1305static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1306{
1307 const struct qmp_phy_cfg *cfg = qmp->cfg;
1308 void __iomem *serdes = qmp->serdes;
1309 int i = cfg->num_resets;
1310
1311 mutex_lock(&qmp->phy_mutex);
1312 if (--qmp->init_count) {
1313 mutex_unlock(&qmp->phy_mutex);
1314 return 0;
1315 }
1316
1317 if (cfg->has_phy_com_ctrl) {
1318 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1319 SERDES_START | PCS_START);
1320 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1321 SW_RESET);
1322 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1323 SW_PWRDN);
1324 }
1325
1326 while (--i >= 0)
1327 reset_control_assert(qmp->resets[i]);
1328
1329 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1330
1331 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1332
1333 mutex_unlock(&qmp->phy_mutex);
1334
1335 return 0;
1336}
1337
1338
1339static int qcom_qmp_phy_init(struct phy *phy)
1340{
1341 struct qmp_phy *qphy = phy_get_drvdata(phy);
1342 struct qcom_qmp *qmp = qphy->qmp;
1343 const struct qmp_phy_cfg *cfg = qmp->cfg;
1344 void __iomem *tx = qphy->tx;
1345 void __iomem *rx = qphy->rx;
1346 void __iomem *pcs = qphy->pcs;
1347 void __iomem *dp_com = qmp->dp_com;
1348 void __iomem *status;
1349 unsigned int mask, val;
1350 int ret;
1351
1352 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1353
1354 ret = qcom_qmp_phy_com_init(qphy);
1355 if (ret)
1356 return ret;
1357
1358 if (cfg->has_lane_rst) {
1359 ret = reset_control_deassert(qphy->lane_rst);
1360 if (ret) {
1361 dev_err(qmp->dev, "lane%d reset deassert failed\n",
1362 qphy->index);
1363 goto err_lane_rst;
1364 }
1365 }
1366
1367 ret = clk_prepare_enable(qphy->pipe_clk);
1368 if (ret) {
1369 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1370 goto err_clk_enable;
1371 }
1372
1373
1374 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1375
1376 if (cfg->is_dual_lane_phy)
1377 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
1378 cfg->tx_tbl, cfg->tx_tbl_num);
1379
1380 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1381 if (cfg->is_dual_lane_phy)
1382 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
1383 cfg->rx_tbl, cfg->rx_tbl_num);
1384
1385 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1386
1387
1388
1389
1390
1391
1392 if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
1393 goto out;
1394
1395
1396
1397
1398
1399 if(cfg->type == PHY_TYPE_PCIE)
1400 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1401
1402 if (cfg->has_pwrdn_delay)
1403 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1404
1405
1406 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1407 if (cfg->has_phy_dp_com_ctrl)
1408 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1409
1410
1411 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1412
1413 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1414 mask = cfg->mask_pcs_ready;
1415
1416 ret = readl_poll_timeout(status, val, !(val & mask), 1,
1417 PHY_INIT_COMPLETE_TIMEOUT);
1418 if (ret) {
1419 dev_err(qmp->dev, "phy initialization timed-out\n");
1420 goto err_pcs_ready;
1421 }
1422 qmp->phy_initialized = true;
1423
1424out:
1425 return ret;
1426
1427err_pcs_ready:
1428 clk_disable_unprepare(qphy->pipe_clk);
1429err_clk_enable:
1430 if (cfg->has_lane_rst)
1431 reset_control_assert(qphy->lane_rst);
1432err_lane_rst:
1433 qcom_qmp_phy_com_exit(qmp);
1434
1435 return ret;
1436}
1437
1438static int qcom_qmp_phy_exit(struct phy *phy)
1439{
1440 struct qmp_phy *qphy = phy_get_drvdata(phy);
1441 struct qcom_qmp *qmp = qphy->qmp;
1442 const struct qmp_phy_cfg *cfg = qmp->cfg;
1443
1444 clk_disable_unprepare(qphy->pipe_clk);
1445
1446
1447 if (!cfg->no_pcs_sw_reset)
1448 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1449
1450
1451 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1452
1453
1454 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1455
1456 if (cfg->has_lane_rst)
1457 reset_control_assert(qphy->lane_rst);
1458
1459 qcom_qmp_phy_com_exit(qmp);
1460
1461 qmp->phy_initialized = false;
1462
1463 return 0;
1464}
1465
1466static int qcom_qmp_phy_poweron(struct phy *phy)
1467{
1468 struct qmp_phy *qphy = phy_get_drvdata(phy);
1469 struct qcom_qmp *qmp = qphy->qmp;
1470 const struct qmp_phy_cfg *cfg = qmp->cfg;
1471 void __iomem *pcs = qphy->pcs;
1472 void __iomem *status;
1473 unsigned int mask, val;
1474 int ret = 0;
1475
1476 if (cfg->type != PHY_TYPE_UFS)
1477 return 0;
1478
1479
1480
1481
1482
1483
1484 if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
1485 (qmp->init_count != 0)) {
1486
1487 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1488
1489 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1490 mask = cfg->mask_pcs_ready;
1491
1492 ret = readl_poll_timeout(status, val, !(val & mask), 1,
1493 PHY_INIT_COMPLETE_TIMEOUT);
1494 if (ret) {
1495 dev_err(qmp->dev, "phy initialization timed-out\n");
1496 return ret;
1497 }
1498 qmp->phy_initialized = true;
1499 }
1500
1501 return ret;
1502}
1503
1504static int qcom_qmp_phy_set_mode(struct phy *phy,
1505 enum phy_mode mode, int submode)
1506{
1507 struct qmp_phy *qphy = phy_get_drvdata(phy);
1508 struct qcom_qmp *qmp = qphy->qmp;
1509
1510 qmp->mode = mode;
1511
1512 return 0;
1513}
1514
1515static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1516{
1517 struct qcom_qmp *qmp = qphy->qmp;
1518 const struct qmp_phy_cfg *cfg = qmp->cfg;
1519 void __iomem *pcs = qphy->pcs;
1520 void __iomem *pcs_misc = qphy->pcs_misc;
1521 u32 intr_mask;
1522
1523 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1524 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1525 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1526 else
1527 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1528
1529
1530 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1531
1532 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1533
1534 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1535 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1536
1537
1538 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1539
1540
1541 if (pcs_misc)
1542 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1543}
1544
1545static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1546{
1547 struct qcom_qmp *qmp = qphy->qmp;
1548 const struct qmp_phy_cfg *cfg = qmp->cfg;
1549 void __iomem *pcs = qphy->pcs;
1550 void __iomem *pcs_misc = qphy->pcs_misc;
1551
1552
1553 if (pcs_misc)
1554 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1555
1556 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1557 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1558
1559 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1560
1561 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1562}
1563
1564static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1565{
1566 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1567 struct qmp_phy *qphy = qmp->phys[0];
1568 const struct qmp_phy_cfg *cfg = qmp->cfg;
1569
1570 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1571
1572
1573 if (cfg->type != PHY_TYPE_USB3)
1574 return 0;
1575
1576 if (!qmp->phy_initialized) {
1577 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1578 return 0;
1579 }
1580
1581 qcom_qmp_phy_enable_autonomous_mode(qphy);
1582
1583 clk_disable_unprepare(qphy->pipe_clk);
1584 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1585
1586 return 0;
1587}
1588
1589static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1590{
1591 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1592 struct qmp_phy *qphy = qmp->phys[0];
1593 const struct qmp_phy_cfg *cfg = qmp->cfg;
1594 int ret = 0;
1595
1596 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1597
1598
1599 if (cfg->type != PHY_TYPE_USB3)
1600 return 0;
1601
1602 if (!qmp->phy_initialized) {
1603 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1604 return 0;
1605 }
1606
1607 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1608 if (ret) {
1609 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1610 return ret;
1611 }
1612
1613 ret = clk_prepare_enable(qphy->pipe_clk);
1614 if (ret) {
1615 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1616 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1617 return ret;
1618 }
1619
1620 qcom_qmp_phy_disable_autonomous_mode(qphy);
1621
1622 return 0;
1623}
1624
1625static int qcom_qmp_phy_vreg_init(struct device *dev)
1626{
1627 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1628 int num = qmp->cfg->num_vregs;
1629 int i;
1630
1631 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1632 if (!qmp->vregs)
1633 return -ENOMEM;
1634
1635 for (i = 0; i < num; i++)
1636 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1637
1638 return devm_regulator_bulk_get(dev, num, qmp->vregs);
1639}
1640
1641static int qcom_qmp_phy_reset_init(struct device *dev)
1642{
1643 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1644 int i;
1645
1646 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1647 sizeof(*qmp->resets), GFP_KERNEL);
1648 if (!qmp->resets)
1649 return -ENOMEM;
1650
1651 for (i = 0; i < qmp->cfg->num_resets; i++) {
1652 struct reset_control *rst;
1653 const char *name = qmp->cfg->reset_list[i];
1654
1655 rst = devm_reset_control_get(dev, name);
1656 if (IS_ERR(rst)) {
1657 dev_err(dev, "failed to get %s reset\n", name);
1658 return PTR_ERR(rst);
1659 }
1660 qmp->resets[i] = rst;
1661 }
1662
1663 return 0;
1664}
1665
1666static int qcom_qmp_phy_clk_init(struct device *dev)
1667{
1668 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1669 int num = qmp->cfg->num_clks;
1670 int i;
1671
1672 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1673 if (!qmp->clks)
1674 return -ENOMEM;
1675
1676 for (i = 0; i < num; i++)
1677 qmp->clks[i].id = qmp->cfg->clk_list[i];
1678
1679 return devm_clk_bulk_get(dev, num, qmp->clks);
1680}
1681
1682static void phy_pipe_clk_release_provider(void *res)
1683{
1684 of_clk_del_provider(res);
1685}
1686
1687
1688
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1704
1705static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1706{
1707 struct clk_fixed_rate *fixed;
1708 struct clk_init_data init = { };
1709 int ret;
1710
1711 if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1712 (qmp->cfg->type != PHY_TYPE_PCIE)) {
1713
1714 return 0;
1715 }
1716
1717 ret = of_property_read_string(np, "clock-output-names", &init.name);
1718 if (ret) {
1719 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1720 return ret;
1721 }
1722
1723 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1724 if (!fixed)
1725 return -ENOMEM;
1726
1727 init.ops = &clk_fixed_rate_ops;
1728
1729
1730 fixed->fixed_rate = 125000000;
1731 fixed->hw.init = &init;
1732
1733 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1734 if (ret)
1735 return ret;
1736
1737 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1738 if (ret)
1739 return ret;
1740
1741
1742
1743
1744
1745 ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
1746 if (ret)
1747 phy_pipe_clk_release_provider(np);
1748
1749 return ret;
1750}
1751
1752static const struct phy_ops qcom_qmp_phy_gen_ops = {
1753 .init = qcom_qmp_phy_init,
1754 .exit = qcom_qmp_phy_exit,
1755 .power_on = qcom_qmp_phy_poweron,
1756 .set_mode = qcom_qmp_phy_set_mode,
1757 .owner = THIS_MODULE,
1758};
1759
1760static
1761int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1762{
1763 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1764 struct phy *generic_phy;
1765 struct qmp_phy *qphy;
1766 char prop_name[MAX_PROP_NAME];
1767 int ret;
1768
1769 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1770 if (!qphy)
1771 return -ENOMEM;
1772
1773
1774
1775
1776
1777
1778
1779 qphy->tx = of_iomap(np, 0);
1780 if (!qphy->tx)
1781 return -ENOMEM;
1782
1783 qphy->rx = of_iomap(np, 1);
1784 if (!qphy->rx)
1785 return -ENOMEM;
1786
1787 qphy->pcs = of_iomap(np, 2);
1788 if (!qphy->pcs)
1789 return -ENOMEM;
1790
1791
1792
1793
1794
1795
1796
1797 if (qmp->cfg->is_dual_lane_phy) {
1798 qphy->tx2 = of_iomap(np, 3);
1799 qphy->rx2 = of_iomap(np, 4);
1800 if (!qphy->tx2 || !qphy->rx2) {
1801 dev_warn(dev,
1802 "Underspecified device tree, falling back to legacy register regions\n");
1803
1804
1805 qphy->pcs_misc = qphy->tx2;
1806 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
1807 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
1808
1809 } else {
1810 qphy->pcs_misc = of_iomap(np, 5);
1811 }
1812
1813 } else {
1814 qphy->pcs_misc = of_iomap(np, 3);
1815 }
1816
1817 if (!qphy->pcs_misc)
1818 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1819
1820
1821
1822
1823
1824
1825
1826
1827 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1828 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1829 if (IS_ERR(qphy->pipe_clk)) {
1830 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1831 qmp->cfg->type == PHY_TYPE_USB3) {
1832 ret = PTR_ERR(qphy->pipe_clk);
1833 if (ret != -EPROBE_DEFER)
1834 dev_err(dev,
1835 "failed to get lane%d pipe_clk, %d\n",
1836 id, ret);
1837 return ret;
1838 }
1839 qphy->pipe_clk = NULL;
1840 }
1841
1842
1843 if (qmp->cfg->has_lane_rst) {
1844 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1845 qphy->lane_rst = of_reset_control_get(np, prop_name);
1846 if (IS_ERR(qphy->lane_rst)) {
1847 dev_err(dev, "failed to get lane%d reset\n", id);
1848 return PTR_ERR(qphy->lane_rst);
1849 }
1850 }
1851
1852 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
1853 if (IS_ERR(generic_phy)) {
1854 ret = PTR_ERR(generic_phy);
1855 dev_err(dev, "failed to create qphy %d\n", ret);
1856 return ret;
1857 }
1858
1859 qphy->phy = generic_phy;
1860 qphy->index = id;
1861 qphy->qmp = qmp;
1862 qmp->phys[id] = qphy;
1863 phy_set_drvdata(generic_phy, qphy);
1864
1865 return 0;
1866}
1867
1868static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1869 {
1870 .compatible = "qcom,msm8996-qmp-pcie-phy",
1871 .data = &msm8996_pciephy_cfg,
1872 }, {
1873 .compatible = "qcom,msm8996-qmp-usb3-phy",
1874 .data = &msm8996_usb3phy_cfg,
1875 }, {
1876 .compatible = "qcom,msm8998-qmp-ufs-phy",
1877 .data = &sdm845_ufsphy_cfg,
1878 }, {
1879 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1880 .data = &ipq8074_pciephy_cfg,
1881 }, {
1882 .compatible = "qcom,sdm845-qmp-usb3-phy",
1883 .data = &qmp_v3_usb3phy_cfg,
1884 }, {
1885 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
1886 .data = &qmp_v3_usb3_uniphy_cfg,
1887 }, {
1888 .compatible = "qcom,sdm845-qmp-ufs-phy",
1889 .data = &sdm845_ufsphy_cfg,
1890 }, {
1891 .compatible = "qcom,msm8998-qmp-usb3-phy",
1892 .data = &msm8998_usb3phy_cfg,
1893 },
1894 { },
1895};
1896MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
1897
1898static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
1899 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
1900 qcom_qmp_phy_runtime_resume, NULL)
1901};
1902
1903static int qcom_qmp_phy_probe(struct platform_device *pdev)
1904{
1905 struct qcom_qmp *qmp;
1906 struct device *dev = &pdev->dev;
1907 struct resource *res;
1908 struct device_node *child;
1909 struct phy_provider *phy_provider;
1910 void __iomem *base;
1911 int num, id;
1912 int ret;
1913
1914 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1915 if (!qmp)
1916 return -ENOMEM;
1917
1918 qmp->dev = dev;
1919 dev_set_drvdata(dev, qmp);
1920
1921
1922 qmp->cfg = of_device_get_match_data(dev);
1923 if (!qmp->cfg)
1924 return -EINVAL;
1925
1926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1927 base = devm_ioremap_resource(dev, res);
1928 if (IS_ERR(base))
1929 return PTR_ERR(base);
1930
1931
1932 qmp->serdes = base;
1933
1934
1935 if (qmp->cfg->has_phy_dp_com_ctrl) {
1936 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1937 "dp_com");
1938 base = devm_ioremap_resource(dev, res);
1939 if (IS_ERR(base))
1940 return PTR_ERR(base);
1941
1942 qmp->dp_com = base;
1943 }
1944
1945 mutex_init(&qmp->phy_mutex);
1946
1947 ret = qcom_qmp_phy_clk_init(dev);
1948 if (ret)
1949 return ret;
1950
1951 ret = qcom_qmp_phy_reset_init(dev);
1952 if (ret)
1953 return ret;
1954
1955 ret = qcom_qmp_phy_vreg_init(dev);
1956 if (ret) {
1957 if (ret != -EPROBE_DEFER)
1958 dev_err(dev, "failed to get regulator supplies: %d\n",
1959 ret);
1960 return ret;
1961 }
1962
1963 num = of_get_available_child_count(dev->of_node);
1964
1965 if (num > qmp->cfg->nlanes)
1966 return -EINVAL;
1967
1968 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
1969 if (!qmp->phys)
1970 return -ENOMEM;
1971
1972 id = 0;
1973 pm_runtime_set_active(dev);
1974 pm_runtime_enable(dev);
1975
1976
1977
1978
1979 pm_runtime_forbid(dev);
1980
1981 for_each_available_child_of_node(dev->of_node, child) {
1982
1983 ret = qcom_qmp_phy_create(dev, child, id);
1984 if (ret) {
1985 dev_err(dev, "failed to create lane%d phy, %d\n",
1986 id, ret);
1987 pm_runtime_disable(dev);
1988 return ret;
1989 }
1990
1991
1992
1993
1994
1995 ret = phy_pipe_clk_register(qmp, child);
1996 if (ret) {
1997 dev_err(qmp->dev,
1998 "failed to register pipe clock source\n");
1999 pm_runtime_disable(dev);
2000 return ret;
2001 }
2002 id++;
2003 }
2004
2005 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2006 if (!IS_ERR(phy_provider))
2007 dev_info(dev, "Registered Qcom-QMP phy\n");
2008 else
2009 pm_runtime_disable(dev);
2010
2011 return PTR_ERR_OR_ZERO(phy_provider);
2012}
2013
2014static struct platform_driver qcom_qmp_phy_driver = {
2015 .probe = qcom_qmp_phy_probe,
2016 .driver = {
2017 .name = "qcom-qmp-phy",
2018 .pm = &qcom_qmp_phy_pm_ops,
2019 .of_match_table = qcom_qmp_phy_of_match_table,
2020 },
2021};
2022
2023module_platform_driver(qcom_qmp_phy_driver);
2024
2025MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2026MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2027MODULE_LICENSE("GPL v2");
2028
