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12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/acpi.h>
15#include <linux/bitfield.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/dmi.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/uaccess.h>
23
24#include <asm/cpu_device_id.h>
25#include <asm/intel-family.h>
26#include <asm/msr.h>
27
28#include "intel_pmc_core.h"
29
30static struct pmc_dev pmc;
31
32
33static const struct pmc_bit_map msr_map[] = {
34 {"Package C2", MSR_PKG_C2_RESIDENCY},
35 {"Package C3", MSR_PKG_C3_RESIDENCY},
36 {"Package C6", MSR_PKG_C6_RESIDENCY},
37 {"Package C7", MSR_PKG_C7_RESIDENCY},
38 {"Package C8", MSR_PKG_C8_RESIDENCY},
39 {"Package C9", MSR_PKG_C9_RESIDENCY},
40 {"Package C10", MSR_PKG_C10_RESIDENCY},
41 {}
42};
43
44static const struct pmc_bit_map spt_pll_map[] = {
45 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
46 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
47 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
48 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
49 {},
50};
51
52static const struct pmc_bit_map spt_mphy_map[] = {
53 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
54 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
55 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
56 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
57 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
58 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
59 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
60 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
61 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
62 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
63 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
64 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
65 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
66 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
67 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
68 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
69 {},
70};
71
72static const struct pmc_bit_map spt_pfear_map[] = {
73 {"PMC", SPT_PMC_BIT_PMC},
74 {"OPI-DMI", SPT_PMC_BIT_OPI},
75 {"SPI / eSPI", SPT_PMC_BIT_SPI},
76 {"XHCI", SPT_PMC_BIT_XHCI},
77 {"SPA", SPT_PMC_BIT_SPA},
78 {"SPB", SPT_PMC_BIT_SPB},
79 {"SPC", SPT_PMC_BIT_SPC},
80 {"GBE", SPT_PMC_BIT_GBE},
81 {"SATA", SPT_PMC_BIT_SATA},
82 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
83 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
84 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
85 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
86 {"RSVD", SPT_PMC_BIT_RSVD_0B},
87 {"LPSS", SPT_PMC_BIT_LPSS},
88 {"LPC", SPT_PMC_BIT_LPC},
89 {"SMB", SPT_PMC_BIT_SMB},
90 {"ISH", SPT_PMC_BIT_ISH},
91 {"P2SB", SPT_PMC_BIT_P2SB},
92 {"DFX", SPT_PMC_BIT_DFX},
93 {"SCC", SPT_PMC_BIT_SCC},
94 {"RSVD", SPT_PMC_BIT_RSVD_0C},
95 {"FUSE", SPT_PMC_BIT_FUSE},
96 {"CAMERA", SPT_PMC_BIT_CAMREA},
97 {"RSVD", SPT_PMC_BIT_RSVD_0D},
98 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
99 {"EXI", SPT_PMC_BIT_EXI},
100 {"CSE", SPT_PMC_BIT_CSE},
101 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
102 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
103 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
104 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
105 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
106 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
107 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
108 {"RSVD", SPT_PMC_BIT_RSVD_1A},
109 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
110 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
111 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
112 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
113 {},
114};
115
116static const struct pmc_bit_map spt_ltr_show_map[] = {
117 {"SOUTHPORT_A", SPT_PMC_LTR_SPA},
118 {"SOUTHPORT_B", SPT_PMC_LTR_SPB},
119 {"SATA", SPT_PMC_LTR_SATA},
120 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
121 {"XHCI", SPT_PMC_LTR_XHCI},
122 {"Reserved", SPT_PMC_LTR_RESERVED},
123 {"ME", SPT_PMC_LTR_ME},
124
125 {"EVA", SPT_PMC_LTR_EVA},
126 {"SOUTHPORT_C", SPT_PMC_LTR_SPC},
127 {"HD_AUDIO", SPT_PMC_LTR_AZ},
128 {"LPSS", SPT_PMC_LTR_LPSS},
129 {"SOUTHPORT_D", SPT_PMC_LTR_SPD},
130 {"SOUTHPORT_E", SPT_PMC_LTR_SPE},
131 {"CAMERA", SPT_PMC_LTR_CAM},
132 {"ESPI", SPT_PMC_LTR_ESPI},
133 {"SCC", SPT_PMC_LTR_SCC},
134 {"ISH", SPT_PMC_LTR_ISH},
135
136 {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
137 {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
138 {}
139};
140
141static const struct pmc_reg_map spt_reg_map = {
142 .pfear_sts = spt_pfear_map,
143 .mphy_sts = spt_mphy_map,
144 .pll_sts = spt_pll_map,
145 .ltr_show_sts = spt_ltr_show_map,
146 .msr_sts = msr_map,
147 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
148 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
149 .regmap_length = SPT_PMC_MMIO_REG_LEN,
150 .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
151 .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
152 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
153 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
154 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
155 .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
156};
157
158
159static const struct pmc_bit_map cnp_pfear_map[] = {
160 {"PMC", BIT(0)},
161 {"OPI-DMI", BIT(1)},
162 {"SPI/eSPI", BIT(2)},
163 {"XHCI", BIT(3)},
164 {"SPA", BIT(4)},
165 {"SPB", BIT(5)},
166 {"SPC", BIT(6)},
167 {"GBE", BIT(7)},
168
169 {"SATA", BIT(0)},
170 {"HDA_PGD0", BIT(1)},
171 {"HDA_PGD1", BIT(2)},
172 {"HDA_PGD2", BIT(3)},
173 {"HDA_PGD3", BIT(4)},
174 {"SPD", BIT(5)},
175 {"LPSS", BIT(6)},
176 {"LPC", BIT(7)},
177
178 {"SMB", BIT(0)},
179 {"ISH", BIT(1)},
180 {"P2SB", BIT(2)},
181 {"NPK_VNN", BIT(3)},
182 {"SDX", BIT(4)},
183 {"SPE", BIT(5)},
184 {"Fuse", BIT(6)},
185
186 {"SBR8", BIT(7)},
187
188 {"CSME_FSC", BIT(0)},
189 {"USB3_OTG", BIT(1)},
190 {"EXI", BIT(2)},
191 {"CSE", BIT(3)},
192 {"CSME_KVM", BIT(4)},
193 {"CSME_PMT", BIT(5)},
194 {"CSME_CLINK", BIT(6)},
195 {"CSME_PTIO", BIT(7)},
196
197 {"CSME_USBR", BIT(0)},
198 {"CSME_SUSRAM", BIT(1)},
199 {"CSME_SMT1", BIT(2)},
200 {"CSME_SMT4", BIT(3)},
201 {"CSME_SMS2", BIT(4)},
202 {"CSME_SMS1", BIT(5)},
203 {"CSME_RTC", BIT(6)},
204 {"CSME_PSF", BIT(7)},
205
206 {"SBR0", BIT(0)},
207 {"SBR1", BIT(1)},
208 {"SBR2", BIT(2)},
209 {"SBR3", BIT(3)},
210 {"SBR4", BIT(4)},
211 {"SBR5", BIT(5)},
212 {"CSME_PECI", BIT(6)},
213 {"PSF1", BIT(7)},
214
215 {"PSF2", BIT(0)},
216 {"PSF3", BIT(1)},
217 {"PSF4", BIT(2)},
218 {"CNVI", BIT(3)},
219 {"UFS0", BIT(4)},
220 {"EMMC", BIT(5)},
221 {"SPF", BIT(6)},
222 {"SBR6", BIT(7)},
223
224 {"SBR7", BIT(0)},
225 {"NPK_AON", BIT(1)},
226 {"HDA_PGD4", BIT(2)},
227 {"HDA_PGD5", BIT(3)},
228 {"HDA_PGD6", BIT(4)},
229
230 {"PSF6", BIT(5)},
231 {"PSF7", BIT(6)},
232 {"PSF8", BIT(7)},
233
234
235 {"RES_65", BIT(0)},
236 {"RES_66", BIT(1)},
237 {"RES_67", BIT(2)},
238 {"TAM", BIT(3)},
239 {"GBETSN", BIT(4)},
240 {"TBTLSX", BIT(5)},
241 {"RES_71", BIT(6)},
242 {"RES_72", BIT(7)},
243 {}
244};
245
246static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
247 {"AUDIO_D3", BIT(0)},
248 {"OTG_D3", BIT(1)},
249 {"XHCI_D3", BIT(2)},
250 {"LPIO_D3", BIT(3)},
251 {"SDX_D3", BIT(4)},
252 {"SATA_D3", BIT(5)},
253 {"UFS0_D3", BIT(6)},
254 {"UFS1_D3", BIT(7)},
255 {"EMMC_D3", BIT(8)},
256 {}
257};
258
259static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
260 {"SDIO_PLL_OFF", BIT(0)},
261 {"USB2_PLL_OFF", BIT(1)},
262 {"AUDIO_PLL_OFF", BIT(2)},
263 {"OC_PLL_OFF", BIT(3)},
264 {"MAIN_PLL_OFF", BIT(4)},
265 {"XOSC_OFF", BIT(5)},
266 {"LPC_CLKS_GATED", BIT(6)},
267 {"PCIE_CLKREQS_IDLE", BIT(7)},
268 {"AUDIO_ROSC_OFF", BIT(8)},
269 {"HPET_XOSC_CLK_REQ", BIT(9)},
270 {"PMC_ROSC_SLOW_CLK", BIT(10)},
271 {"AON2_ROSC_GATED", BIT(11)},
272 {"CLKACKS_DEASSERTED", BIT(12)},
273 {}
274};
275
276static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
277 {"MPHY_CORE_GATED", BIT(0)},
278 {"CSME_GATED", BIT(1)},
279 {"USB2_SUS_GATED", BIT(2)},
280 {"DYN_FLEX_IO_IDLE", BIT(3)},
281 {"GBE_NO_LINK", BIT(4)},
282 {"THERM_SEN_DISABLED", BIT(5)},
283 {"PCIE_LOW_POWER", BIT(6)},
284 {"ISH_VNNAON_REQ_ACT", BIT(7)},
285 {"ISH_VNN_REQ_ACT", BIT(8)},
286 {"CNV_VNNAON_REQ_ACT", BIT(9)},
287 {"CNV_VNN_REQ_ACT", BIT(10)},
288 {"NPK_VNNON_REQ_ACT", BIT(11)},
289 {"PMSYNC_STATE_IDLE", BIT(12)},
290 {"ALST_GT_THRES", BIT(13)},
291 {"PMC_ARC_PG_READY", BIT(14)},
292 {}
293};
294
295static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
296 cnp_slps0_dbg0_map,
297 cnp_slps0_dbg1_map,
298 cnp_slps0_dbg2_map,
299 NULL,
300};
301
302static const struct pmc_bit_map cnp_ltr_show_map[] = {
303 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
304 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
305 {"SATA", CNP_PMC_LTR_SATA},
306 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
307 {"XHCI", CNP_PMC_LTR_XHCI},
308 {"Reserved", CNP_PMC_LTR_RESERVED},
309 {"ME", CNP_PMC_LTR_ME},
310
311 {"EVA", CNP_PMC_LTR_EVA},
312 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
313 {"HD_AUDIO", CNP_PMC_LTR_AZ},
314 {"CNV", CNP_PMC_LTR_CNV},
315 {"LPSS", CNP_PMC_LTR_LPSS},
316 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
317 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
318 {"CAMERA", CNP_PMC_LTR_CAM},
319 {"ESPI", CNP_PMC_LTR_ESPI},
320 {"SCC", CNP_PMC_LTR_SCC},
321 {"ISH", CNP_PMC_LTR_ISH},
322 {"UFSX2", CNP_PMC_LTR_UFSX2},
323 {"EMMC", CNP_PMC_LTR_EMMC},
324
325 {"WIGIG", ICL_PMC_LTR_WIGIG},
326
327 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
328 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
329 {}
330};
331
332static const struct pmc_reg_map cnp_reg_map = {
333 .pfear_sts = cnp_pfear_map,
334 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
335 .slps0_dbg_maps = cnp_slps0_dbg_maps,
336 .ltr_show_sts = cnp_ltr_show_map,
337 .msr_sts = msr_map,
338 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
339 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
340 .regmap_length = CNP_PMC_MMIO_REG_LEN,
341 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
342 .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
343 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
344 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
345 .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
346};
347
348static const struct pmc_reg_map icl_reg_map = {
349 .pfear_sts = cnp_pfear_map,
350 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
351 .slps0_dbg_maps = cnp_slps0_dbg_maps,
352 .ltr_show_sts = cnp_ltr_show_map,
353 .msr_sts = msr_map,
354 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
355 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
356 .regmap_length = CNP_PMC_MMIO_REG_LEN,
357 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
358 .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
359 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
360 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
361 .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
362};
363
364static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
365{
366 return readb(pmcdev->regbase + offset);
367}
368
369static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
370{
371 return readl(pmcdev->regbase + reg_offset);
372}
373
374static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
375 reg_offset, u32 val)
376{
377 writel(val, pmcdev->regbase + reg_offset);
378}
379
380static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
381{
382 return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
383}
384
385static int pmc_core_dev_state_get(void *data, u64 *val)
386{
387 struct pmc_dev *pmcdev = data;
388 const struct pmc_reg_map *map = pmcdev->map;
389 u32 value;
390
391 value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
392 *val = pmc_core_adjust_slp_s0_step(value);
393
394 return 0;
395}
396
397DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
398
399static int pmc_core_check_read_lock_bit(void)
400{
401 struct pmc_dev *pmcdev = &pmc;
402 u32 value;
403
404 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
405 return value & BIT(pmcdev->map->pm_read_disable_bit);
406}
407
408#if IS_ENABLED(CONFIG_DEBUG_FS)
409static bool slps0_dbg_latch;
410
411static void pmc_core_display_map(struct seq_file *s, int index,
412 u8 pf_reg, const struct pmc_bit_map *pf_map)
413{
414 seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
415 index, pf_map[index].name,
416 pf_map[index].bit_mask & pf_reg ? "Off" : "On");
417}
418
419static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
420{
421 struct pmc_dev *pmcdev = s->private;
422 const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
423 u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
424 int index, iter;
425
426 iter = pmcdev->map->ppfear0_offset;
427
428 for (index = 0; index < pmcdev->map->ppfear_buckets &&
429 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
430 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
431
432 for (index = 0; map[index].name &&
433 index < pmcdev->map->ppfear_buckets * 8; index++)
434 pmc_core_display_map(s, index, pf_regs[index / 8], map);
435
436 return 0;
437}
438DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
439
440
441static int pmc_core_mtpmc_link_status(void)
442{
443 struct pmc_dev *pmcdev = &pmc;
444 u32 value;
445
446 value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
447 return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
448}
449
450static int pmc_core_send_msg(u32 *addr_xram)
451{
452 struct pmc_dev *pmcdev = &pmc;
453 u32 dest;
454 int timeout;
455
456 for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
457 if (pmc_core_mtpmc_link_status() == 0)
458 break;
459 msleep(5);
460 }
461
462 if (timeout <= 0 && pmc_core_mtpmc_link_status())
463 return -EBUSY;
464
465 dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
466 pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
467 return 0;
468}
469
470static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
471{
472 struct pmc_dev *pmcdev = s->private;
473 const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
474 u32 mphy_core_reg_low, mphy_core_reg_high;
475 u32 val_low, val_high;
476 int index, err = 0;
477
478 if (pmcdev->pmc_xram_read_bit) {
479 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
480 return 0;
481 }
482
483 mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
484 mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
485
486 mutex_lock(&pmcdev->lock);
487
488 if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
489 err = -EBUSY;
490 goto out_unlock;
491 }
492
493 msleep(10);
494 val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
495
496 if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
497 err = -EBUSY;
498 goto out_unlock;
499 }
500
501 msleep(10);
502 val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
503
504 for (index = 0; map[index].name && index < 8; index++) {
505 seq_printf(s, "%-32s\tState: %s\n",
506 map[index].name,
507 map[index].bit_mask & val_low ? "Not power gated" :
508 "Power gated");
509 }
510
511 for (index = 8; map[index].name; index++) {
512 seq_printf(s, "%-32s\tState: %s\n",
513 map[index].name,
514 map[index].bit_mask & val_high ? "Not power gated" :
515 "Power gated");
516 }
517
518out_unlock:
519 mutex_unlock(&pmcdev->lock);
520 return err;
521}
522DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
523
524static int pmc_core_pll_show(struct seq_file *s, void *unused)
525{
526 struct pmc_dev *pmcdev = s->private;
527 const struct pmc_bit_map *map = pmcdev->map->pll_sts;
528 u32 mphy_common_reg, val;
529 int index, err = 0;
530
531 if (pmcdev->pmc_xram_read_bit) {
532 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
533 return 0;
534 }
535
536 mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
537 mutex_lock(&pmcdev->lock);
538
539 if (pmc_core_send_msg(&mphy_common_reg) != 0) {
540 err = -EBUSY;
541 goto out_unlock;
542 }
543
544
545 msleep(10);
546 val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
547
548 for (index = 0; map[index].name ; index++) {
549 seq_printf(s, "%-32s\tState: %s\n",
550 map[index].name,
551 map[index].bit_mask & val ? "Active" : "Idle");
552 }
553
554out_unlock:
555 mutex_unlock(&pmcdev->lock);
556 return err;
557}
558DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
559
560static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
561*userbuf, size_t count, loff_t *ppos)
562{
563 struct pmc_dev *pmcdev = &pmc;
564 const struct pmc_reg_map *map = pmcdev->map;
565 u32 val, buf_size, fd;
566 int err = 0;
567
568 buf_size = count < 64 ? count : 64;
569 mutex_lock(&pmcdev->lock);
570
571 if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
572 err = -EFAULT;
573 goto out_unlock;
574 }
575
576 if (val > map->ltr_ignore_max) {
577 err = -EINVAL;
578 goto out_unlock;
579 }
580
581 fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
582 fd |= (1U << val);
583 pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
584
585out_unlock:
586 mutex_unlock(&pmcdev->lock);
587 return err == 0 ? count : err;
588}
589
590static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
591{
592 return 0;
593}
594
595static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
596{
597 return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
598}
599
600static const struct file_operations pmc_core_ltr_ignore_ops = {
601 .open = pmc_core_ltr_ignore_open,
602 .read = seq_read,
603 .write = pmc_core_ltr_ignore_write,
604 .llseek = seq_lseek,
605 .release = single_release,
606};
607
608static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
609{
610 const struct pmc_reg_map *map = pmcdev->map;
611 u32 fd;
612
613 mutex_lock(&pmcdev->lock);
614
615 if (!reset && !slps0_dbg_latch)
616 goto out_unlock;
617
618 fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
619 if (reset)
620 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
621 else
622 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
623 pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
624
625 slps0_dbg_latch = 0;
626
627out_unlock:
628 mutex_unlock(&pmcdev->lock);
629}
630
631static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
632{
633 struct pmc_dev *pmcdev = s->private;
634 const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
635 const struct pmc_bit_map *map;
636 int offset;
637 u32 data;
638
639 pmc_core_slps0_dbg_latch(pmcdev, false);
640 offset = pmcdev->map->slps0_dbg_offset;
641 while (*maps) {
642 map = *maps;
643 data = pmc_core_reg_read(pmcdev, offset);
644 offset += 4;
645 while (map->name) {
646 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
647 map->name,
648 data & map->bit_mask ?
649 "Yes" : "No");
650 ++map;
651 }
652 ++maps;
653 }
654 pmc_core_slps0_dbg_latch(pmcdev, true);
655 return 0;
656}
657DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
658
659static u32 convert_ltr_scale(u32 val)
660{
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685 if (val > 5) {
686 pr_warn("Invalid LTR scale factor.\n");
687 return 0;
688 }
689
690 return 1U << (5 * val);
691}
692
693static int pmc_core_ltr_show(struct seq_file *s, void *unused)
694{
695 struct pmc_dev *pmcdev = s->private;
696 const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
697 u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
698 u32 ltr_raw_data, scale, val;
699 u16 snoop_ltr, nonsnoop_ltr;
700 int index;
701
702 for (index = 0; map[index].name ; index++) {
703 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
704 ltr_raw_data = pmc_core_reg_read(pmcdev,
705 map[index].bit_mask);
706 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
707 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
708
709 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
710 scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
711 val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
712 decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
713 }
714
715 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
716 scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
717 val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
718 decoded_snoop_ltr = val * convert_ltr_scale(scale);
719 }
720
721 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
722 map[index].name, ltr_raw_data,
723 decoded_non_snoop_ltr,
724 decoded_snoop_ltr);
725 }
726 return 0;
727}
728DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
729
730static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
731{
732 struct pmc_dev *pmcdev = s->private;
733 const struct pmc_bit_map *map = pmcdev->map->msr_sts;
734 u64 pcstate_count;
735 int index;
736
737 for (index = 0; map[index].name ; index++) {
738 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
739 continue;
740
741 seq_printf(s, "%-8s : 0x%llx\n", map[index].name,
742 pcstate_count);
743 }
744
745 return 0;
746}
747DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
748
749static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
750{
751 debugfs_remove_recursive(pmcdev->dbgfs_dir);
752}
753
754static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
755{
756 struct dentry *dir;
757
758 dir = debugfs_create_dir("pmc_core", NULL);
759 if (!dir)
760 return -ENOMEM;
761
762 pmcdev->dbgfs_dir = dir;
763
764 debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
765 &pmc_core_dev_state);
766
767 debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
768 &pmc_core_ppfear_fops);
769
770 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
771 &pmc_core_ltr_ignore_ops);
772
773 debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
774
775 debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
776 &pmc_core_pkgc_fops);
777
778 if (pmcdev->map->pll_sts)
779 debugfs_create_file("pll_status", 0444, dir, pmcdev,
780 &pmc_core_pll_fops);
781
782 if (pmcdev->map->mphy_sts)
783 debugfs_create_file("mphy_core_lanes_power_gating_status",
784 0444, dir, pmcdev,
785 &pmc_core_mphy_pg_fops);
786
787 if (pmcdev->map->slps0_dbg_maps) {
788 debugfs_create_file("slp_s0_debug_status", 0444,
789 dir, pmcdev,
790 &pmc_core_slps0_dbg_fops);
791
792 debugfs_create_bool("slp_s0_dbg_latch", 0644,
793 dir, &slps0_dbg_latch);
794 }
795
796 return 0;
797}
798#else
799static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
800{
801 return 0;
802}
803
804static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
805{
806}
807#endif
808
809static const struct x86_cpu_id intel_pmc_core_ids[] = {
810 INTEL_CPU_FAM6(SKYLAKE_MOBILE, spt_reg_map),
811 INTEL_CPU_FAM6(SKYLAKE_DESKTOP, spt_reg_map),
812 INTEL_CPU_FAM6(KABYLAKE_MOBILE, spt_reg_map),
813 INTEL_CPU_FAM6(KABYLAKE_DESKTOP, spt_reg_map),
814 INTEL_CPU_FAM6(CANNONLAKE_MOBILE, cnp_reg_map),
815 INTEL_CPU_FAM6(ICELAKE_MOBILE, icl_reg_map),
816 {}
817};
818
819MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
820
821static const struct pci_device_id pmc_pci_ids[] = {
822 { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
823 { 0, },
824};
825
826
827
828
829
830
831int quirk_xtal_ignore(const struct dmi_system_id *id)
832{
833 struct pmc_dev *pmcdev = &pmc;
834 u32 value;
835
836 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
837
838 value |= SPT_PMC_VRIC1_XTALSDQDIS;
839
840 value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
841 pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
842 return 0;
843}
844
845static const struct dmi_system_id pmc_core_dmi_table[] = {
846 {
847 .callback = quirk_xtal_ignore,
848 .ident = "HP Elite x2 1013 G3",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
851 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
852 },
853 },
854 {}
855};
856
857static int __init pmc_core_probe(void)
858{
859 struct pmc_dev *pmcdev = &pmc;
860 const struct x86_cpu_id *cpu_id;
861 u64 slp_s0_addr;
862 int err;
863
864 cpu_id = x86_match_cpu(intel_pmc_core_ids);
865 if (!cpu_id)
866 return -ENODEV;
867
868 pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
869
870
871
872
873
874
875 if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
876 pmcdev->map = &cnp_reg_map;
877
878 if (lpit_read_residency_count_address(&slp_s0_addr))
879 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
880 else
881 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
882
883 pmcdev->regbase = ioremap(pmcdev->base_addr,
884 pmcdev->map->regmap_length);
885 if (!pmcdev->regbase)
886 return -ENOMEM;
887
888 mutex_init(&pmcdev->lock);
889 pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
890
891 err = pmc_core_dbgfs_register(pmcdev);
892 if (err < 0) {
893 pr_warn(" debugfs register failed.\n");
894 iounmap(pmcdev->regbase);
895 return err;
896 }
897
898 dmi_check_system(pmc_core_dmi_table);
899 pr_info(" initialized\n");
900 return 0;
901}
902module_init(pmc_core_probe)
903
904static void __exit pmc_core_remove(void)
905{
906 struct pmc_dev *pmcdev = &pmc;
907
908 pmc_core_dbgfs_unregister(pmcdev);
909 mutex_destroy(&pmcdev->lock);
910 iounmap(pmcdev->regbase);
911}
912module_exit(pmc_core_remove)
913
914MODULE_LICENSE("GPL v2");
915MODULE_DESCRIPTION("Intel PMC Core Driver");
916
