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33#include <linux/kernel.h>
34#include <linux/types.h>
35#include <linux/pci.h>
36#include <linux/list.h>
37#include <linux/moduleparam.h>
38#include <linux/module.h>
39#include <linux/spinlock.h>
40#include <linux/interrupt.h>
41#include <linux/delay.h>
42#include <linux/uio.h>
43#include <linux/uaccess.h>
44#include <linux/fs.h>
45#include <linux/compat.h>
46#include <linux/blkdev.h>
47#include <linux/poll.h>
48
49#include <scsi/scsi.h>
50#include <scsi/scsi_cmnd.h>
51#include <scsi/scsi_device.h>
52#include <scsi/scsi_host.h>
53
54#include "megaraid_sas_fusion.h"
55#include "megaraid_sas.h"
56#include <asm/div64.h>
57
58#define LB_PENDING_CMDS_DEFAULT 4
59static unsigned int lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
60module_param(lb_pending_cmds, int, S_IRUGO);
61MODULE_PARM_DESC(lb_pending_cmds, "Change raid-1 load balancing outstanding "
62 "threshold. Valid Values are 1-128. Default: 4");
63
64
65#define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
66#define MR_LD_STATE_OPTIMAL 3
67
68#define SPAN_ROW_SIZE(map, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowSize)
69#define SPAN_ROW_DATA_SIZE(map_, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize)
70#define SPAN_INVALID 0xff
71
72
73static void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
74 PLD_SPAN_INFO ldSpanInfo);
75static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
76 u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
77 struct RAID_CONTEXT *pRAID_Context, struct MR_DRV_RAID_MAP_ALL *map);
78static u64 get_row_from_strip(struct megasas_instance *instance, u32 ld,
79 u64 strip, struct MR_DRV_RAID_MAP_ALL *map);
80
81u32 mega_mod64(u64 dividend, u32 divisor)
82{
83 u64 d;
84 u32 remainder;
85
86 if (!divisor)
87 printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n");
88 d = dividend;
89 remainder = do_div(d, divisor);
90 return remainder;
91}
92
93
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96
97
98
99u64 mega_div64_32(uint64_t dividend, uint32_t divisor)
100{
101 u32 remainder;
102 u64 d;
103
104 if (!divisor)
105 printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n");
106
107 d = dividend;
108 remainder = do_div(d, divisor);
109
110 return d;
111}
112
113struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
114{
115 return &map->raidMap.ldSpanMap[ld].ldRaid;
116}
117
118static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld,
119 struct MR_DRV_RAID_MAP_ALL
120 *map)
121{
122 return &map->raidMap.ldSpanMap[ld].spanBlock[0];
123}
124
125static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_DRV_RAID_MAP_ALL *map)
126{
127 return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx];
128}
129
130u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map)
131{
132 return le16_to_cpu(map->raidMap.arMapInfo[ar].pd[arm]);
133}
134
135u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map)
136{
137 return le16_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef);
138}
139
140__le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
141{
142 return map->raidMap.devHndlInfo[pd].curDevHdl;
143}
144
145static u8 MR_PdInterfaceTypeGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
146{
147 return map->raidMap.devHndlInfo[pd].interfaceType;
148}
149
150u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
151{
152 return le16_to_cpu(map->raidMap.ldSpanMap[ld].ldRaid.targetId);
153}
154
155u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map)
156{
157 return map->raidMap.ldTgtIdToLd[ldTgtId];
158}
159
160static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span,
161 struct MR_DRV_RAID_MAP_ALL *map)
162{
163 return &map->raidMap.ldSpanMap[ld].spanBlock[span].span;
164}
165
166
167
168
169static int MR_PopulateDrvRaidMap(struct megasas_instance *instance, u64 map_id)
170{
171 struct fusion_context *fusion = instance->ctrl_context;
172 struct MR_FW_RAID_MAP_ALL *fw_map_old = NULL;
173 struct MR_FW_RAID_MAP *pFwRaidMap = NULL;
174 int i, j;
175 u16 ld_count;
176 struct MR_FW_RAID_MAP_DYNAMIC *fw_map_dyn;
177 struct MR_FW_RAID_MAP_EXT *fw_map_ext;
178 struct MR_RAID_MAP_DESC_TABLE *desc_table;
179
180
181 struct MR_DRV_RAID_MAP_ALL *drv_map =
182 fusion->ld_drv_map[(map_id & 1)];
183 struct MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap;
184 void *raid_map_data = NULL;
185
186 memset(drv_map, 0, fusion->drv_map_sz);
187 memset(pDrvRaidMap->ldTgtIdToLd,
188 0xff, (sizeof(u16) * MAX_LOGICAL_DRIVES_DYN));
189
190 if (instance->max_raid_mapsize) {
191 fw_map_dyn = fusion->ld_map[(map_id & 1)];
192 desc_table =
193 (struct MR_RAID_MAP_DESC_TABLE *)((void *)fw_map_dyn + le32_to_cpu(fw_map_dyn->desc_table_offset));
194 if (desc_table != fw_map_dyn->raid_map_desc_table)
195 dev_dbg(&instance->pdev->dev, "offsets of desc table are not matching desc %p original %p\n",
196 desc_table, fw_map_dyn->raid_map_desc_table);
197
198 ld_count = (u16)le16_to_cpu(fw_map_dyn->ld_count);
199 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
200 pDrvRaidMap->fpPdIoTimeoutSec =
201 fw_map_dyn->fp_pd_io_timeout_sec;
202 pDrvRaidMap->totalSize =
203 cpu_to_le32(sizeof(struct MR_DRV_RAID_MAP_ALL));
204
205 raid_map_data = (void *)fw_map_dyn +
206 le32_to_cpu(fw_map_dyn->desc_table_offset) +
207 le32_to_cpu(fw_map_dyn->desc_table_size);
208
209 for (i = 0; i < le32_to_cpu(fw_map_dyn->desc_table_num_elements); ++i) {
210 switch (le32_to_cpu(desc_table->raid_map_desc_type)) {
211 case RAID_MAP_DESC_TYPE_DEVHDL_INFO:
212 fw_map_dyn->dev_hndl_info =
213 (struct MR_DEV_HANDLE_INFO *)(raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
214 memcpy(pDrvRaidMap->devHndlInfo,
215 fw_map_dyn->dev_hndl_info,
216 sizeof(struct MR_DEV_HANDLE_INFO) *
217 le32_to_cpu(desc_table->raid_map_desc_elements));
218 break;
219 case RAID_MAP_DESC_TYPE_TGTID_INFO:
220 fw_map_dyn->ld_tgt_id_to_ld =
221 (u16 *)(raid_map_data +
222 le32_to_cpu(desc_table->raid_map_desc_offset));
223 for (j = 0; j < le32_to_cpu(desc_table->raid_map_desc_elements); j++) {
224 pDrvRaidMap->ldTgtIdToLd[j] =
225 le16_to_cpu(fw_map_dyn->ld_tgt_id_to_ld[j]);
226 }
227 break;
228 case RAID_MAP_DESC_TYPE_ARRAY_INFO:
229 fw_map_dyn->ar_map_info =
230 (struct MR_ARRAY_INFO *)
231 (raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
232 memcpy(pDrvRaidMap->arMapInfo,
233 fw_map_dyn->ar_map_info,
234 sizeof(struct MR_ARRAY_INFO) *
235 le32_to_cpu(desc_table->raid_map_desc_elements));
236 break;
237 case RAID_MAP_DESC_TYPE_SPAN_INFO:
238 fw_map_dyn->ld_span_map =
239 (struct MR_LD_SPAN_MAP *)
240 (raid_map_data +
241 le32_to_cpu(desc_table->raid_map_desc_offset));
242 memcpy(pDrvRaidMap->ldSpanMap,
243 fw_map_dyn->ld_span_map,
244 sizeof(struct MR_LD_SPAN_MAP) *
245 le32_to_cpu(desc_table->raid_map_desc_elements));
246 break;
247 default:
248 dev_dbg(&instance->pdev->dev, "wrong number of desctableElements %d\n",
249 fw_map_dyn->desc_table_num_elements);
250 }
251 ++desc_table;
252 }
253
254 } else if (instance->supportmax256vd) {
255 fw_map_ext =
256 (struct MR_FW_RAID_MAP_EXT *)fusion->ld_map[(map_id & 1)];
257 ld_count = (u16)le16_to_cpu(fw_map_ext->ldCount);
258 if (ld_count > MAX_LOGICAL_DRIVES_EXT) {
259 dev_dbg(&instance->pdev->dev, "megaraid_sas: LD count exposed in RAID map in not valid\n");
260 return 1;
261 }
262
263 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
264 pDrvRaidMap->fpPdIoTimeoutSec = fw_map_ext->fpPdIoTimeoutSec;
265 for (i = 0; i < (MAX_LOGICAL_DRIVES_EXT); i++)
266 pDrvRaidMap->ldTgtIdToLd[i] =
267 (u16)fw_map_ext->ldTgtIdToLd[i];
268 memcpy(pDrvRaidMap->ldSpanMap, fw_map_ext->ldSpanMap,
269 sizeof(struct MR_LD_SPAN_MAP) * ld_count);
270 memcpy(pDrvRaidMap->arMapInfo, fw_map_ext->arMapInfo,
271 sizeof(struct MR_ARRAY_INFO) * MAX_API_ARRAYS_EXT);
272 memcpy(pDrvRaidMap->devHndlInfo, fw_map_ext->devHndlInfo,
273 sizeof(struct MR_DEV_HANDLE_INFO) *
274 MAX_RAIDMAP_PHYSICAL_DEVICES);
275
276
277
278
279 pDrvRaidMap->totalSize =
280 cpu_to_le32(sizeof(struct MR_FW_RAID_MAP_EXT));
281 } else {
282 fw_map_old = (struct MR_FW_RAID_MAP_ALL *)
283 fusion->ld_map[(map_id & 1)];
284 pFwRaidMap = &fw_map_old->raidMap;
285 ld_count = (u16)le32_to_cpu(pFwRaidMap->ldCount);
286 if (ld_count > MAX_LOGICAL_DRIVES) {
287 dev_dbg(&instance->pdev->dev,
288 "LD count exposed in RAID map in not valid\n");
289 return 1;
290 }
291
292 pDrvRaidMap->totalSize = pFwRaidMap->totalSize;
293 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
294 pDrvRaidMap->fpPdIoTimeoutSec = pFwRaidMap->fpPdIoTimeoutSec;
295 for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++)
296 pDrvRaidMap->ldTgtIdToLd[i] =
297 (u8)pFwRaidMap->ldTgtIdToLd[i];
298 for (i = 0; i < ld_count; i++) {
299 pDrvRaidMap->ldSpanMap[i] = pFwRaidMap->ldSpanMap[i];
300 }
301 memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo,
302 sizeof(struct MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS);
303 memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo,
304 sizeof(struct MR_DEV_HANDLE_INFO) *
305 MAX_RAIDMAP_PHYSICAL_DEVICES);
306 }
307
308 return 0;
309}
310
311
312
313
314u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id)
315{
316 struct fusion_context *fusion;
317 struct MR_DRV_RAID_MAP_ALL *drv_map;
318 struct MR_DRV_RAID_MAP *pDrvRaidMap;
319 struct LD_LOAD_BALANCE_INFO *lbInfo;
320 PLD_SPAN_INFO ldSpanInfo;
321 struct MR_LD_RAID *raid;
322 u16 num_lds, i;
323 u16 ld;
324 u32 expected_size;
325
326 if (MR_PopulateDrvRaidMap(instance, map_id))
327 return 0;
328
329 fusion = instance->ctrl_context;
330 drv_map = fusion->ld_drv_map[(map_id & 1)];
331 pDrvRaidMap = &drv_map->raidMap;
332
333 lbInfo = fusion->load_balance_info;
334 ldSpanInfo = fusion->log_to_span;
335
336 if (instance->max_raid_mapsize)
337 expected_size = sizeof(struct MR_DRV_RAID_MAP_ALL);
338 else if (instance->supportmax256vd)
339 expected_size = sizeof(struct MR_FW_RAID_MAP_EXT);
340 else
341 expected_size =
342 (sizeof(struct MR_FW_RAID_MAP) - sizeof(struct MR_LD_SPAN_MAP) +
343 (sizeof(struct MR_LD_SPAN_MAP) * le16_to_cpu(pDrvRaidMap->ldCount)));
344
345 if (le32_to_cpu(pDrvRaidMap->totalSize) != expected_size) {
346 dev_dbg(&instance->pdev->dev, "megasas: map info structure size 0x%x",
347 le32_to_cpu(pDrvRaidMap->totalSize));
348 dev_dbg(&instance->pdev->dev, "is not matching expected size 0x%x\n",
349 (unsigned int)expected_size);
350 dev_err(&instance->pdev->dev, "megasas: span map %x, pDrvRaidMap->totalSize : %x\n",
351 (unsigned int)sizeof(struct MR_LD_SPAN_MAP),
352 le32_to_cpu(pDrvRaidMap->totalSize));
353 return 0;
354 }
355
356 if (instance->UnevenSpanSupport)
357 mr_update_span_set(drv_map, ldSpanInfo);
358
359 if (lbInfo)
360 mr_update_load_balance_params(drv_map, lbInfo);
361
362 num_lds = le16_to_cpu(drv_map->raidMap.ldCount);
363
364
365 for (i = 0; (num_lds > 0) && (i < MAX_LOGICAL_DRIVES_EXT); i++) {
366 ld = MR_TargetIdToLdGet(i, drv_map);
367
368
369 if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
370 continue;
371
372 raid = MR_LdRaidGet(ld, drv_map);
373 le32_to_cpus((u32 *)&raid->capability);
374
375 num_lds--;
376 }
377
378 return 1;
379}
380
381u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk,
382 struct MR_DRV_RAID_MAP_ALL *map)
383{
384 struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map);
385 struct MR_QUAD_ELEMENT *quad;
386 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
387 u32 span, j;
388
389 for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) {
390
391 for (j = 0; j < le32_to_cpu(pSpanBlock->block_span_info.noElements); j++) {
392 quad = &pSpanBlock->block_span_info.quad[j];
393
394 if (le32_to_cpu(quad->diff) == 0)
395 return SPAN_INVALID;
396 if (le64_to_cpu(quad->logStart) <= row && row <=
397 le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart),
398 le32_to_cpu(quad->diff))) == 0) {
399 if (span_blk != NULL) {
400 u64 blk, debugBlk;
401 blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff));
402 debugBlk = blk;
403
404 blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift;
405 *span_blk = blk;
406 }
407 return span;
408 }
409 }
410 }
411 return SPAN_INVALID;
412}
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431
432u32 mr_spanset_get_span_block(struct megasas_instance *instance,
433 u32 ld, u64 row, u64 *span_blk, struct MR_DRV_RAID_MAP_ALL *map)
434{
435 struct fusion_context *fusion = instance->ctrl_context;
436 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
437 LD_SPAN_SET *span_set;
438 struct MR_QUAD_ELEMENT *quad;
439 u32 span, info;
440 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
441
442 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
443 span_set = &(ldSpanInfo[ld].span_set[info]);
444
445 if (span_set->span_row_data_width == 0)
446 break;
447
448 if (row > span_set->data_row_end)
449 continue;
450
451 for (span = 0; span < raid->spanDepth; span++)
452 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
453 block_span_info.noElements) >= info+1) {
454 quad = &map->raidMap.ldSpanMap[ld].
455 spanBlock[span].
456 block_span_info.quad[info];
457 if (le32_to_cpu(quad->diff) == 0)
458 return SPAN_INVALID;
459 if (le64_to_cpu(quad->logStart) <= row &&
460 row <= le64_to_cpu(quad->logEnd) &&
461 (mega_mod64(row - le64_to_cpu(quad->logStart),
462 le32_to_cpu(quad->diff))) == 0) {
463 if (span_blk != NULL) {
464 u64 blk;
465 blk = mega_div64_32
466 ((row - le64_to_cpu(quad->logStart)),
467 le32_to_cpu(quad->diff));
468 blk = (blk + le64_to_cpu(quad->offsetInSpan))
469 << raid->stripeShift;
470 *span_blk = blk;
471 }
472 return span;
473 }
474 }
475 }
476 return SPAN_INVALID;
477}
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495static u64 get_row_from_strip(struct megasas_instance *instance,
496 u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
497{
498 struct fusion_context *fusion = instance->ctrl_context;
499 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
500 LD_SPAN_SET *span_set;
501 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
502 u32 info, strip_offset, span, span_offset;
503 u64 span_set_Strip, span_set_Row, retval;
504
505 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
506 span_set = &(ldSpanInfo[ld].span_set[info]);
507
508 if (span_set->span_row_data_width == 0)
509 break;
510 if (strip > span_set->data_strip_end)
511 continue;
512
513 span_set_Strip = strip - span_set->data_strip_start;
514 strip_offset = mega_mod64(span_set_Strip,
515 span_set->span_row_data_width);
516 span_set_Row = mega_div64_32(span_set_Strip,
517 span_set->span_row_data_width) * span_set->diff;
518 for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
519 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
520 block_span_info.noElements) >= info+1) {
521 if (strip_offset >=
522 span_set->strip_offset[span])
523 span_offset++;
524 else
525 break;
526 }
527
528 retval = (span_set->data_row_start + span_set_Row +
529 (span_offset - 1));
530 return retval;
531 }
532 return -1LLU;
533}
534
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552static u64 get_strip_from_row(struct megasas_instance *instance,
553 u32 ld, u64 row, struct MR_DRV_RAID_MAP_ALL *map)
554{
555 struct fusion_context *fusion = instance->ctrl_context;
556 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
557 LD_SPAN_SET *span_set;
558 struct MR_QUAD_ELEMENT *quad;
559 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
560 u32 span, info;
561 u64 strip;
562
563 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
564 span_set = &(ldSpanInfo[ld].span_set[info]);
565
566 if (span_set->span_row_data_width == 0)
567 break;
568 if (row > span_set->data_row_end)
569 continue;
570
571 for (span = 0; span < raid->spanDepth; span++)
572 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
573 block_span_info.noElements) >= info+1) {
574 quad = &map->raidMap.ldSpanMap[ld].
575 spanBlock[span].block_span_info.quad[info];
576 if (le64_to_cpu(quad->logStart) <= row &&
577 row <= le64_to_cpu(quad->logEnd) &&
578 mega_mod64((row - le64_to_cpu(quad->logStart)),
579 le32_to_cpu(quad->diff)) == 0) {
580 strip = mega_div64_32
581 (((row - span_set->data_row_start)
582 - le64_to_cpu(quad->logStart)),
583 le32_to_cpu(quad->diff));
584 strip *= span_set->span_row_data_width;
585 strip += span_set->data_strip_start;
586 strip += span_set->strip_offset[span];
587 return strip;
588 }
589 }
590 }
591 dev_err(&instance->pdev->dev, "get_strip_from_row"
592 "returns invalid strip for ld=%x, row=%lx\n",
593 ld, (long unsigned int)row);
594 return -1;
595}
596
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612
613static u32 get_arm_from_strip(struct megasas_instance *instance,
614 u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
615{
616 struct fusion_context *fusion = instance->ctrl_context;
617 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
618 LD_SPAN_SET *span_set;
619 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
620 u32 info, strip_offset, span, span_offset, retval;
621
622 for (info = 0 ; info < MAX_QUAD_DEPTH; info++) {
623 span_set = &(ldSpanInfo[ld].span_set[info]);
624
625 if (span_set->span_row_data_width == 0)
626 break;
627 if (strip > span_set->data_strip_end)
628 continue;
629
630 strip_offset = (uint)mega_mod64
631 ((strip - span_set->data_strip_start),
632 span_set->span_row_data_width);
633
634 for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
635 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
636 block_span_info.noElements) >= info+1) {
637 if (strip_offset >=
638 span_set->strip_offset[span])
639 span_offset =
640 span_set->strip_offset[span];
641 else
642 break;
643 }
644
645 retval = (strip_offset - span_offset);
646 return retval;
647 }
648
649 dev_err(&instance->pdev->dev, "get_arm_from_strip"
650 "returns invalid arm for ld=%x strip=%lx\n",
651 ld, (long unsigned int)strip);
652
653 return -1;
654}
655
656
657u8 get_arm(struct megasas_instance *instance, u32 ld, u8 span, u64 stripe,
658 struct MR_DRV_RAID_MAP_ALL *map)
659{
660 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
661
662 u32 arm = 0;
663
664 switch (raid->level) {
665 case 0:
666 case 5:
667 case 6:
668 arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span));
669 break;
670 case 1:
671
672 arm = get_arm_from_strip(instance, ld, stripe, map);
673 if (arm != -1U)
674 arm *= 2;
675 break;
676 }
677
678 return arm;
679}
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
700 u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
701 struct RAID_CONTEXT *pRAID_Context,
702 struct MR_DRV_RAID_MAP_ALL *map)
703{
704 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
705 u32 pd, arRef, r1_alt_pd;
706 u8 physArm, span;
707 u64 row;
708 u8 retval = true;
709 u64 *pdBlock = &io_info->pdBlock;
710 __le16 *pDevHandle = &io_info->devHandle;
711 u8 *pPdInterface = &io_info->pd_interface;
712 u32 logArm, rowMod, armQ, arm;
713 struct fusion_context *fusion;
714
715 fusion = instance->ctrl_context;
716 *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
717
718
719 row = io_info->start_row;
720 span = io_info->start_span;
721
722
723 if (raid->level == 6) {
724 logArm = get_arm_from_strip(instance, ld, stripRow, map);
725 if (logArm == -1U)
726 return false;
727 rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span));
728 armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod;
729 arm = armQ + 1 + logArm;
730 if (arm >= SPAN_ROW_SIZE(map, ld, span))
731 arm -= SPAN_ROW_SIZE(map, ld, span);
732 physArm = (u8)arm;
733 } else
734
735 physArm = get_arm(instance, ld, span, stripRow, map);
736 if (physArm == 0xFF)
737 return false;
738
739 arRef = MR_LdSpanArrayGet(ld, span, map);
740 pd = MR_ArPdGet(arRef, physArm, map);
741
742 if (pd != MR_PD_INVALID) {
743 *pDevHandle = MR_PdDevHandleGet(pd, map);
744 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
745
746 if ((instance->adapter_type >= VENTURA_SERIES) &&
747 (raid->level == 1) &&
748 !io_info->isRead) {
749 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
750 if (r1_alt_pd != MR_PD_INVALID)
751 io_info->r1_alt_dev_handle =
752 MR_PdDevHandleGet(r1_alt_pd, map);
753 }
754 } else {
755 if ((raid->level >= 5) &&
756 ((instance->adapter_type == THUNDERBOLT_SERIES) ||
757 ((instance->adapter_type == INVADER_SERIES) &&
758 (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
759 pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
760 else if (raid->level == 1) {
761 physArm = physArm + 1;
762 pd = MR_ArPdGet(arRef, physArm, map);
763 if (pd != MR_PD_INVALID) {
764 *pDevHandle = MR_PdDevHandleGet(pd, map);
765 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
766 }
767 }
768 }
769
770 *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
771 if (instance->adapter_type >= VENTURA_SERIES) {
772 ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
773 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
774 io_info->span_arm =
775 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
776 } else {
777 pRAID_Context->span_arm =
778 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
779 io_info->span_arm = pRAID_Context->span_arm;
780 }
781 io_info->pd_after_lb = pd;
782 return retval;
783}
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow,
803 u16 stripRef, struct IO_REQUEST_INFO *io_info,
804 struct RAID_CONTEXT *pRAID_Context,
805 struct MR_DRV_RAID_MAP_ALL *map)
806{
807 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
808 u32 pd, arRef, r1_alt_pd;
809 u8 physArm, span;
810 u64 row;
811 u8 retval = true;
812 u64 *pdBlock = &io_info->pdBlock;
813 __le16 *pDevHandle = &io_info->devHandle;
814 u8 *pPdInterface = &io_info->pd_interface;
815 struct fusion_context *fusion;
816
817 fusion = instance->ctrl_context;
818 *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
819
820 row = mega_div64_32(stripRow, raid->rowDataSize);
821
822 if (raid->level == 6) {
823
824 u32 logArm = mega_mod64(stripRow, raid->rowDataSize);
825 u32 rowMod, armQ, arm;
826
827 if (raid->rowSize == 0)
828 return false;
829
830 rowMod = mega_mod64(row, raid->rowSize);
831 armQ = raid->rowSize-1-rowMod;
832 arm = armQ+1+logArm;
833 if (arm >= raid->rowSize)
834 arm -= raid->rowSize;
835 physArm = (u8)arm;
836 } else {
837 if (raid->modFactor == 0)
838 return false;
839 physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow,
840 raid->modFactor),
841 map);
842 }
843
844 if (raid->spanDepth == 1) {
845 span = 0;
846 *pdBlock = row << raid->stripeShift;
847 } else {
848 span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map);
849 if (span == SPAN_INVALID)
850 return false;
851 }
852
853
854 arRef = MR_LdSpanArrayGet(ld, span, map);
855 pd = MR_ArPdGet(arRef, physArm, map);
856
857 if (pd != MR_PD_INVALID) {
858
859 *pDevHandle = MR_PdDevHandleGet(pd, map);
860 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
861
862 if ((instance->adapter_type >= VENTURA_SERIES) &&
863 (raid->level == 1) &&
864 !io_info->isRead) {
865 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
866 if (r1_alt_pd != MR_PD_INVALID)
867 io_info->r1_alt_dev_handle =
868 MR_PdDevHandleGet(r1_alt_pd, map);
869 }
870 } else {
871 if ((raid->level >= 5) &&
872 ((instance->adapter_type == THUNDERBOLT_SERIES) ||
873 ((instance->adapter_type == INVADER_SERIES) &&
874 (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
875 pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
876 else if (raid->level == 1) {
877
878 physArm = physArm + 1;
879 pd = MR_ArPdGet(arRef, physArm, map);
880 if (pd != MR_PD_INVALID) {
881
882 *pDevHandle = MR_PdDevHandleGet(pd, map);
883 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
884 }
885 }
886 }
887
888 *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
889 if (instance->adapter_type >= VENTURA_SERIES) {
890 ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
891 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
892 io_info->span_arm =
893 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
894 } else {
895 pRAID_Context->span_arm =
896 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
897 io_info->span_arm = pRAID_Context->span_arm;
898 }
899 io_info->pd_after_lb = pd;
900 return retval;
901}
902
903
904
905
906
907
908
909
910
911
912u8
913MR_BuildRaidContext(struct megasas_instance *instance,
914 struct IO_REQUEST_INFO *io_info,
915 struct RAID_CONTEXT *pRAID_Context,
916 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN)
917{
918 struct fusion_context *fusion;
919 struct MR_LD_RAID *raid;
920 u32 stripSize, stripe_mask;
921 u64 endLba, endStrip, endRow, start_row, start_strip;
922 u64 regStart;
923 u32 regSize;
924 u8 num_strips, numRows;
925 u16 ref_in_start_stripe, ref_in_end_stripe;
926 u64 ldStartBlock;
927 u32 numBlocks, ldTgtId;
928 u8 isRead;
929 u8 retval = 0;
930 u8 startlba_span = SPAN_INVALID;
931 u64 *pdBlock = &io_info->pdBlock;
932 u16 ld;
933
934 ldStartBlock = io_info->ldStartBlock;
935 numBlocks = io_info->numBlocks;
936 ldTgtId = io_info->ldTgtId;
937 isRead = io_info->isRead;
938 io_info->IoforUnevenSpan = 0;
939 io_info->start_span = SPAN_INVALID;
940 fusion = instance->ctrl_context;
941
942 ld = MR_TargetIdToLdGet(ldTgtId, map);
943 raid = MR_LdRaidGet(ld, map);
944
945 io_info->ra_capable = raid->capability.ra_capable;
946
947
948
949
950
951 if (raid->rowDataSize == 0) {
952 if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0)
953 return false;
954 else if (instance->UnevenSpanSupport) {
955 io_info->IoforUnevenSpan = 1;
956 } else {
957 dev_info(&instance->pdev->dev,
958 "raid->rowDataSize is 0, but has SPAN[0]"
959 "rowDataSize = 0x%0x,"
960 "but there is _NO_ UnevenSpanSupport\n",
961 MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize);
962 return false;
963 }
964 }
965
966 stripSize = 1 << raid->stripeShift;
967 stripe_mask = stripSize-1;
968
969
970
971
972
973 start_strip = ldStartBlock >> raid->stripeShift;
974 ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask);
975 endLba = ldStartBlock + numBlocks - 1;
976 ref_in_end_stripe = (u16)(endLba & stripe_mask);
977 endStrip = endLba >> raid->stripeShift;
978 num_strips = (u8)(endStrip - start_strip + 1);
979
980 if (io_info->IoforUnevenSpan) {
981 start_row = get_row_from_strip(instance, ld, start_strip, map);
982 endRow = get_row_from_strip(instance, ld, endStrip, map);
983 if (start_row == -1ULL || endRow == -1ULL) {
984 dev_info(&instance->pdev->dev, "return from %s %d."
985 "Send IO w/o region lock.\n",
986 __func__, __LINE__);
987 return false;
988 }
989
990 if (raid->spanDepth == 1) {
991 startlba_span = 0;
992 *pdBlock = start_row << raid->stripeShift;
993 } else
994 startlba_span = (u8)mr_spanset_get_span_block(instance,
995 ld, start_row, pdBlock, map);
996 if (startlba_span == SPAN_INVALID) {
997 dev_info(&instance->pdev->dev, "return from %s %d"
998 "for row 0x%llx,start strip %llx"
999 "endSrip %llx\n", __func__, __LINE__,
1000 (unsigned long long)start_row,
1001 (unsigned long long)start_strip,
1002 (unsigned long long)endStrip);
1003 return false;
1004 }
1005 io_info->start_span = startlba_span;
1006 io_info->start_row = start_row;
1007 } else {
1008 start_row = mega_div64_32(start_strip, raid->rowDataSize);
1009 endRow = mega_div64_32(endStrip, raid->rowDataSize);
1010 }
1011 numRows = (u8)(endRow - start_row + 1);
1012
1013
1014
1015
1016
1017
1018 regStart = start_row << raid->stripeShift;
1019
1020 regSize = stripSize;
1021
1022 io_info->do_fp_rlbypass = raid->capability.fpBypassRegionLock;
1023
1024
1025 if (raid->capability.fpCapable) {
1026 if (isRead)
1027 io_info->fpOkForIo = (raid->capability.fpReadCapable &&
1028 ((num_strips == 1) ||
1029 raid->capability.
1030 fpReadAcrossStripe));
1031 else
1032 io_info->fpOkForIo = (raid->capability.fpWriteCapable &&
1033 ((num_strips == 1) ||
1034 raid->capability.
1035 fpWriteAcrossStripe));
1036 } else
1037 io_info->fpOkForIo = false;
1038
1039 if (numRows == 1) {
1040
1041 if (num_strips == 1) {
1042 regStart += ref_in_start_stripe;
1043 regSize = numBlocks;
1044 }
1045
1046 } else if (io_info->IoforUnevenSpan == 0) {
1047
1048
1049
1050
1051 if (start_strip == (start_row + 1) * raid->rowDataSize - 1) {
1052 regStart += ref_in_start_stripe;
1053
1054
1055 regSize = stripSize - ref_in_start_stripe;
1056 }
1057
1058
1059 if (numRows > 2)
1060 regSize += (numRows-2) << raid->stripeShift;
1061
1062
1063 if (endStrip == endRow*raid->rowDataSize)
1064 regSize += ref_in_end_stripe+1;
1065 else
1066 regSize += stripSize;
1067 } else {
1068
1069
1070
1071
1072 if (start_strip == (get_strip_from_row(instance, ld, start_row, map) +
1073 SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) {
1074 regStart += ref_in_start_stripe;
1075
1076
1077
1078 regSize = stripSize - ref_in_start_stripe;
1079 }
1080
1081
1082 if (numRows > 2)
1083
1084 regSize += (numRows-2) << raid->stripeShift;
1085
1086
1087 if (endStrip == get_strip_from_row(instance, ld, endRow, map))
1088 regSize += ref_in_end_stripe + 1;
1089 else
1090 regSize += stripSize;
1091 }
1092
1093 pRAID_Context->timeout_value =
1094 cpu_to_le16(raid->fpIoTimeoutForLd ?
1095 raid->fpIoTimeoutForLd :
1096 map->raidMap.fpPdIoTimeoutSec);
1097 if (instance->adapter_type == INVADER_SERIES)
1098 pRAID_Context->reg_lock_flags = (isRead) ?
1099 raid->regTypeReqOnRead : raid->regTypeReqOnWrite;
1100 else if (instance->adapter_type == THUNDERBOLT_SERIES)
1101 pRAID_Context->reg_lock_flags = (isRead) ?
1102 REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite;
1103 pRAID_Context->virtual_disk_tgt_id = raid->targetId;
1104 pRAID_Context->reg_lock_row_lba = cpu_to_le64(regStart);
1105 pRAID_Context->reg_lock_length = cpu_to_le32(regSize);
1106 pRAID_Context->config_seq_num = raid->seqNum;
1107
1108 *raidLUN = raid->LUN;
1109
1110
1111
1112
1113 if (io_info->fpOkForIo) {
1114 retval = io_info->IoforUnevenSpan ?
1115 mr_spanset_get_phy_params(instance, ld,
1116 start_strip, ref_in_start_stripe,
1117 io_info, pRAID_Context, map) :
1118 MR_GetPhyParams(instance, ld, start_strip,
1119 ref_in_start_stripe, io_info,
1120 pRAID_Context, map);
1121
1122 if (io_info->devHandle == MR_DEVHANDLE_INVALID)
1123 io_info->fpOkForIo = false;
1124 return retval;
1125 } else if (isRead) {
1126 uint stripIdx;
1127 for (stripIdx = 0; stripIdx < num_strips; stripIdx++) {
1128 retval = io_info->IoforUnevenSpan ?
1129 mr_spanset_get_phy_params(instance, ld,
1130 start_strip + stripIdx,
1131 ref_in_start_stripe, io_info,
1132 pRAID_Context, map) :
1133 MR_GetPhyParams(instance, ld,
1134 start_strip + stripIdx, ref_in_start_stripe,
1135 io_info, pRAID_Context, map);
1136 if (!retval)
1137 return true;
1138 }
1139 }
1140 return true;
1141}
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
1155 PLD_SPAN_INFO ldSpanInfo)
1156{
1157 u8 span, count;
1158 u32 element, span_row_width;
1159 u64 span_row;
1160 struct MR_LD_RAID *raid;
1161 LD_SPAN_SET *span_set, *span_set_prev;
1162 struct MR_QUAD_ELEMENT *quad;
1163 int ldCount;
1164 u16 ld;
1165
1166
1167 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1168 ld = MR_TargetIdToLdGet(ldCount, map);
1169 if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
1170 continue;
1171 raid = MR_LdRaidGet(ld, map);
1172 for (element = 0; element < MAX_QUAD_DEPTH; element++) {
1173 for (span = 0; span < raid->spanDepth; span++) {
1174 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
1175 block_span_info.noElements) <
1176 element + 1)
1177 continue;
1178 span_set = &(ldSpanInfo[ld].span_set[element]);
1179 quad = &map->raidMap.ldSpanMap[ld].
1180 spanBlock[span].block_span_info.
1181 quad[element];
1182
1183 span_set->diff = le32_to_cpu(quad->diff);
1184
1185 for (count = 0, span_row_width = 0;
1186 count < raid->spanDepth; count++) {
1187 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].
1188 spanBlock[count].
1189 block_span_info.
1190 noElements) >= element + 1) {
1191 span_set->strip_offset[count] =
1192 span_row_width;
1193 span_row_width +=
1194 MR_LdSpanPtrGet
1195 (ld, count, map)->spanRowDataSize;
1196 }
1197 }
1198
1199 span_set->span_row_data_width = span_row_width;
1200 span_row = mega_div64_32(((le64_to_cpu(quad->logEnd) -
1201 le64_to_cpu(quad->logStart)) + le32_to_cpu(quad->diff)),
1202 le32_to_cpu(quad->diff));
1203
1204 if (element == 0) {
1205 span_set->log_start_lba = 0;
1206 span_set->log_end_lba =
1207 ((span_row << raid->stripeShift)
1208 * span_row_width) - 1;
1209
1210 span_set->span_row_start = 0;
1211 span_set->span_row_end = span_row - 1;
1212
1213 span_set->data_strip_start = 0;
1214 span_set->data_strip_end =
1215 (span_row * span_row_width) - 1;
1216
1217 span_set->data_row_start = 0;
1218 span_set->data_row_end =
1219 (span_row * le32_to_cpu(quad->diff)) - 1;
1220 } else {
1221 span_set_prev = &(ldSpanInfo[ld].
1222 span_set[element - 1]);
1223 span_set->log_start_lba =
1224 span_set_prev->log_end_lba + 1;
1225 span_set->log_end_lba =
1226 span_set->log_start_lba +
1227 ((span_row << raid->stripeShift)
1228 * span_row_width) - 1;
1229
1230 span_set->span_row_start =
1231 span_set_prev->span_row_end + 1;
1232 span_set->span_row_end =
1233 span_set->span_row_start + span_row - 1;
1234
1235 span_set->data_strip_start =
1236 span_set_prev->data_strip_end + 1;
1237 span_set->data_strip_end =
1238 span_set->data_strip_start +
1239 (span_row * span_row_width) - 1;
1240
1241 span_set->data_row_start =
1242 span_set_prev->data_row_end + 1;
1243 span_set->data_row_end =
1244 span_set->data_row_start +
1245 (span_row * le32_to_cpu(quad->diff)) - 1;
1246 }
1247 break;
1248 }
1249 if (span == raid->spanDepth)
1250 break;
1251 }
1252 }
1253}
1254
1255void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *drv_map,
1256 struct LD_LOAD_BALANCE_INFO *lbInfo)
1257{
1258 int ldCount;
1259 u16 ld;
1260 struct MR_LD_RAID *raid;
1261
1262 if (lb_pending_cmds > 128 || lb_pending_cmds < 1)
1263 lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
1264
1265 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1266 ld = MR_TargetIdToLdGet(ldCount, drv_map);
1267 if (ld >= MAX_LOGICAL_DRIVES_EXT - 1) {
1268 lbInfo[ldCount].loadBalanceFlag = 0;
1269 continue;
1270 }
1271
1272 raid = MR_LdRaidGet(ld, drv_map);
1273 if ((raid->level != 1) ||
1274 (raid->ldState != MR_LD_STATE_OPTIMAL)) {
1275 lbInfo[ldCount].loadBalanceFlag = 0;
1276 continue;
1277 }
1278 lbInfo[ldCount].loadBalanceFlag = 1;
1279 }
1280}
1281
1282u8 megasas_get_best_arm_pd(struct megasas_instance *instance,
1283 struct LD_LOAD_BALANCE_INFO *lbInfo,
1284 struct IO_REQUEST_INFO *io_info,
1285 struct MR_DRV_RAID_MAP_ALL *drv_map)
1286{
1287 struct MR_LD_RAID *raid;
1288 u16 pd1_dev_handle;
1289 u16 pend0, pend1, ld;
1290 u64 diff0, diff1;
1291 u8 bestArm, pd0, pd1, span, arm;
1292 u32 arRef, span_row_size;
1293
1294 u64 block = io_info->ldStartBlock;
1295 u32 count = io_info->numBlocks;
1296
1297 span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK)
1298 >> RAID_CTX_SPANARM_SPAN_SHIFT);
1299 arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK);
1300
1301 ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map);
1302 raid = MR_LdRaidGet(ld, drv_map);
1303 span_row_size = instance->UnevenSpanSupport ?
1304 SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize;
1305
1306 arRef = MR_LdSpanArrayGet(ld, span, drv_map);
1307 pd0 = MR_ArPdGet(arRef, arm, drv_map);
1308 pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ?
1309 (arm + 1 - span_row_size) : arm + 1, drv_map);
1310
1311
1312
1313 pd1_dev_handle = MR_PdDevHandleGet(pd1, drv_map);
1314
1315 if (pd1_dev_handle == MR_DEVHANDLE_INVALID) {
1316 bestArm = arm;
1317 } else {
1318
1319 pend0 = atomic_read(&lbInfo->scsi_pending_cmds[pd0]);
1320 pend1 = atomic_read(&lbInfo->scsi_pending_cmds[pd1]);
1321
1322
1323 diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]);
1324 diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]);
1325 bestArm = (diff0 <= diff1 ? arm : arm ^ 1);
1326
1327
1328
1329
1330 if ((bestArm == arm && pend0 > pend1 + lb_pending_cmds) ||
1331 (bestArm != arm && pend1 > pend0 + lb_pending_cmds))
1332 bestArm ^= 1;
1333
1334
1335 io_info->span_arm =
1336 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm;
1337 io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1;
1338 }
1339
1340 lbInfo->last_accessed_block[io_info->pd_after_lb] = block + count - 1;
1341 return io_info->pd_after_lb;
1342}
1343
1344__le16 get_updated_dev_handle(struct megasas_instance *instance,
1345 struct LD_LOAD_BALANCE_INFO *lbInfo,
1346 struct IO_REQUEST_INFO *io_info,
1347 struct MR_DRV_RAID_MAP_ALL *drv_map)
1348{
1349 u8 arm_pd;
1350 __le16 devHandle;
1351
1352
1353 arm_pd = megasas_get_best_arm_pd(instance, lbInfo, io_info, drv_map);
1354 devHandle = MR_PdDevHandleGet(arm_pd, drv_map);
1355 io_info->pd_interface = MR_PdInterfaceTypeGet(arm_pd, drv_map);
1356 atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]);
1357
1358 return devHandle;
1359}
1360
