1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41#ifndef _PMC8001_REG_H_
42#define _PMC8001_REG_H_
43
44#include <linux/types.h>
45#include <scsi/libsas.h>
46
47
48#define OPC_INB_ECHO 1
49#define OPC_INB_PHYSTART 4
50#define OPC_INB_PHYSTOP 5
51#define OPC_INB_SSPINIIOSTART 6
52#define OPC_INB_SSPINITMSTART 7
53
54#define OPC_INB_RSVD 8
55#define OPC_INB_DEV_HANDLE_ACCEPT 9
56#define OPC_INB_SSPTGTIOSTART 10
57#define OPC_INB_SSPTGTRSPSTART 11
58
59#define OPC_INB_SSP_ABORT 15
60#define OPC_INB_DEREG_DEV_HANDLE 16
61#define OPC_INB_GET_DEV_HANDLE 17
62#define OPC_INB_SMP_REQUEST 18
63
64#define OPC_INB_SMP_ABORT 20
65
66#define OPC_INB_RSVD1 22
67#define OPC_INB_SATA_HOST_OPSTART 23
68#define OPC_INB_SATA_ABORT 24
69#define OPC_INB_LOCAL_PHY_CONTROL 25
70
71#define OPC_INB_RSVD2 26
72#define OPC_INB_FW_FLASH_UPDATE 32
73#define OPC_INB_GPIO 34
74#define OPC_INB_SAS_DIAG_MODE_START_END 35
75#define OPC_INB_SAS_DIAG_EXECUTE 36
76
77#define OPC_INB_RSVD3 37
78#define OPC_INB_GET_TIME_STAMP 38
79#define OPC_INB_PORT_CONTROL 39
80#define OPC_INB_GET_NVMD_DATA 40
81#define OPC_INB_SET_NVMD_DATA 41
82#define OPC_INB_SET_DEVICE_STATE 42
83#define OPC_INB_GET_DEVICE_STATE 43
84#define OPC_INB_SET_DEV_INFO 44
85
86#define OPC_INB_RSVD4 45
87#define OPC_INB_SGPIO_REGISTER 46
88#define OPC_INB_PCIE_DIAG_EXEC 47
89#define OPC_INB_SET_CONTROLLER_CONFIG 48
90#define OPC_INB_GET_CONTROLLER_CONFIG 49
91#define OPC_INB_REG_DEV 50
92#define OPC_INB_SAS_HW_EVENT_ACK 51
93#define OPC_INB_GET_DEVICE_INFO 52
94#define OPC_INB_GET_PHY_PROFILE 53
95#define OPC_INB_FLASH_OP_EXT 54
96#define OPC_INB_SET_PHY_PROFILE 55
97#define OPC_INB_KEK_MANAGEMENT 256
98#define OPC_INB_DEK_MANAGEMENT 257
99#define OPC_INB_SSP_INI_DIF_ENC_IO 258
100#define OPC_INB_SATA_DIF_ENC_IO 259
101
102
103#define OPC_OUB_ECHO 1
104#define OPC_OUB_RSVD 4
105#define OPC_OUB_SSP_COMP 5
106#define OPC_OUB_SMP_COMP 6
107#define OPC_OUB_LOCAL_PHY_CNTRL 7
108#define OPC_OUB_RSVD1 10
109#define OPC_OUB_DEREG_DEV 11
110#define OPC_OUB_GET_DEV_HANDLE 12
111#define OPC_OUB_SATA_COMP 13
112#define OPC_OUB_SATA_EVENT 14
113#define OPC_OUB_SSP_EVENT 15
114#define OPC_OUB_RSVD2 16
115
116#define OPC_OUB_SSP_RECV_EVENT 18
117#define OPC_OUB_RSVD3 19
118#define OPC_OUB_FW_FLASH_UPDATE 20
119#define OPC_OUB_GPIO_RESPONSE 22
120#define OPC_OUB_GPIO_EVENT 23
121#define OPC_OUB_GENERAL_EVENT 24
122#define OPC_OUB_SSP_ABORT_RSP 26
123#define OPC_OUB_SATA_ABORT_RSP 27
124#define OPC_OUB_SAS_DIAG_MODE_START_END 28
125#define OPC_OUB_SAS_DIAG_EXECUTE 29
126#define OPC_OUB_GET_TIME_STAMP 30
127#define OPC_OUB_RSVD4 31
128#define OPC_OUB_PORT_CONTROL 32
129#define OPC_OUB_SKIP_ENTRY 33
130#define OPC_OUB_SMP_ABORT_RSP 34
131#define OPC_OUB_GET_NVMD_DATA 35
132#define OPC_OUB_SET_NVMD_DATA 36
133#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37
134#define OPC_OUB_SET_DEVICE_STATE 38
135#define OPC_OUB_GET_DEVICE_STATE 39
136#define OPC_OUB_SET_DEV_INFO 40
137#define OPC_OUB_RSVD5 41
138#define OPC_OUB_HW_EVENT 1792
139#define OPC_OUB_DEV_HANDLE_ARRIV 1824
140#define OPC_OUB_THERM_HW_EVENT 1840
141#define OPC_OUB_SGPIO_RESP 2094
142#define OPC_OUB_PCIE_DIAG_EXECUTE 2095
143#define OPC_OUB_DEV_REGIST 2098
144#define OPC_OUB_SAS_HW_EVENT_ACK 2099
145#define OPC_OUB_GET_DEVICE_INFO 2100
146
147#define OPC_OUB_PHY_START_RESP 2052
148#define OPC_OUB_PHY_STOP_RESP 2053
149#define OPC_OUB_SET_CONTROLLER_CONFIG 2096
150#define OPC_OUB_GET_CONTROLLER_CONFIG 2097
151#define OPC_OUB_GET_PHY_PROFILE 2101
152#define OPC_OUB_FLASH_OP_EXT 2102
153#define OPC_OUB_SET_PHY_PROFILE 2103
154#define OPC_OUB_KEK_MANAGEMENT_RESP 2304
155#define OPC_OUB_DEK_MANAGEMENT_RESP 2305
156#define OPC_OUB_SSP_COALESCED_COMP_RESP 2306
157
158
159#define SSC_DISABLE_15 (0x01 << 16)
160#define SSC_DISABLE_30 (0x02 << 16)
161#define SSC_DISABLE_60 (0x04 << 16)
162#define SAS_ASE (0x01 << 15)
163#define SPINHOLD_DISABLE (0x00 << 14)
164#define SPINHOLD_ENABLE (0x01 << 14)
165#define LINKMODE_SAS (0x01 << 12)
166#define LINKMODE_DSATA (0x02 << 12)
167#define LINKMODE_AUTO (0x03 << 12)
168#define LINKRATE_15 (0x01 << 8)
169#define LINKRATE_30 (0x02 << 8)
170#define LINKRATE_60 (0x04 << 8)
171#define LINKRATE_120 (0x08 << 8)
172
173
174#define PHY_STOP_SUCCESS 0x00
175#define PHY_STOP_ERR_DEVICE_ATTACHED 0x1046
176
177
178#define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
179#define PHY_DWORD_LENGTH 0xC
180
181
182#define THERMAL_ENABLE 0x1
183#define THERMAL_LOG_ENABLE 0x1
184#define THERMAL_PAGE_CODE_7H 0x6
185#define THERMAL_PAGE_CODE_8H 0x7
186#define LTEMPHIL 70
187#define RTEMPHIL 100
188
189
190#define SCRATCH_PAD3_ENC_DISABLED 0x00000000
191#define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
192#define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
193#define SCRATCH_PAD3_ENC_READY 0x00000003
194#define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
195
196#define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
197#define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
198#define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
199#define SCRATCH_PAD3_SMF_ENABLED 0
200#define SCRATCH_PAD3_SM_MASK 0x000000F0
201#define SCRATCH_PAD3_ERR_CODE 0x00FF0000
202
203#define SEC_MODE_SMF 0x0
204#define SEC_MODE_SMA 0x100
205#define SEC_MODE_SMB 0x200
206#define CIPHER_MODE_ECB 0x00000001
207#define CIPHER_MODE_XTS 0x00000002
208#define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
209
210
211#define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
212#define STP_MCT_TMO 32
213#define SSP_MCT_TMO 32
214#define SAS_MAX_OPEN_TIME 5
215#define SMP_MAX_CONN_TIMER 0xFF
216#define STP_FRM_TIMER 0
217#define STP_IDLE_TIME 5
218#define SAS_MFD 0
219#define SAS_OPNRJT_RTRY_INTVL 2
220#define SAS_DOPNRJT_RTRY_TMO 128
221#define SAS_COPNRJT_RTRY_TMO 128
222
223
224
225
226
227
228#define SAS_DOPNRJT_RTRY_THR 23438
229#define SAS_COPNRJT_RTRY_THR 23438
230#define SAS_MAX_AIP 0x200000
231#define IT_NEXUS_TIMEOUT 0x7D0
232#define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30)
233
234#ifdef __LITTLE_ENDIAN_BITFIELD
235struct sas_identify_frame_local {
236
237 u8 frame_type:4;
238 u8 dev_type:3;
239 u8 _un0:1;
240
241
242 u8 _un1;
243
244
245 union {
246 struct {
247 u8 _un20:1;
248 u8 smp_iport:1;
249 u8 stp_iport:1;
250 u8 ssp_iport:1;
251 u8 _un247:4;
252 };
253 u8 initiator_bits;
254 };
255
256
257 union {
258 struct {
259 u8 _un30:1;
260 u8 smp_tport:1;
261 u8 stp_tport:1;
262 u8 ssp_tport:1;
263 u8 _un347:4;
264 };
265 u8 target_bits;
266 };
267
268
269 u8 _un4_11[8];
270
271
272 u8 sas_addr[SAS_ADDR_SIZE];
273
274
275 u8 phy_id;
276
277 u8 _un21_27[7];
278
279} __packed;
280
281#elif defined(__BIG_ENDIAN_BITFIELD)
282struct sas_identify_frame_local {
283
284 u8 _un0:1;
285 u8 dev_type:3;
286 u8 frame_type:4;
287
288
289 u8 _un1;
290
291
292 union {
293 struct {
294 u8 _un247:4;
295 u8 ssp_iport:1;
296 u8 stp_iport:1;
297 u8 smp_iport:1;
298 u8 _un20:1;
299 };
300 u8 initiator_bits;
301 };
302
303
304 union {
305 struct {
306 u8 _un347:4;
307 u8 ssp_tport:1;
308 u8 stp_tport:1;
309 u8 smp_tport:1;
310 u8 _un30:1;
311 };
312 u8 target_bits;
313 };
314
315
316 u8 _un4_11[8];
317
318
319 u8 sas_addr[SAS_ADDR_SIZE];
320
321
322 u8 phy_id;
323
324 u8 _un21_27[7];
325} __packed;
326#else
327#error "Bitfield order not defined!"
328#endif
329
330struct mpi_msg_hdr {
331 __le32 header;
332
333
334
335
336
337
338
339
340} __attribute__((packed, aligned(4)));
341
342
343
344
345
346struct phy_start_req {
347 __le32 tag;
348 __le32 ase_sh_lm_slr_phyid;
349 struct sas_identify_frame_local sas_identify;
350 __le32 spasti;
351 u32 reserved[21];
352} __attribute__((packed, aligned(4)));
353
354
355
356
357
358struct phy_stop_req {
359 __le32 tag;
360 __le32 phy_id;
361 u32 reserved[29];
362} __attribute__((packed, aligned(4)));
363
364
365struct set_dev_bits_fis {
366 u8 fis_type;
367 u8 n_i_pmport;
368
369
370
371
372 u8 status;
373 u8 error;
374 u32 _r_a;
375} __attribute__ ((packed));
376
377struct pio_setup_fis {
378 u8 fis_type;
379 u8 i_d_pmPort;
380
381
382
383
384
385
386 u8 status;
387 u8 error;
388 u8 lbal;
389 u8 lbam;
390 u8 lbah;
391 u8 device;
392 u8 lbal_exp;
393 u8 lbam_exp;
394 u8 lbah_exp;
395 u8 _r_a;
396 u8 sector_count;
397 u8 sector_count_exp;
398 u8 _r_b;
399 u8 e_status;
400 u8 _r_c[2];
401 u8 transfer_count;
402} __attribute__ ((packed));
403
404
405
406
407
408struct sata_completion_resp {
409 __le32 tag;
410 __le32 status;
411 __le32 param;
412 u32 sata_resp[12];
413} __attribute__((packed, aligned(4)));
414
415
416
417
418
419
420
421struct hw_event_resp {
422 __le32 lr_status_evt_portid;
423 __le32 evt_param;
424 __le32 phyid_npip_portstate;
425 struct sas_identify_frame sas_identify;
426 struct dev_to_host_fis sata_fis;
427} __attribute__((packed, aligned(4)));
428
429
430
431
432
433struct thermal_hw_event {
434 __le32 thermal_event;
435 __le32 rht_lht;
436} __attribute__((packed, aligned(4)));
437
438
439
440
441
442
443struct reg_dev_req {
444 __le32 tag;
445 __le32 phyid_portid;
446 __le32 dtype_dlr_mcn_ir_retry;
447 __le32 firstburstsize_ITNexustimeout;
448 u8 sas_addr[SAS_ADDR_SIZE];
449 __le32 upper_device_id;
450 u32 reserved[24];
451} __attribute__((packed, aligned(4)));
452
453
454
455
456
457
458
459struct dereg_dev_req {
460 __le32 tag;
461 __le32 device_id;
462 u32 reserved[29];
463} __attribute__((packed, aligned(4)));
464
465
466
467
468
469struct dev_reg_resp {
470 __le32 tag;
471 __le32 status;
472 __le32 device_id;
473 u32 reserved[12];
474} __attribute__((packed, aligned(4)));
475
476
477
478
479
480struct local_phy_ctl_req {
481 __le32 tag;
482 __le32 phyop_phyid;
483 u32 reserved1[29];
484} __attribute__((packed, aligned(4)));
485
486
487
488
489
490 struct local_phy_ctl_resp {
491 __le32 tag;
492 __le32 phyop_phyid;
493 __le32 status;
494 u32 reserved[12];
495} __attribute__((packed, aligned(4)));
496
497#define OP_BITS 0x0000FF00
498#define ID_BITS 0x000000FF
499
500
501
502
503
504
505struct port_ctl_req {
506 __le32 tag;
507 __le32 portop_portid;
508 __le32 param0;
509 __le32 param1;
510 u32 reserved1[27];
511} __attribute__((packed, aligned(4)));
512
513
514
515
516
517struct hw_event_ack_req {
518 __le32 tag;
519 __le32 phyid_sea_portid;
520 __le32 param0;
521 __le32 param1;
522 u32 reserved1[27];
523} __attribute__((packed, aligned(4)));
524
525
526
527
528
529struct phy_start_resp {
530 __le32 tag;
531 __le32 status;
532 __le32 phyid;
533 u32 reserved[12];
534} __attribute__((packed, aligned(4)));
535
536
537
538
539
540struct phy_stop_resp {
541 __le32 tag;
542 __le32 status;
543 __le32 phyid;
544 u32 reserved[12];
545} __attribute__((packed, aligned(4)));
546
547
548
549
550
551struct ssp_completion_resp {
552 __le32 tag;
553 __le32 status;
554 __le32 param;
555 __le32 ssptag_rescv_rescpad;
556 struct ssp_response_iu ssp_resp_iu;
557 __le32 residual_count;
558} __attribute__((packed, aligned(4)));
559
560#define SSP_RESCV_BIT 0x00010000
561
562
563
564
565
566struct sata_event_resp {
567 __le32 tag;
568 __le32 event;
569 __le32 port_id;
570 __le32 device_id;
571 u32 reserved;
572 __le32 event_param0;
573 __le32 event_param1;
574 __le32 sata_addr_h32;
575 __le32 sata_addr_l32;
576 __le32 e_udt1_udt0_crc;
577 __le32 e_udt5_udt4_udt3_udt2;
578 __le32 a_udt1_udt0_crc;
579 __le32 a_udt5_udt4_udt3_udt2;
580 __le32 hwdevid_diferr;
581 __le32 err_framelen_byteoffset;
582 __le32 err_dataframe;
583} __attribute__((packed, aligned(4)));
584
585
586
587
588
589struct ssp_event_resp {
590 __le32 tag;
591 __le32 event;
592 __le32 port_id;
593 __le32 device_id;
594 __le32 ssp_tag;
595 __le32 event_param0;
596 __le32 event_param1;
597 __le32 sas_addr_h32;
598 __le32 sas_addr_l32;
599 __le32 e_udt1_udt0_crc;
600 __le32 e_udt5_udt4_udt3_udt2;
601 __le32 a_udt1_udt0_crc;
602 __le32 a_udt5_udt4_udt3_udt2;
603 __le32 hwdevid_diferr;
604 __le32 err_framelen_byteoffset;
605 __le32 err_dataframe;
606} __attribute__((packed, aligned(4)));
607
608
609
610
611
612struct general_event_resp {
613 __le32 status;
614 __le32 inb_IOMB_payload[14];
615} __attribute__((packed, aligned(4)));
616
617#define GENERAL_EVENT_PAYLOAD 14
618#define OPCODE_BITS 0x00000fff
619
620
621
622
623
624struct smp_req {
625 __le32 tag;
626 __le32 device_id;
627 __le32 len_ip_ir;
628
629
630
631
632
633 u8 smp_req16[16];
634 union {
635 u8 smp_req[32];
636 struct {
637 __le64 long_req_addr;
638 __le32 long_req_size;
639 u32 _r_a;
640 __le64 long_resp_addr;
641 __le32 long_resp_size;
642 u32 _r_b;
643 } long_smp_req;
644 };
645 __le32 rsvd[16];
646} __attribute__((packed, aligned(4)));
647
648
649
650
651struct smp_completion_resp {
652 __le32 tag;
653 __le32 status;
654 __le32 param;
655 u8 _r_a[252];
656} __attribute__((packed, aligned(4)));
657
658
659
660
661
662struct task_abort_req {
663 __le32 tag;
664 __le32 device_id;
665 __le32 tag_to_abort;
666 __le32 abort_all;
667 u32 reserved[27];
668} __attribute__((packed, aligned(4)));
669
670
671#define ABORT_MASK 0x3
672#define ABORT_SINGLE 0x0
673#define ABORT_ALL 0x1
674
675
676
677
678
679struct task_abort_resp {
680 __le32 tag;
681 __le32 status;
682 __le32 scp;
683 u32 reserved[12];
684} __attribute__((packed, aligned(4)));
685
686
687
688
689
690struct sas_diag_start_end_req {
691 __le32 tag;
692 __le32 operation_phyid;
693 u32 reserved[29];
694} __attribute__((packed, aligned(4)));
695
696
697
698
699
700struct sas_diag_execute_req {
701 __le32 tag;
702 __le32 cmdtype_cmddesc_phyid;
703 __le32 pat1_pat2;
704 __le32 threshold;
705 __le32 codepat_errmsk;
706 __le32 pmon;
707 __le32 pERF1CTL;
708 u32 reserved[24];
709} __attribute__((packed, aligned(4)));
710
711#define SAS_DIAG_PARAM_BYTES 24
712
713
714
715
716
717struct set_dev_state_req {
718 __le32 tag;
719 __le32 device_id;
720 __le32 nds;
721 u32 reserved[28];
722} __attribute__((packed, aligned(4)));
723
724
725
726
727
728
729
730struct sata_start_req {
731 __le32 tag;
732 __le32 device_id;
733 __le32 data_len;
734 __le32 ncqtag_atap_dir_m_dad;
735 struct host_to_dev_fis sata_fis;
736 u32 reserved1;
737 u32 reserved2;
738
739 u32 addr_low;
740 u32 addr_high;
741 __le32 len;
742
743 __le32 esgl;
744 __le32 atapi_scsi_cdb[4];
745
746 __le32 key_index_mode;
747 __le32 sector_cnt_enss;
748 __le32 keytagl;
749 __le32 keytagh;
750 __le32 twk_val0;
751 __le32 twk_val1;
752 __le32 twk_val2;
753 __le32 twk_val3;
754 __le32 enc_addr_low;
755 __le32 enc_addr_high;
756 __le32 enc_len;
757 __le32 enc_esgl;
758} __attribute__((packed, aligned(4)));
759
760
761
762
763
764struct ssp_ini_tm_start_req {
765 __le32 tag;
766 __le32 device_id;
767 __le32 relate_tag;
768 __le32 tmf;
769 u8 lun[8];
770 __le32 ds_ads_m;
771 u32 reserved[24];
772} __attribute__((packed, aligned(4)));
773
774struct ssp_info_unit {
775 u8 lun[8];
776 u8 reserved1;
777 u8 efb_prio_attr;
778
779
780
781 u8 reserved2;
782 u8 additional_cdb_len;
783
784
785 u8 cdb[16];
786} __attribute__((packed, aligned(4)));
787
788
789
790
791
792
793struct ssp_ini_io_start_req {
794 __le32 tag;
795 __le32 device_id;
796 __le32 data_len;
797 __le32 dad_dir_m_tlr;
798 struct ssp_info_unit ssp_iu;
799 __le32 addr_low;
800
801 __le32 addr_high;
802
803 __le32 len;
804
805 __le32 esgl;
806
807
808 u8 udt[12];
809 __le32 sectcnt_ios;
810 __le32 key_cmode;
811 __le32 ks_enss;
812 __le32 keytagl;
813 __le32 keytagh;
814 __le32 twk_val0;
815 __le32 twk_val1;
816 __le32 twk_val2;
817 __le32 twk_val3;
818 __le32 enc_addr_low;
819 __le32 enc_addr_high;
820 __le32 enc_len;
821 __le32 enc_esgl;
822} __attribute__((packed, aligned(4)));
823
824
825
826
827
828struct ssp_dif_enc_io_req {
829 __le32 tag;
830 __le32 device_id;
831 __le32 data_len;
832 __le32 dirMTlr;
833 __le32 sspiu0;
834 __le32 sspiu1;
835 __le32 sspiu2;
836 __le32 sspiu3;
837 __le32 sspiu4;
838 __le32 sspiu5;
839 __le32 sspiu6;
840 __le32 epl_des;
841 __le32 dpl_desl_ndplr;
842 __le32 dpl_desh;
843 __le32 uum_uuv_bss_difbits;
844 u8 udt[12];
845 __le32 sectcnt_ios;
846 __le32 key_cmode;
847 __le32 ks_enss;
848 __le32 keytagl;
849 __le32 keytagh;
850 __le32 twk_val0;
851 __le32 twk_val1;
852 __le32 twk_val2;
853 __le32 twk_val3;
854 __le32 addr_low;
855 __le32 addr_high;
856 __le32 len;
857 __le32 esgl;
858} __attribute__((packed, aligned(4)));
859
860
861
862
863
864struct fw_flash_Update_req {
865 __le32 tag;
866 __le32 cur_image_offset;
867 __le32 cur_image_len;
868 __le32 total_image_len;
869 u32 reserved0[7];
870 __le32 sgl_addr_lo;
871 __le32 sgl_addr_hi;
872 __le32 len;
873 __le32 ext_reserved;
874 u32 reserved1[16];
875} __attribute__((packed, aligned(4)));
876
877#define FWFLASH_IOMB_RESERVED_LEN 0x07
878
879
880
881
882
883 struct fw_flash_Update_resp {
884 __le32 tag;
885 __le32 status;
886 u32 reserved[13];
887} __attribute__((packed, aligned(4)));
888
889
890
891
892
893struct get_nvm_data_req {
894 __le32 tag;
895 __le32 len_ir_vpdd;
896 __le32 vpd_offset;
897 u32 reserved[8];
898 __le32 resp_addr_lo;
899 __le32 resp_addr_hi;
900 __le32 resp_len;
901 u32 reserved1[17];
902} __attribute__((packed, aligned(4)));
903
904struct set_nvm_data_req {
905 __le32 tag;
906 __le32 len_ir_vpdd;
907 __le32 vpd_offset;
908 u32 reserved[8];
909 __le32 resp_addr_lo;
910 __le32 resp_addr_hi;
911 __le32 resp_len;
912 u32 reserved1[17];
913} __attribute__((packed, aligned(4)));
914
915
916
917
918
919struct set_ctrl_cfg_req {
920 __le32 tag;
921 __le32 cfg_pg[14];
922 u32 reserved[16];
923} __attribute__((packed, aligned(4)));
924
925
926
927
928
929struct get_ctrl_cfg_req {
930 __le32 tag;
931 __le32 pgcd;
932 __le32 int_vec;
933 u32 reserved[28];
934} __attribute__((packed, aligned(4)));
935
936
937
938
939
940struct kek_mgmt_req {
941 __le32 tag;
942 __le32 new_curidx_ksop;
943 u32 reserved;
944 __le32 kblob[12];
945 u32 reserved1[16];
946} __attribute__((packed, aligned(4)));
947
948
949
950
951
952struct dek_mgmt_req {
953 __le32 tag;
954 __le32 kidx_dsop;
955 __le32 dekidx;
956 __le32 addr_l;
957 __le32 addr_h;
958 __le32 nent;
959 __le32 dbf_tblsize;
960 u32 reserved[24];
961} __attribute__((packed, aligned(4)));
962
963
964
965
966
967struct set_phy_profile_req {
968 __le32 tag;
969 __le32 ppc_phyid;
970 u32 reserved[29];
971} __attribute__((packed, aligned(4)));
972
973
974
975
976
977struct get_phy_profile_req {
978 __le32 tag;
979 __le32 ppc_phyid;
980 __le32 profile[29];
981} __attribute__((packed, aligned(4)));
982
983
984
985
986
987struct ext_flash_partition_req {
988 __le32 tag;
989 __le32 cmd;
990 __le32 offset;
991 __le32 len;
992 u32 reserved[7];
993 __le32 addr_low;
994 __le32 addr_high;
995 __le32 len1;
996 __le32 ext;
997 u32 reserved1[16];
998} __attribute__((packed, aligned(4)));
999
1000#define TWI_DEVICE 0x0
1001#define C_SEEPROM 0x1
1002#define VPD_FLASH 0x4
1003#define AAP1_RDUMP 0x5
1004#define IOP_RDUMP 0x6
1005#define EXPAN_ROM 0x7
1006
1007#define IPMode 0x80000000
1008#define NVMD_TYPE 0x0000000F
1009#define NVMD_STAT 0x0000FFFF
1010#define NVMD_LEN 0xFF000000
1011
1012
1013
1014
1015struct get_nvm_data_resp {
1016 __le32 tag;
1017 __le32 ir_tda_bn_dps_das_nvm;
1018 __le32 dlen_status;
1019 __le32 nvm_data[12];
1020} __attribute__((packed, aligned(4)));
1021
1022
1023
1024
1025
1026
1027struct sas_diag_start_end_resp {
1028 __le32 tag;
1029 __le32 status;
1030 u32 reserved[13];
1031} __attribute__((packed, aligned(4)));
1032
1033
1034
1035
1036
1037
1038struct sas_diag_execute_resp {
1039 __le32 tag;
1040 __le32 cmdtype_cmddesc_phyid;
1041 __le32 Status;
1042 __le32 ReportData;
1043 u32 reserved[11];
1044} __attribute__((packed, aligned(4)));
1045
1046
1047
1048
1049
1050
1051struct set_dev_state_resp {
1052 __le32 tag;
1053 __le32 status;
1054 __le32 device_id;
1055 __le32 pds_nds;
1056 u32 reserved[11];
1057} __attribute__((packed, aligned(4)));
1058
1059
1060
1061
1062
1063
1064struct set_ctrl_cfg_resp {
1065 __le32 tag;
1066 __le32 status;
1067 __le32 err_qlfr_pgcd;
1068 u32 reserved[12];
1069} __attribute__((packed, aligned(4)));
1070
1071struct get_ctrl_cfg_resp {
1072 __le32 tag;
1073 __le32 status;
1074 __le32 err_qlfr;
1075 __le32 confg_page[12];
1076} __attribute__((packed, aligned(4)));
1077
1078struct kek_mgmt_resp {
1079 __le32 tag;
1080 __le32 status;
1081 __le32 kidx_new_curr_ksop;
1082 __le32 err_qlfr;
1083 u32 reserved[11];
1084} __attribute__((packed, aligned(4)));
1085
1086struct dek_mgmt_resp {
1087 __le32 tag;
1088 __le32 status;
1089 __le32 kekidx_tbls_dsop;
1090 __le32 dekidx;
1091 __le32 err_qlfr;
1092 u32 reserved[10];
1093} __attribute__((packed, aligned(4)));
1094
1095struct get_phy_profile_resp {
1096 __le32 tag;
1097 __le32 status;
1098 __le32 ppc_phyid;
1099 __le32 ppc_specific_rsp[12];
1100} __attribute__((packed, aligned(4)));
1101
1102struct flash_op_ext_resp {
1103 __le32 tag;
1104 __le32 cmd;
1105 __le32 status;
1106 __le32 epart_size;
1107 __le32 epart_sect_size;
1108 u32 reserved[10];
1109} __attribute__((packed, aligned(4)));
1110
1111struct set_phy_profile_resp {
1112 __le32 tag;
1113 __le32 status;
1114 __le32 ppc_phyid;
1115 __le32 ppc_specific_rsp[12];
1116} __attribute__((packed, aligned(4)));
1117
1118struct ssp_coalesced_comp_resp {
1119 __le32 coal_cnt;
1120 __le32 tag0;
1121 __le32 ssp_tag0;
1122 __le32 tag1;
1123 __le32 ssp_tag1;
1124 __le32 add_tag_ssp_tag[10];
1125} __attribute__((packed, aligned(4)));
1126
1127
1128
1129
1130
1131
1132struct SASProtocolTimerConfig {
1133 __le32 pageCode;
1134 __le32 MST_MSI;
1135 __le32 STP_SSP_MCT_TMO;
1136 __le32 STP_FRM_TMO;
1137 __le32 STP_IDLE_TMO;
1138 __le32 OPNRJT_RTRY_INTVL;
1139 __le32 Data_Cmd_OPNRJT_RTRY_TMO;
1140 __le32 Data_Cmd_OPNRJT_RTRY_THR;
1141 __le32 MAX_AIP;
1142} __attribute__((packed, aligned(4)));
1143
1144typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1145
1146#define NDS_BITS 0x0F
1147#define PDS_BITS 0xF0
1148
1149
1150
1151
1152
1153#define HW_EVENT_RESET_START 0x01
1154#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1155#define HW_EVENT_PHY_STOP_STATUS 0x03
1156#define HW_EVENT_SAS_PHY_UP 0x04
1157#define HW_EVENT_SATA_PHY_UP 0x05
1158#define HW_EVENT_SATA_SPINUP_HOLD 0x06
1159#define HW_EVENT_PHY_DOWN 0x07
1160#define HW_EVENT_PORT_INVALID 0x08
1161#define HW_EVENT_BROADCAST_CHANGE 0x09
1162#define HW_EVENT_PHY_ERROR 0x0A
1163#define HW_EVENT_BROADCAST_SES 0x0B
1164#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1165#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1166#define HW_EVENT_MALFUNCTION 0x0E
1167#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1168#define HW_EVENT_BROADCAST_EXP 0x10
1169#define HW_EVENT_PHY_START_STATUS 0x11
1170#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1171#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1172#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1173#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1174#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1175#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1176#define HW_EVENT_PORT_RECOVER 0x18
1177#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1178#define HW_EVENT_PORT_RESET_COMPLETE 0x20
1179#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1180
1181
1182#define PORT_NOT_ESTABLISHED 0x00
1183#define PORT_VALID 0x01
1184#define PORT_LOSTCOMM 0x02
1185#define PORT_IN_RESET 0x04
1186#define PORT_3RD_PARTY_RESET 0x07
1187#define PORT_INVALID 0x08
1188
1189
1190
1191
1192
1193#define IO_SUCCESS 0x00
1194#define IO_ABORTED 0x01
1195#define IO_OVERFLOW 0x02
1196#define IO_UNDERFLOW 0x03
1197#define IO_FAILED 0x04
1198#define IO_ABORT_RESET 0x05
1199#define IO_NOT_VALID 0x06
1200#define IO_NO_DEVICE 0x07
1201#define IO_ILLEGAL_PARAMETER 0x08
1202#define IO_LINK_FAILURE 0x09
1203#define IO_PROG_ERROR 0x0A
1204
1205#define IO_EDC_IN_ERROR 0x0B
1206#define IO_EDC_OUT_ERROR 0x0C
1207#define IO_ERROR_HW_TIMEOUT 0x0D
1208#define IO_XFER_ERROR_BREAK 0x0E
1209#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1210#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1211#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1212#define IO_OPEN_CNX_ERROR_BREAK 0x12
1213#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1214#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1215#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1216#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1217#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1218
1219#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1220#define IO_XFER_ERROR_NAK_RECEIVED 0x19
1221#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1222#define IO_XFER_ERROR_PEER_ABORTED 0x1B
1223#define IO_XFER_ERROR_RX_FRAME 0x1C
1224#define IO_XFER_ERROR_DMA 0x1D
1225#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1226#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1227#define IO_XFER_ERROR_SATA 0x20
1228
1229
1230#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1231#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1232#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1233#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1234
1235#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1236#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1237#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1238#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1239#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1240
1241
1242#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1243#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1244
1245#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1246#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1247#define IO_XFER_CMD_FRAME_ISSUED 0x36
1248#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1249#define IO_PORT_IN_RESET 0x38
1250#define IO_DS_NON_OPERATIONAL 0x39
1251#define IO_DS_IN_RECOVERY 0x3A
1252#define IO_TM_TAG_NOT_FOUND 0x3B
1253#define IO_XFER_PIO_SETUP_ERROR 0x3C
1254#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1255#define IO_DS_IN_ERROR 0x3E
1256#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1257#define IO_ABORT_IN_PROGRESS 0x40
1258#define IO_ABORT_DELAYED 0x41
1259#define IO_INVALID_LENGTH 0x42
1260
1261
1262
1263#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1264#define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1265#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1266#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1267#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1268#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1269#define IO_DS_INVALID 0x49
1270
1271#define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1272#define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
1273#define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
1274#define MPI_IO_RQE_BUSY_FULL 0x55
1275#define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1276#define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
1277#define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1278
1279#define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1280#define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1281
1282#define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1283
1284
1285
1286
1287
1288#define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1289#define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1290
1291
1292
1293
1294#define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1295
1296
1297#define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1298
1299
1300#define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1301
1302
1303
1304
1305
1306#define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1307
1308
1309#define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1310#define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1311#define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1312#define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1313
1314
1315#define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1316#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1317#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1318#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1319#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1320#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1321#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1322
1323
1324
1325
1326
1327
1328#define IO_ERROR_UNKNOWN_GENERIC 0x2023
1329
1330
1331
1332#define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
1333#define SPCv_MSGU_CFG_TABLE_RESET 0x002
1334#define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
1335#define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
1336#define MSGU_IBDB_SET 0x00
1337#define MSGU_HOST_INT_STATUS 0x08
1338#define MSGU_HOST_INT_MASK 0x0C
1339#define MSGU_IOPIB_INT_STATUS 0x18
1340#define MSGU_IOPIB_INT_MASK 0x1C
1341#define MSGU_IBDB_CLEAR 0x20
1342
1343#define MSGU_MSGU_CONTROL 0x24
1344#define MSGU_ODR 0x20
1345#define MSGU_ODCR 0x28
1346
1347#define MSGU_ODMR 0x30
1348#define MSGU_ODMR_U 0x34
1349#define MSGU_ODMR_CLR 0x38
1350#define MSGU_ODMR_CLR_U 0x3C
1351#define MSGU_OD_RSVD 0x40
1352
1353#define MSGU_SCRATCH_PAD_0 0x44
1354#define MSGU_SCRATCH_PAD_1 0x48
1355#define MSGU_SCRATCH_PAD_2 0x4C
1356#define MSGU_SCRATCH_PAD_3 0x50
1357#define MSGU_HOST_SCRATCH_PAD_0 0x54
1358#define MSGU_HOST_SCRATCH_PAD_1 0x58
1359#define MSGU_HOST_SCRATCH_PAD_2 0x5C
1360#define MSGU_HOST_SCRATCH_PAD_3 0x60
1361#define MSGU_HOST_SCRATCH_PAD_4 0x64
1362#define MSGU_HOST_SCRATCH_PAD_5 0x68
1363#define MSGU_HOST_SCRATCH_PAD_6 0x6C
1364#define MSGU_HOST_SCRATCH_PAD_7 0x70
1365
1366
1367#define ODMR_MASK_ALL 0xFFFFFFFF
1368
1369#define ODMR_CLEAR_ALL 0
1370
1371
1372#define ODCR_CLEAR_ALL 0xFFFFFFFF
1373
1374
1375#define MSIX_TABLE_OFFSET 0x2000
1376#define MSIX_TABLE_ELEMENT_SIZE 0x10
1377#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1378#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
1379 MSIX_INTERRUPT_CONTROL_OFFSET)
1380#define MSIX_INTERRUPT_DISABLE 0x1
1381#define MSIX_INTERRUPT_ENABLE 0x0
1382
1383
1384#define SCRATCH_PAD_RAAE_READY 0x3
1385#define SCRATCH_PAD_ILA_READY 0xC
1386#define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1387#define SCRATCH_PAD_IOP0_READY 0xC00
1388#define SCRATCH_PAD_IOP1_READY 0x3000
1389#define SCRATCH_PAD_MIPSALL_READY (SCRATCH_PAD_IOP1_READY | \
1390 SCRATCH_PAD_IOP0_READY | \
1391 SCRATCH_PAD_RAAE_READY)
1392
1393
1394#define SCRATCH_PAD1_BOOTSTATE_MASK 0x70
1395#define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0
1396#define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10
1397#define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20
1398#define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30
1399#define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40
1400#define SCRATCH_PAD1_BOOTSTATE_R1 0x50
1401#define SCRATCH_PAD1_BOOTSTATE_R2 0x60
1402#define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70
1403
1404
1405#define SCRATCH_PAD2_POR 0x00
1406#define SCRATCH_PAD2_SFR 0x01
1407#define SCRATCH_PAD2_ERR 0x02
1408#define SCRATCH_PAD2_RDY 0x03
1409#define SCRATCH_PAD2_FWRDY_RST 0x04
1410#define SCRATCH_PAD2_IOPRDY_RST 0x08
1411#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4
1412
1413#define SCRATCH_PAD2_RESERVED 0x000003FC
1414
1415
1416#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00
1417#define SCRATCH_PAD_STATE_MASK 0x00000003
1418
1419
1420#define MAIN_SIGNATURE_OFFSET 0x00
1421#define MAIN_INTERFACE_REVISION 0x04
1422#define MAIN_FW_REVISION 0x08
1423#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C
1424#define MAIN_MAX_SGL_OFFSET 0x10
1425#define MAIN_CNTRL_CAP_OFFSET 0x14
1426#define MAIN_GST_OFFSET 0x18
1427#define MAIN_IBQ_OFFSET 0x1C
1428#define MAIN_OBQ_OFFSET 0x20
1429#define MAIN_IQNPPD_HPPD_OFFSET 0x24
1430
1431
1432#define MAIN_EVENT_CRC_CHECK 0x48
1433#define MAIN_EVENT_LOG_ADDR_HI 0x50
1434#define MAIN_EVENT_LOG_ADDR_LO 0x54
1435#define MAIN_EVENT_LOG_BUFF_SIZE 0x58
1436#define MAIN_EVENT_LOG_OPTION 0x5C
1437#define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60
1438#define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64
1439#define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68
1440#define MAIN_PCS_EVENT_LOG_OPTION 0x6C
1441#define MAIN_FATAL_ERROR_INTERRUPT 0x70
1442#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74
1443#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78
1444#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C
1445#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80
1446#define MAIN_GPIO_LED_FLAGS_OFFSET 0x84
1447#define MAIN_ANALOG_SETUP_OFFSET 0x88
1448
1449#define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C
1450#define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90
1451#define MAIN_PORT_RECOVERY_TIMER 0x94
1452#define MAIN_INT_REASSERTION_DELAY 0x98
1453#define MAIN_MPI_ILA_RELEASE_TYPE 0xA4
1454#define MAIN_MPI_INACTIVE_FW_VERSION 0XB0
1455
1456
1457#define GST_GSTLEN_MPIS_OFFSET 0x00
1458#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1459#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1460#define GST_MSGUTCNT_OFFSET 0x0C
1461#define GST_IOPTCNT_OFFSET 0x10
1462
1463#define GST_GPIO_INPUT_VAL 0x38
1464
1465#define GST_RERRINFO_OFFSET0 0x44
1466#define GST_RERRINFO_OFFSET1 0x48
1467#define GST_RERRINFO_OFFSET2 0x4c
1468#define GST_RERRINFO_OFFSET3 0x50
1469#define GST_RERRINFO_OFFSET4 0x54
1470#define GST_RERRINFO_OFFSET5 0x58
1471#define GST_RERRINFO_OFFSET6 0x5c
1472#define GST_RERRINFO_OFFSET7 0x60
1473
1474
1475#define GST_MPI_STATE_UNINIT 0x00
1476#define GST_MPI_STATE_INIT 0x01
1477#define GST_MPI_STATE_TERMINATION 0x02
1478#define GST_MPI_STATE_ERROR 0x03
1479#define GST_MPI_STATE_MASK 0x07
1480
1481
1482
1483#define PSPA_PHYSTATE0_OFFSET 0x00
1484#define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04
1485#define PSPA_PHYSTATE1_OFFSET 0x08
1486#define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C
1487#define PSPA_PHYSTATE2_OFFSET 0x10
1488#define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14
1489#define PSPA_PHYSTATE3_OFFSET 0x18
1490#define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C
1491#define PSPA_PHYSTATE4_OFFSET 0x20
1492#define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24
1493#define PSPA_PHYSTATE5_OFFSET 0x28
1494#define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C
1495#define PSPA_PHYSTATE6_OFFSET 0x30
1496#define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34
1497#define PSPA_PHYSTATE7_OFFSET 0x38
1498#define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C
1499#define PSPA_PHYSTATE8_OFFSET 0x40
1500#define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44
1501#define PSPA_PHYSTATE9_OFFSET 0x48
1502#define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C
1503#define PSPA_PHYSTATE10_OFFSET 0x50
1504#define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54
1505#define PSPA_PHYSTATE11_OFFSET 0x58
1506#define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C
1507#define PSPA_PHYSTATE12_OFFSET 0x60
1508#define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64
1509#define PSPA_PHYSTATE13_OFFSET 0x68
1510#define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c
1511#define PSPA_PHYSTATE14_OFFSET 0x70
1512#define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74
1513#define PSPA_PHYSTATE15_OFFSET 0x78
1514#define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c
1515
1516
1517
1518#define IB_PROPERITY_OFFSET 0x00
1519#define IB_BASE_ADDR_HI_OFFSET 0x04
1520#define IB_BASE_ADDR_LO_OFFSET 0x08
1521#define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1522#define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1523#define IB_PIPCI_BAR 0x14
1524#define IB_PIPCI_BAR_OFFSET 0x18
1525#define IB_RESERVED_OFFSET 0x1C
1526
1527
1528#define OB_PROPERITY_OFFSET 0x00
1529#define OB_BASE_ADDR_HI_OFFSET 0x04
1530#define OB_BASE_ADDR_LO_OFFSET 0x08
1531#define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1532#define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1533#define OB_CIPCI_BAR 0x14
1534#define OB_CIPCI_BAR_OFFSET 0x18
1535#define OB_INTERRUPT_COALES_OFFSET 0x1C
1536#define OB_DYNAMIC_COALES_OFFSET 0x20
1537#define OB_PROPERTY_INT_ENABLE 0x40000000
1538
1539#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1540#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1541
1542#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1543#define PCIE_EVENT_INTERRUPT 0x003044
1544#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1545#define PCIE_ERROR_INTERRUPT 0x00304C
1546
1547
1548#define SPC_REG_SOFT_RESET 0x00001000
1549#define SPCv_NORMAL_RESET_VALUE 0x1
1550
1551#define SPCv_SOFT_RESET_READ_MASK 0xC0
1552#define SPCv_SOFT_RESET_NO_RESET 0x0
1553#define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1554#define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1555#define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1556
1557
1558#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1559
1560
1561
1562#define SPC_REG_RESET 0x000000
1563
1564
1565#define SPC_REG_RESET_OSSP 0x00000001
1566#define SPC_REG_RESET_RAAE 0x00000002
1567#define SPC_REG_RESET_PCS_SPBC 0x00000004
1568#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1569#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1570#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1571#define SPC_REG_RESET_PCS_LM 0x00000040
1572#define SPC_REG_RESET_PCS 0x00000080
1573#define SPC_REG_RESET_GSM 0x00000100
1574#define SPC_REG_RESET_DDR2 0x00010000
1575#define SPC_REG_RESET_BDMA_CORE 0x00020000
1576#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1577#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1578#define SPC_REG_RESET_PCIE_PWR 0x00100000
1579#define SPC_REG_RESET_PCIE_SFT 0x00200000
1580#define SPC_REG_RESET_PCS_SXCBI 0x00400000
1581#define SPC_REG_RESET_LMS_SXCBI 0x00800000
1582#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1583#define SPC_REG_RESET_PMIC_CORE 0x02000000
1584#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1585#define SPC_REG_RESET_DEVICE 0x80000000
1586
1587
1588#define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1589
1590#define MBIC_AAP1_ADDR_BASE 0x060000
1591#define MBIC_IOP_ADDR_BASE 0x070000
1592#define GSM_ADDR_BASE 0x0700000
1593
1594#define GSM_CONFIG_RESET 0x00000000
1595#define RAM_ECC_DB_ERR 0x00000018
1596#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1597#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1598#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1599#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1600#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1601#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1602
1603#define RB6_ACCESS_REG 0x6A0000
1604#define HDAC_EXEC_CMD 0x0002
1605#define HDA_C_PA 0xcb
1606#define HDA_SEQ_ID_BITS 0x00ff0000
1607#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1608#define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1609#define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1610
1611#define MBIC_AAP1_ADDR_BASE 0x060000
1612#define MBIC_IOP_ADDR_BASE 0x070000
1613#define GSM_ADDR_BASE 0x0700000
1614#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1615#define GSM_CONFIG_RESET_VALUE 0x00003b00
1616#define GPIO_ADDR_BASE 0x00090000
1617#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1618
1619
1620#define SPC_RB6_OFFSET 0x80C0
1621
1622#define RB6_MAGIC_NUMBER_RST 0x1234
1623
1624
1625#define DEVREG_SUCCESS 0x00
1626#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1627#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1628#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1629#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1630#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1631#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1632#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1633
1634
1635#define MEMBASE_II_SHIFT_REGISTER 0x1010
1636#endif
1637